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authorJan Sommer <jan.sommer@dlr.de>2020-05-31 16:22:53 +0200
committerChris Johns <chrisj@rtems.org>2020-06-11 13:28:55 +1000
commit85d6a760f57e6f53c72cf8d15be20e3e4eaf4734 (patch)
tree21f2a8582414ad8810c8a52e553d27e1a790d9f1 /cpukit/score/cpu/i386
parentbsp/pc386: Turn start16.S into a startAP.S (diff)
downloadrtems-85d6a760f57e6f53c72cf8d15be20e3e4eaf4734.tar.bz2
bsp/pc386: Update GDT to work for SMP
Create a GS segment in the GDT for each processor for storing TLS. This makes the GDT in startAP.S obsolete as all processors now share the same GDT, which is passed to each AP at startup. The correct segment for each processor is calculated in cpu_asm.S. Update #3335
Diffstat (limited to 'cpukit/score/cpu/i386')
-rw-r--r--cpukit/score/cpu/i386/cpu_asm.S11
-rw-r--r--cpukit/score/cpu/i386/include/rtems/asm.h26
2 files changed, 32 insertions, 5 deletions
diff --git a/cpukit/score/cpu/i386/cpu_asm.S b/cpukit/score/cpu/i386/cpu_asm.S
index 6b609ab4ce..9e1e848bbd 100644
--- a/cpukit/score/cpu/i386/cpu_asm.S
+++ b/cpukit/score/cpu/i386/cpu_asm.S
@@ -85,12 +85,13 @@ restore:
movl REG_EBX(eax),ebx /* restore ebx */
movl REG_ESI(eax),esi /* restore source register */
movl REG_EDI(eax),edi /* restore destination register */
- movl REG_GS_0(eax), ecx /* restore gs segment */
+ GET_CPU_ID ecx
+ movl REG_GS_0(eax), edx /* restore gs segment */
+ movl edx, _Global_descriptor_table+24(,ecx,8)
movl REG_GS_1(eax), edx
- movl ecx, _Global_descriptor_table + 24
- movl edx, _Global_descriptor_table + 28
- movl $24, ecx
- mov ecx, gs
+ movl edx, _Global_descriptor_table+28(,ecx,8)
+ leal 24(,ecx,8), edx
+ movl edx, gs
ret
/*
diff --git a/cpukit/score/cpu/i386/include/rtems/asm.h b/cpukit/score/cpu/i386/include/rtems/asm.h
index 5db402c930..5856f724de 100644
--- a/cpukit/score/cpu/i386/include/rtems/asm.h
+++ b/cpukit/score/cpu/i386/include/rtems/asm.h
@@ -38,6 +38,7 @@
#endif
#include <rtems/score/cpuopts.h>
#include <rtems/score/i386.h>
+#include <rtems/score/percpu.h>
/**
* @defgroup RTEMSScoreCPUi386ASM i386 Assembler Support
@@ -146,6 +147,31 @@
#define PUBLIC(sym) .globl SYM (sym)
#define EXTERN(sym) .globl SYM (sym)
+#ifdef RTEMS_SMP
+.macro GET_CPU_ID REG
+ .set LAPIC_ID, 0x20
+ .set LAPIC_ID_SHIFT, 0x18L
+ movl imps_lapic_addr,\REG
+ movl LAPIC_ID(\REG),\REG
+ shrl $LAPIC_ID_SHIFT,\REG /* LAPIC_ID in REG */
+ movb imps_apic_cpu_map(\REG),\REG /* CPU ID in REG */
+.endm
+
+.macro GET_SELF_CPU_CONTROL REG
+ GET_CPU_ID \REG
+ shll $PER_CPU_CONTROL_SIZE_LOG2,\REG /* Calculate offset for CPU structure */
+ leal _Per_CPU_Information(\REG),\REG /* Address of info for current CPU in REG */
+.endm
+#else
+.macro GET_CPU_ID REG
+ movl $0,\REG
+.endm
+
+.macro GET_SELF_CPU_CONTROL REG
+ leal _Per_CPU_Information, \REG
+.endm
+#endif
+
/**@}**/
#endif