Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step.  It
copied header files from arbitrary locations into the build tree.  The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

* The make preinstall step itself needs time and disk space.

* Errors in header files show up in the build tree copy.  This makes it
  hard for editors to open the right file to fix the error.

* There is no clear relationship between source and build tree header
  files.  This makes an audit of the build process difficult.

* The visibility of all header files in the build tree makes it
  difficult to enforce API barriers.  For example it is discouraged to
  use BSP-specifics in the cpukit.

* An introduction of a new build system is difficult.

* Include paths specified by the -B option are system headers.  This
  may suppress warnings.

* The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step.   All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc.  Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

* cpukit/include

* cpukit/score/cpu/@RTEMS_CPU@/include

* cpukit/libnetworking

The new BSP include directories are:

* bsps/include

* bsps/@RTEMS_CPU@/include

* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed.  The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

10 files changed, 1890 insertions, 0 deletions

diff --git a/cpukit/score/cpu/i386/include/machine/elf_machdep.h b/cpukit/score/cpu/i386/include/machine/elf_machdep.h
new file mode 100644
index 0000000000..442c561a9c
--- /dev/null
+++ b/cpukit/score/cpu/i386/include/machine/elf_machdep.h
@@ -0,0 +1,63 @@
+/*	$NetBSD: elf_machdep.h,v 1.10 2009/05/30 05:56:52 skrll Exp $	*/
+
+#define	ELF32_MACHDEP_ENDIANNESS	ELFDATA2LSB
+#define	ELF32_MACHDEP_ID_CASES						\
+		case EM_386:						\
+		case EM_486:						\
+			break;
+
+#define	ELF64_MACHDEP_ENDIANNESS	XXX	/* break compilation */
+#define	ELF64_MACHDEP_ID_CASES						\
+		/* no 64-bit ELF machine types supported */
+
+#define	ELF32_MACHDEP_ID		EM_386
+
+#define ARCH_ELFSIZE		32	/* MD native binary size */
+
+/* i386 relocations */
+#define	R_386_NONE	0
+#define	R_386_32	1
+#define	R_386_PC32	2
+#define	R_386_GOT32	3
+#define	R_386_PLT32	4
+#define	R_386_COPY	5
+#define	R_386_GLOB_DAT	6
+#define	R_386_JMP_SLOT	7
+#define	R_386_RELATIVE	8
+#define	R_386_GOTOFF	9
+#define	R_386_GOTPC	10
+
+/* TLS relocations */
+#define	R_386_TLS_TPOFF	14
+#define	R_386_TLS_IE	15
+#define	R_386_TLS_GOTIE	16
+#define	R_386_TLS_LE	17
+#define	R_386_TLS_GD	18
+#define	R_386_TLS_LDM	19
+
+/* The following relocations are GNU extensions. */
+#define	R_386_16	20
+#define	R_386_PC16	21
+#define	R_386_8		22
+#define	R_386_PC8	23
+
+/* More TLS relocations */
+#define	R_386_TLS_GD_32		24
+#define	R_386_TLS_GD_PUSH	25
+#define	R_386_TLS_GD_CALL	26
+#define	R_386_TLS_GD_POP	27
+#define	R_386_TLS_LDM_32	28
+#define	R_386_TLS_LDM_PUSH	29
+#define	R_386_TLS_LDM_CALL	30
+#define	R_386_TLS_LDM_POP	31
+#define	R_386_TLS_LDO_32	32
+#define	R_386_TLS_IE_32		33
+#define	R_386_TLS_LE_32		34
+#define	R_386_TLS_DTPMOD32	35
+#define	R_386_TLS_DTPOFF32	36
+#define	R_386_TLS_TPOFF32	37
+#define	R_386_TLS_GOTDESC	39
+#define	R_386_TLS_DESC_CALL	40
+#define	R_386_TLS_DESC		41
+
+#define	R_TYPE(name)	__CONCAT(R_386_,name)
diff --git a/cpukit/score/cpu/i386/include/rtems/asm.h b/cpukit/score/cpu/i386/include/rtems/asm.h
new file mode 100644
index 0000000000..50b0fd71a0
--- /dev/null
+++ b/cpukit/score/cpu/i386/include/rtems/asm.h
@@ -0,0 +1,140 @@
+/**
+ * @file
+ *
+ * @brief Address the Problems Caused by Incompatible Flavor of 
+ * Assemblers and Toolsets
+ * 
+ * This include file attempts to address the problems
+ * caused by incompatible flavors of assemblers and
+ * toolsets.  It primarily addresses variations in the
+ * use of leading underscores on symbols and the requirement
+ * that register names be preceded by a %.
+ * 
+ * NOTE: The spacing in the use of these macros
+ *       is critical to them working as advertised.
+ */
+
+/*
+ *  COPYRIGHT:
+ *
+ *  This file is based on similar code found in newlib available
+ *  from ftp.cygnus.com.  The file which was used had no copyright
+ *  notice.  This file is freely distributable as long as the source
+ *  of the file is noted.  This file is:
+ *
+ *  COPYRIGHT (c) 1994-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ */
+
+#ifndef _RTEMS_ASM_H
+#define _RTEMS_ASM_H
+
+/*
+ *  Indicate we are in an assembly file and get the basic CPU definitions.
+ */
+
+#ifndef ASM
+#define ASM
+#endif
+#include <rtems/score/cpuopts.h>
+#include <rtems/score/i386.h>
+
+/*
+ *  Recent versions of GNU cpp define variables which indicate the
+ *  need for underscores and percents.  If not using GNU cpp or
+ *  the version does not support this, then you will obviously
+ *  have to define these as appropriate.
+ */
+
+#ifndef __USER_LABEL_PREFIX__
+#define __USER_LABEL_PREFIX__
+#endif
+
+/*
+ *  Looks like there is a bug in gcc 2.6.2 where this is not
+ *  defined correctly when configured as i386-coff and
+ *  i386-aout.
+ */
+
+#undef __REGISTER_PREFIX__
+#define __REGISTER_PREFIX__ %
+
+/*
+#ifndef __REGISTER_PREFIX__
+#define __REGISTER_PREFIX__
+#endif
+*/
+
+#include <rtems/concat.h>
+
+/* Use the right prefix for global labels.  */
+
+#define SYM(x) CONCAT0 (__USER_LABEL_PREFIX__, x)
+
+/* Use the right prefix for registers.  */
+
+#define REG(x) CONCAT0 (__REGISTER_PREFIX__, x)
+
+#define eax REG (eax)
+#define ebx REG (ebx)
+#define ecx REG (ecx)
+#define edx REG (edx)
+#define esi REG (esi)
+#define edi REG (edi)
+#define esp REG (esp)
+#define ebp REG (ebp)
+#define cr0 REG (cr0)
+#define cr4 REG (cr4)
+
+#define ax REG (ax)
+#define bx REG (bx)
+#define cx REG (cx)
+#define dx REG (dx)
+#define si REG (si)
+#define di REG (di)
+#define sp REG (sp)
+#define bp REG (bp)
+
+#define ah REG (ah)
+#define bh REG (bh)
+#define ch REG (ch)
+#define dh REG (dh)
+
+#define al REG (al)
+#define bl REG (bl)
+#define cl REG (cl)
+#define dl REG (dl)
+
+#define cs REG (cs)
+#define ds REG (ds)
+#define es REG (es)
+#define fs REG (fs)
+#define gs REG (gs)
+#define ss REG (ss)
+
+/*
+ *  Define macros to handle section beginning and ends.
+ */
+
+
+#define BEGIN_CODE_DCL .text
+#define END_CODE_DCL
+#define BEGIN_DATA_DCL .data
+#define END_DATA_DCL
+#define BEGIN_CODE .text
+#define END_CODE
+#define BEGIN_DATA .data
+#define END_DATA
+#define BEGIN_BSS .bss
+#define END_BSS
+#define END
+
+/*
+ *  Following must be tailor for a particular flavor of the C compiler.
+ *  They may need to put underscores in front of the symbols.
+ */
+
+#define PUBLIC(sym) .globl SYM (sym)
+#define EXTERN(sym) .globl SYM (sym)
+
+#endif
diff --git a/cpukit/score/cpu/i386/include/rtems/score/cpu.h b/cpukit/score/cpu/i386/include/rtems/score/cpu.h
new file mode 100644
index 0000000000..f78149c24b
--- /dev/null
+++ b/cpukit/score/cpu/i386/include/rtems/score/cpu.h
@@ -0,0 +1,700 @@
+/**
+ * @file
+ * 
+ * @brief Intel I386 CPU Dependent Source
+ * 
+ * This include file contains information pertaining to the Intel
+ * i386 processor.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2011.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _RTEMS_SCORE_CPU_H
+#define _RTEMS_SCORE_CPU_H
+
+#ifndef ASM
+#include <string.h> /* for memcpy */
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtems/score/types.h>
+#include <rtems/score/i386.h>
+
+/* conditional compilation parameters */
+
+/*
+ *  Does the CPU follow the simple vectored interrupt model?
+ *
+ *  If TRUE, then RTEMS allocates the vector table it internally manages.
+ *  If FALSE, then the BSP is assumed to allocate and manage the vector
+ *  table
+ *
+ *  PowerPC Specific Information:
+ *
+ *  The PowerPC and x86 were the first to use the PIC interrupt model.
+ *  They do not use the simple vectored interrupt model.
+ */
+#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
+
+/*
+ *  i386 has an RTEMS allocated and managed interrupt stack.
+ */
+
+#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
+#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
+#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
+
+/*
+ *  Does the RTEMS invoke the user's ISR with the vector number and
+ *  a pointer to the saved interrupt frame (1) or just the vector
+ *  number (0)?
+ */
+
+#define CPU_ISR_PASSES_FRAME_POINTER FALSE
+
+/*
+ *  Some family members have no FP, some have an FPU such as the i387
+ *  for the i386, others have it built in (i486DX, Pentium).
+ */
+
+#ifdef __SSE__
+#define CPU_HARDWARE_FP                  TRUE
+#define CPU_SOFTWARE_FP                  FALSE
+
+#define CPU_ALL_TASKS_ARE_FP             TRUE
+#define CPU_IDLE_TASK_IS_FP              TRUE
+#define CPU_USE_DEFERRED_FP_SWITCH       FALSE
+#else /* __SSE__ */
+
+#if ( I386_HAS_FPU == 1 )
+#define CPU_HARDWARE_FP     TRUE    /* i387 for i386 */
+#else
+#define CPU_HARDWARE_FP     FALSE
+#endif
+#define CPU_SOFTWARE_FP     FALSE
+
+#define CPU_ALL_TASKS_ARE_FP             FALSE
+#define CPU_IDLE_TASK_IS_FP              FALSE
+#if defined(RTEMS_SMP)
+  #define CPU_USE_DEFERRED_FP_SWITCH     FALSE
+#else
+  #define CPU_USE_DEFERRED_FP_SWITCH     TRUE
+#endif
+#endif /* __SSE__ */
+
+#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
+
+#define CPU_STACK_GROWS_UP               FALSE
+
+/* FIXME: The Pentium 4 used 128 bytes, it this processor still relevant? */
+#define CPU_CACHE_LINE_BYTES 64
+
+#define CPU_STRUCTURE_ALIGNMENT
+
+/*
+ *  Does this port provide a CPU dependent IDLE task implementation?
+ *
+ *  If TRUE, then the routine _CPU_Thread_Idle_body
+ *  must be provided and is the default IDLE thread body instead of
+ *  _CPU_Thread_Idle_body.
+ *
+ *  If FALSE, then use the generic IDLE thread body if the BSP does
+ *  not provide one.
+ */
+
+#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
+
+#define CPU_MAXIMUM_PROCESSORS 32
+
+#define I386_CONTEXT_CONTROL_EFLAGS_OFFSET 0
+#define I386_CONTEXT_CONTROL_ESP_OFFSET 4
+#define I386_CONTEXT_CONTROL_EBP_OFFSET 8
+#define I386_CONTEXT_CONTROL_EBX_OFFSET 12
+#define I386_CONTEXT_CONTROL_ESI_OFFSET 16
+#define I386_CONTEXT_CONTROL_EDI_OFFSET 20
+#define I386_CONTEXT_CONTROL_GS_0_OFFSET 24
+#define I386_CONTEXT_CONTROL_GS_1_OFFSET 28
+
+#ifdef RTEMS_SMP
+  #define I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 32
+#endif
+
+/* structures */
+
+#ifndef ASM
+
+/*
+ *  Basic integer context for the i386 family.
+ */
+
+typedef struct {
+  uint32_t    eflags;     /* extended flags register                   */
+  void       *esp;        /* extended stack pointer register           */
+  void       *ebp;        /* extended base pointer register            */
+  uint32_t    ebx;        /* extended bx register                      */
+  uint32_t    esi;        /* extended source index register            */
+  uint32_t    edi;        /* extended destination index flags register */
+  segment_descriptors gs; /* gs segment descriptor                     */
+#ifdef RTEMS_SMP
+  volatile bool is_executing;
+#endif
+}   Context_Control;
+
+#define _CPU_Context_Get_SP( _context ) \
+  (_context)->esp
+
+#ifdef RTEMS_SMP
+  static inline bool _CPU_Context_Get_is_executing(
+    const Context_Control *context
+  )
+  {
+    return context->is_executing;
+  }
+
+  static inline void _CPU_Context_Set_is_executing(
+    Context_Control *context,
+    bool is_executing
+  )
+  {
+    context->is_executing = is_executing;
+  }
+#endif
+
+/*
+ *  FP context save area for the i387 numeric coprocessors.
+ */
+#ifdef __SSE__
+/* All FPU and SSE registers are volatile; hence, as long
+ * as we are within normally executing C code (including
+ * a task switch) there is no need for saving/restoring
+ * any of those registers.
+ * We must save/restore the full FPU/SSE context across
+ * interrupts and exceptions, however:
+ *   -  after ISR execution a _Thread_Dispatch() may happen
+ *      and it is therefore necessary to save the FPU/SSE
+ *      registers to be restored when control is returned
+ *      to the interrupted task.
+ *   -  gcc may implicitly use FPU/SSE instructions in
+ *      an ISR.
+ *
+ * Even though there is no explicit mentioning of the FPU
+ * control word in the SYSV ABI (i386) being non-volatile
+ * we maintain MXCSR and the FPU control-word for each task.
+ */
+typedef struct {
+	uint32_t  mxcsr;
+	uint16_t  fpucw;
+} Context_Control_fp;
+
+#else
+
+typedef struct {
+  uint8_t     fp_save_area[108];    /* context size area for I80387 */
+                                    /*  28 bytes for environment    */
+} Context_Control_fp;
+
+#endif
+
+
+/*
+ *  The following structure defines the set of information saved
+ *  on the current stack by RTEMS upon receipt of execptions.
+ *
+ * idtIndex is either the interrupt number or the trap/exception number.
+ * faultCode is the code pushed by the processor on some exceptions.
+ *
+ * Since the first registers are directly pushed by the CPU they
+ * may not respect 16-byte stack alignment, which is, however,
+ * mandatory for the SSE register area.
+ * Therefore, these registers are stored at an aligned address
+ * and a pointer is stored in the CPU_Exception_frame.
+ * If the executive was compiled without SSE support then
+ * this pointer is NULL.
+ */
+
+struct Context_Control_sse;
+
+typedef struct {
+  struct Context_Control_sse *fp_ctxt;
+  uint32_t    edi;
+  uint32_t    esi;
+  uint32_t    ebp;
+  uint32_t    esp0;
+  uint32_t    ebx;
+  uint32_t    edx;
+  uint32_t    ecx;
+  uint32_t    eax;
+  uint32_t    idtIndex;
+  uint32_t    faultCode;
+  uint32_t    eip;
+  uint32_t    cs;
+  uint32_t    eflags;
+} CPU_Exception_frame;
+
+#ifdef __SSE__
+typedef struct Context_Control_sse {
+  uint16_t  fcw;
+  uint16_t  fsw;
+  uint8_t   ftw;
+  uint8_t   res_1;
+  uint16_t  fop;
+  uint32_t  fpu_ip;
+  uint16_t  cs;
+  uint16_t  res_2;
+  uint32_t  fpu_dp;
+  uint16_t  ds;
+  uint16_t  res_3;
+  uint32_t  mxcsr;
+  uint32_t  mxcsr_mask;
+  struct {
+  	uint8_t fpreg[10];
+  	uint8_t res_4[ 6];
+  } fp_mmregs[8];
+  uint8_t   xmmregs[8][16];
+  uint8_t   res_5[224];
+} Context_Control_sse
+__attribute__((aligned(16)))
+;
+#endif
+
+typedef void (*cpuExcHandlerType) (CPU_Exception_frame*);
+extern cpuExcHandlerType _currentExcHandler;
+extern void rtems_exception_init_mngt(void);
+
+/*
+ * This port does not pass any frame info to the
+ * interrupt handler.
+ */
+
+typedef void CPU_Interrupt_frame;
+
+typedef enum {
+  I386_EXCEPTION_DIVIDE_BY_ZERO      = 0,
+  I386_EXCEPTION_DEBUG               = 1,
+  I386_EXCEPTION_NMI                 = 2,
+  I386_EXCEPTION_BREAKPOINT          = 3,
+  I386_EXCEPTION_OVERFLOW            = 4,
+  I386_EXCEPTION_BOUND               = 5,
+  I386_EXCEPTION_ILLEGAL_INSTR       = 6,
+  I386_EXCEPTION_MATH_COPROC_UNAVAIL = 7,
+  I386_EXCEPTION_DOUBLE_FAULT        = 8,
+  I386_EXCEPTION_I386_COPROC_SEG_ERR = 9,
+  I386_EXCEPTION_INVALID_TSS         = 10,
+  I386_EXCEPTION_SEGMENT_NOT_PRESENT = 11,
+  I386_EXCEPTION_STACK_SEGMENT_FAULT = 12,
+  I386_EXCEPTION_GENERAL_PROT_ERR    = 13,
+  I386_EXCEPTION_PAGE_FAULT          = 14,
+  I386_EXCEPTION_INTEL_RES15         = 15,
+  I386_EXCEPTION_FLOAT_ERROR         = 16,
+  I386_EXCEPTION_ALIGN_CHECK         = 17,
+  I386_EXCEPTION_MACHINE_CHECK       = 18,
+  I386_EXCEPTION_ENTER_RDBG          = 50     /* to enter manually RDBG */
+
+} Intel_symbolic_exception_name;
+
+
+/*
+ *  context size area for floating point
+ *
+ *  NOTE:  This is out of place on the i386 to avoid a forward reference.
+ */
+
+#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
+
+/* variables */
+
+extern Context_Control_fp _CPU_Null_fp_context;
+
+#endif /* ASM */
+
+/* constants */
+
+/*
+ *  This defines the number of levels and the mask used to pick those
+ *  bits out of a thread mode.
+ */
+
+#define CPU_MODES_INTERRUPT_LEVEL  0x00000001 /* interrupt level in mode */
+#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
+
+/*
+ *  extra stack required by the MPCI receive server thread
+ */
+
+#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
+
+/*
+ *  This is defined if the port has a special way to report the ISR nesting
+ *  level.  Most ports maintain the variable _ISR_Nest_level.
+ */
+
+#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
+
+/*
+ *  Minimum size of a thread's stack.
+ */
+
+#define CPU_STACK_MINIMUM_SIZE          4096
+
+#define CPU_SIZEOF_POINTER 4
+
+/*
+ *  i386 is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
+ */
+
+#define CPU_ALIGNMENT                    4
+#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
+#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
+
+/*
+ *  On i386 thread stacks require no further alignment after allocation
+ *  from the Workspace. However, since gcc maintains 16-byte alignment
+ *  we try to respect that. If you find an option to let gcc squeeze
+ *  the stack more tightly then setting CPU_STACK_ALIGNMENT to 16 still
+ *  doesn't waste much space since this only determines the *initial*
+ *  alignment.
+ */
+
+#define CPU_STACK_ALIGNMENT             16
+
+/* macros */
+
+#ifndef ASM
+/*
+ *  ISR handler macros
+ *
+ *  These macros perform the following functions:
+ *     + initialize the RTEMS vector table
+ *     + disable all maskable CPU interrupts
+ *     + restore previous interrupt level (enable)
+ *     + temporarily restore interrupts (flash)
+ *     + set a particular level
+ */
+
+#if !defined(RTEMS_PARAVIRT)
+#define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level )
+
+#define _CPU_ISR_Enable( _level )  i386_enable_interrupts( _level )
+
+#define _CPU_ISR_Flash( _level )   i386_flash_interrupts( _level )
+
+#define _CPU_ISR_Set_level( _new_level ) \
+  { \
+    if ( _new_level ) __asm__ volatile ( "cli" ); \
+    else              __asm__ volatile ( "sti" ); \
+  }
+#else
+#define _CPU_ISR_Disable( _level ) _level = i386_disable_interrupts()
+#define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level )
+#define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level )
+#define _CPU_ISR_Set_level( _new_level ) i386_set_interrupt_level(_new_level)
+#endif
+
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+  return ( level & EFLAGS_INTR_ENABLE ) != 0;
+}
+
+uint32_t   _CPU_ISR_Get_level( void );
+
+/*  Make sure interrupt stack has space for ISR
+ *  'vector' arg at the top and that it is aligned
+ *  properly.
+ */
+
+#define _CPU_Interrupt_stack_setup( _lo, _hi )  \
+	do {                                        \
+		_hi = (void*)(((uintptr_t)(_hi) - 4) & ~ (CPU_STACK_ALIGNMENT - 1)); \
+	} while (0)
+
+#endif /* ASM */
+
+/* end of ISR handler macros */
+
+/*
+ *  Context handler macros
+ *
+ *  These macros perform the following functions:
+ *     + initialize a context area
+ *     + restart the current thread
+ *     + calculate the initial pointer into a FP context area
+ *     + initialize an FP context area
+ */
+
+#define CPU_EFLAGS_INTERRUPTS_ON  0x00003202
+#define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002
+
+#ifndef ASM
+
+void _CPU_Context_Initialize(
+  Context_Control *the_context,
+  void *stack_area_begin,
+  size_t stack_area_size,
+  uint32_t new_level,
+  void (*entry_point)( void ),
+  bool is_fp,
+  void *tls_area
+);
+
+#define _CPU_Context_Restart_self( _the_context ) \
+   _CPU_Context_restore( (_the_context) );
+
+#if defined(RTEMS_SMP)
+  uint32_t _CPU_SMP_Initialize( void );
+
+  bool _CPU_SMP_Start_processor( uint32_t cpu_index );
+
+  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
+
+  /* Nothing to do */
+  #define _CPU_SMP_Prepare_start_multitasking() do { } while ( 0 )
+
+  uint32_t _CPU_SMP_Get_current_processor( void );
+
+  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
+
+  static inline void _CPU_SMP_Processor_event_broadcast( void )
+  {
+    __asm__ volatile ( "" : : : "memory" );
+  }
+
+  static inline void _CPU_SMP_Processor_event_receive( void )
+  {
+    __asm__ volatile ( "" : : : "memory" );
+  }
+#endif
+
+#define _CPU_Context_Initialize_fp( _fp_area ) \
+  { \
+    memcpy( *_fp_area, &_CPU_Null_fp_context, CPU_CONTEXT_FP_SIZE ); \
+  }
+
+/* end of Context handler macros */
+
+/*
+ *  Fatal Error manager macros
+ *
+ *  These macros perform the following functions:
+ *    + disable interrupts and halt the CPU
+ */
+
+extern void _CPU_Fatal_halt(uint32_t source, uint32_t error)
+  RTEMS_NO_RETURN;
+
+#endif /* ASM */
+
+/* end of Fatal Error manager macros */
+
+/*
+ *  Bitfield handler macros
+ *
+ *  These macros perform the following functions:
+ *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
+ */
+
+#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
+
+#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
+  { \
+    register uint16_t __value_in_register = ( _value ); \
+    uint16_t          __output = 0; \
+    __asm__ volatile ( "bsfw    %0,%1 " \
+                    : "=r" ( __value_in_register ), "=r" ( __output ) \
+                    : "0"  ( __value_in_register ), "1"  ( __output ) \
+    ); \
+    ( _output ) = __output; \
+  }
+
+/* end of Bitfield handler macros */
+
+/*
+ *  Priority handler macros
+ *
+ *  These macros perform the following functions:
+ *    + return a mask with the bit for this major/minor portion of
+ *      of thread priority set.
+ *    + translate the bit number returned by "Bitfield_find_first_bit"
+ *      into an index into the thread ready chain bit maps
+ */
+
+#define _CPU_Priority_Mask( _bit_number ) \
+  ( 1 << (_bit_number) )
+
+#define _CPU_Priority_bits_index( _priority ) \
+  (_priority)
+
+/* functions */
+
+#ifndef ASM
+/*
+ *  _CPU_Initialize
+ *
+ *  This routine performs CPU dependent initialization.
+ */
+
+void _CPU_Initialize(void);
+
+/*
+ *  _CPU_ISR_install_raw_handler
+ *
+ *  This routine installs a "raw" interrupt handler directly into the
+ *  processor's vector table.
+ */
+
+void _CPU_ISR_install_raw_handler(
+  uint32_t    vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+);
+
+/*
+ *  _CPU_ISR_install_vector
+ *
+ *  This routine installs an interrupt vector.
+ */
+
+void _CPU_ISR_install_vector(
+  uint32_t    vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+);
+
+/*
+ *  _CPU_Thread_Idle_body
+ *
+ *  Use the halt instruction of low power mode of a particular i386 model.
+ */
+
+#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
+
+void *_CPU_Thread_Idle_body( uintptr_t ignored );
+
+#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
+
+/*
+ *  _CPU_Context_switch
+ *
+ *  This routine switches from the run context to the heir context.
+ */
+
+void _CPU_Context_switch(
+  Context_Control  *run,
+  Context_Control  *heir
+);
+
+/*
+ *  _CPU_Context_restore
+ *
+ *  This routine is generally used only to restart self in an
+ *  efficient manner and avoid stack conflicts.
+ */
+
+void _CPU_Context_restore(
+  Context_Control *new_context
+) RTEMS_NO_RETURN;
+
+/*
+ *  _CPU_Context_save_fp
+ *
+ *  This routine saves the floating point context passed to it.
+ */
+
+#ifdef __SSE__
+#define _CPU_Context_save_fp(fp_context_pp) \
+  do {                                      \
+    __asm__ __volatile__(                   \
+      "fstcw %0"                            \
+      :"=m"((*(fp_context_pp))->fpucw)      \
+    );                                      \
+	__asm__ __volatile__(                   \
+      "stmxcsr %0"                          \
+      :"=m"((*(fp_context_pp))->mxcsr)      \
+    );                                      \
+  } while (0)
+#else
+void _CPU_Context_save_fp(
+  Context_Control_fp **fp_context_ptr
+);
+#endif
+
+/*
+ *  _CPU_Context_restore_fp
+ *
+ *  This routine restores the floating point context passed to it.
+ */
+#ifdef __SSE__
+#define _CPU_Context_restore_fp(fp_context_pp) \
+  do {                                         \
+    __asm__ __volatile__(                      \
+      "fldcw %0"                               \
+      ::"m"((*(fp_context_pp))->fpucw)         \
+      :"fpcr"                                  \
+    );                                         \
+    __builtin_ia32_ldmxcsr(_Thread_Executing->fp_context->mxcsr);  \
+  } while (0)
+#else
+void _CPU_Context_restore_fp(
+  Context_Control_fp **fp_context_ptr
+);
+#endif
+
+#ifdef __SSE__
+#define _CPU_Context_Initialization_at_thread_begin() \
+  do {                                                \
+    __asm__ __volatile__(                             \
+      "finit"                                         \
+      :                                               \
+      :                                               \
+      :"st","st(1)","st(2)","st(3)",                  \
+       "st(4)","st(5)","st(6)","st(7)",               \
+       "fpsr","fpcr"                                  \
+    );                                                \
+	if ( _Thread_Executing->fp_context ) {            \
+	  _CPU_Context_restore_fp(&_Thread_Executing->fp_context); \
+   }                                                  \
+  } while (0)
+#endif
+
+static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
+{
+  /* TODO */
+}
+
+static inline void _CPU_Context_validate( uintptr_t pattern )
+{
+  while (1) {
+    /* TODO */
+  }
+}
+
+void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
+
+typedef uint32_t CPU_Counter_ticks;
+
+CPU_Counter_ticks _CPU_Counter_read( void );
+
+static inline CPU_Counter_ticks _CPU_Counter_difference(
+  CPU_Counter_ticks second,
+  CPU_Counter_ticks first
+)
+{
+  return second - first;
+}
+
+#endif /* ASM */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/cpukit/score/cpu/i386/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/i386/include/rtems/score/cpuatomic.h
new file mode 100644
index 0000000000..598ee76b20
--- /dev/null
+++ b/cpukit/score/cpu/i386/include/rtems/score/cpuatomic.h
@@ -0,0 +1,14 @@
+/*
+ * COPYRIGHT (c) 2012-2013 Deng Hengyi.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
+#define _RTEMS_SCORE_ATOMIC_CPU_H
+
+#include <rtems/score/cpustdatomic.h>
+
+#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
diff --git a/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h
new file mode 100644
index 0000000000..789f2badd9
--- /dev/null
+++ b/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h
@@ -0,0 +1,34 @@
+/**
+ * @file
+ *
+ * @brief CPU Port Implementation API
+ */
+
+/*
+ * Copyright (c) 2013 embedded brains GmbH
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _RTEMS_SCORE_CPUIMPL_H
+#define _RTEMS_SCORE_CPUIMPL_H
+
+#include <rtems/score/cpu.h>
+
+#define CPU_PER_CPU_CONTROL_SIZE 0
+
+#ifndef ASM
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ASM */
+
+#endif /* _RTEMS_SCORE_CPUIMPL_H */
diff --git a/cpukit/score/cpu/i386/include/rtems/score/i386.h b/cpukit/score/cpu/i386/include/rtems/score/i386.h
new file mode 100644
index 0000000000..2555d13b8b
--- /dev/null
+++ b/cpukit/score/cpu/i386/include/rtems/score/i386.h
@@ -0,0 +1,670 @@
+/**
+ * @file
+ *
+ * @brief Intel I386 CPU Dependent Source
+ *
+ * This include file contains information pertaining to the Intel
+ * i386 processor.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2016.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  Copyright (C) 1998  Eric Valette (valette@crf.canon.fr)
+ *                     Canon Centre Recherche France.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _RTEMS_SCORE_I386_H
+#define _RTEMS_SCORE_I386_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtems/score/interrupts.h>
+#include <rtems/score/registers.h>
+
+/*
+ *  This section contains the information required to build
+ *  RTEMS for a particular member of the Intel i386
+ *  family when executing in protected mode.  It does
+ *  this by setting variables to indicate which implementation
+ *  dependent features are present in a particular member
+ *  of the family.
+ *
+ *  Currently recognized:
+ *    i386_fp    (i386 DX or SX w/i387)
+ *    i486dx
+ *    pentium
+ *    pentiumpro
+ *
+ *  CPU Model Feature Flags:
+ *
+ *  I386_HAS_BSWAP:  Defined to "1" if the instruction for endian swapping
+ *                   (bswap) should be used.  This instruction appears to
+ *                   be present in all i486's and above.
+ *
+ *  I386_HAS_FPU:    Defined to "1" if the CPU has an FPU.
+ *                   As of at least gcc 4.7, i386 soft-float was obsoleted.
+ *                   Thus this is always set to "1".
+ */
+#define I386_HAS_FPU 1
+
+#if defined(__pentiumpro__)
+
+  #define CPU_MODEL_NAME  "Pentium Pro"
+
+#elif defined(__i586__)
+
+  #if defined(__pentium__)
+    #define CPU_MODEL_NAME "Pentium"
+  #elif defined(__k6__)
+    #define CPU_MODEL_NAME "K6"
+  #else
+    #define CPU_MODEL_NAME "i586"
+  #endif
+
+#elif defined(__i486__)
+
+  #define CPU_MODEL_NAME  "i486dx"
+
+#elif defined(__i386__)
+
+  #define I386_HAS_BSWAP  0
+  #define CPU_MODEL_NAME  "i386 with i387"
+
+#else
+  #error "Unknown CPU Model"
+#endif
+
+/*
+ *  Set default values for CPU model feature flags
+ *
+ *  NOTE: These settings are chosen to reflect most of the family members.
+ */
+#ifndef I386_HAS_BSWAP
+#define I386_HAS_BSWAP 1
+#endif
+
+/*
+ *  Define the name of the CPU family.
+ */
+#define CPU_NAME "Intel i386"
+
+#ifndef ASM
+
+/*
+ *  The following routine swaps the endian format of an unsigned int.
+ *  It must be static so it can be referenced indirectly.
+ */
+
+static inline uint32_t i386_swap_u32(
+  uint32_t value
+)
+{
+  uint32_t lout;
+
+#if (I386_HAS_BSWAP == 0)
+  __asm__ volatile( "rorw  $8,%%ax;"
+                "rorl  $16,%0;"
+                "rorw  $8,%%ax" : "=a" (lout) : "0" (value) );
+#else
+    __asm__ volatile( "bswap %0" : "=r"  (lout) : "0"   (value));
+#endif
+  return( lout );
+}
+#define CPU_swap_u32( _value )  i386_swap_u32( _value )
+
+static inline uint16_t i386_swap_u16(
+  uint16_t value
+)
+{
+  unsigned short      sout;
+
+  __asm__ volatile( "rorw $8,%0" : "=r"  (sout) : "0"   (value));
+  return (sout);
+}
+#define CPU_swap_u16( _value )  i386_swap_u16( _value )
+
+/*
+ * Added for pagination management
+ */
+static inline unsigned int i386_get_cr0(void)
+{
+  register unsigned int segment = 0;
+
+  __asm__ volatile ( "movl %%cr0,%0" : "=r" (segment) : "0" (segment) );
+
+  return segment;
+}
+
+static inline void i386_set_cr0(unsigned int segment)
+{
+  __asm__ volatile ( "movl %0,%%cr0" : "=r" (segment) : "0" (segment) );
+}
+
+static inline unsigned int i386_get_cr2(void)
+{
+  register unsigned int segment = 0;
+
+  __asm__ volatile ( "movl %%cr2,%0" : "=r" (segment) : "0" (segment) );
+
+  return segment;
+}
+
+static inline unsigned int i386_get_cr3(void)
+{
+  register unsigned int segment = 0;
+
+  __asm__ volatile ( "movl %%cr3,%0" : "=r" (segment) : "0" (segment) );
+
+  return segment;
+}
+
+static inline void i386_set_cr3(unsigned int segment)
+{
+  __asm__ volatile ( "movl %0,%%cr3" : "=r" (segment) : "0" (segment) );
+}
+
+/* routines */
+
+/*
+ *  i386_Logical_to_physical
+ *
+ *  Converts logical address to physical address.
+ */
+void *i386_Logical_to_physical(
+  unsigned short  segment,
+  void           *address
+);
+
+/*
+ *  i386_Physical_to_logical
+ *
+ *  Converts physical address to logical address.
+ */
+void *i386_Physical_to_logical(
+  unsigned short  segment,
+  void           *address
+);
+
+/**
+ * @brief Converts real mode pointer {segment, offset} to physical address.
+ *
+ * i386_Real_to_physical
+ *
+ * @param[in] segment used with \p offset to compute physical address
+ * @param[in] offset used with \p segment to compute physical address
+ * @retval    physical address
+ */
+RTEMS_INLINE_ROUTINE void *i386_Real_to_physical(
+    uint16_t segment,
+    uint16_t offset)
+{
+    return (void *)(((uint32_t)segment<<4)+offset);
+}
+
+/**
+ * @brief Retrieves real mode pointer elements {segmnet, offset} from
+ * physical address.
+ *
+ * i386_Physical_to_real
+ * Function returns the highest segment (base) address possible.
+ * Example:    input   address - 0x4B3A2
+ *             output  segment - 0x4B3A
+ *                     offset  - 0x2
+ *             input   address - 0x10F12E
+ *             output  segment - 0xFFFF
+ *                     offset  - 0xF13E
+ *
+ * @param[in]  address address to be converted, must be less than 0x10FFEF
+ * @param[out] segment segment computed from \p address
+ * @param[out] offset offset computed from \p address
+ * @retval  0 address not convertible
+ * @retval  1 segment and offset extracted
+ */
+int i386_Physical_to_real(
+  void *address,
+  uint16_t *segment,
+  uint16_t *offset
+);
+
+/*
+ *  Segment Access Routines
+ *
+ *  NOTE:  Unfortunately, these are still static inlines even when the
+ *         "macro" implementation of the generic code is used.
+ */
+
+static __inline__ unsigned short i386_get_cs(void)
+{
+  register unsigned short segment = 0;
+
+  __asm__ volatile ( "movw %%cs,%0" : "=r" (segment) : "0" (segment) );
+
+  return segment;
+}
+
+static __inline__ unsigned short i386_get_ds(void)
+{
+  register unsigned short segment = 0;
+
+  __asm__ volatile ( "movw %%ds,%0" : "=r" (segment) : "0" (segment) );
+
+  return segment;
+}
+
+static __inline__ unsigned short i386_get_es(void)
+{
+  register unsigned short segment = 0;
+
+  __asm__ volatile ( "movw %%es,%0" : "=r" (segment) : "0" (segment) );
+
+  return segment;
+}
+
+static __inline__ unsigned short i386_get_ss(void)
+{
+  register unsigned short segment = 0;
+
+  __asm__ volatile ( "movw %%ss,%0" : "=r" (segment) : "0" (segment) );
+
+  return segment;
+}
+
+static __inline__ unsigned short i386_get_fs(void)
+{
+  register unsigned short segment = 0;
+
+  __asm__ volatile ( "movw %%fs,%0" : "=r" (segment) : "0" (segment) );
+
+  return segment;
+}
+
+static __inline__ unsigned short i386_get_gs(void)
+{
+  register unsigned short segment = 0;
+
+  __asm__ volatile ( "movw %%gs,%0" : "=r" (segment) : "0" (segment) );
+
+  return segment;
+}
+
+/*
+ *  IO Port Access Routines
+ */
+
+#define i386_outport_byte( _port, _value ) \
+do { register unsigned short __port  = _port; \
+     register unsigned char  __value = _value; \
+     \
+     __asm__ volatile ( "outb %0,%1" : : "a" (__value), "d" (__port) ); \
+   } while (0)
+
+#define i386_outport_word( _port, _value ) \
+do { register unsigned short __port  = _port; \
+     register unsigned short __value = _value; \
+     \
+     __asm__ volatile ( "outw %0,%1" : : "a" (__value), "d" (__port) ); \
+   } while (0)
+
+#define i386_outport_long( _port, _value ) \
+do { register unsigned short __port  = _port; \
+     register unsigned int  __value = _value; \
+     \
+     __asm__ volatile ( "outl %0,%1" : : "a" (__value), "d" (__port) ); \
+   } while (0)
+
+#define i386_inport_byte( _port, _value ) \
+do { register unsigned short __port  = _port; \
+     register unsigned char  __value = 0; \
+     \
+     __asm__ volatile ( "inb %1,%0" : "=a" (__value) \
+                                : "d"  (__port) \
+                  ); \
+     _value = __value; \
+   } while (0)
+
+#define i386_inport_word( _port, _value ) \
+do { register unsigned short __port  = _port; \
+     register unsigned short __value = 0; \
+     \
+     __asm__ volatile ( "inw %1,%0" : "=a" (__value) \
+                                : "d"  (__port) \
+                  ); \
+     _value = __value; \
+   } while (0)
+
+#define i386_inport_long( _port, _value ) \
+do { register unsigned short __port  = _port; \
+     register unsigned int  __value = 0; \
+     \
+     __asm__ volatile ( "inl %1,%0" : "=a" (__value) \
+                                : "d"  (__port) \
+                  ); \
+     _value = __value; \
+   } while (0)
+
+/*
+ * Type definition for raw interrupts.
+ */
+
+typedef unsigned char  rtems_vector_offset;
+
+typedef struct __rtems_raw_irq_connect_data__{
+ /*
+  * IDT vector offset (IRQ line + PC386_IRQ_VECTOR_BASE)
+  */
+  rtems_vector_offset		idtIndex;
+  /*
+   * IDT raw handler. See comment on handler properties below in function prototype.
+   */
+  rtems_raw_irq_hdl	   	hdl;
+  /*
+   * function for enabling raw interrupts. In order to be consistent
+   * with the fact that the raw connexion can defined in the
+   * libcpu library, this library should have no knowledge of
+   * board specific hardware to manage interrupts and thus the
+   * "on" routine must enable the irq both at device and PIC level.
+   *
+   */
+    rtems_raw_irq_enable	on;
+  /*
+   * function for disabling raw interrupts. In order to be consistent
+   * with the fact that the raw connexion can defined in the
+   * libcpu library, this library should have no knowledge of
+   * board specific hardware to manage interrupts and thus the
+   * "on" routine must disable the irq both at device and PIC level.
+   *
+   */
+  rtems_raw_irq_disable		off;
+  /*
+   * function enabling to know what interrupt may currently occur
+   */
+  rtems_raw_irq_is_enabled	isOn;
+}rtems_raw_irq_connect_data;
+
+typedef struct {
+  /*
+   * size of all the table fields (*Tbl) described below.
+   */
+  unsigned int	 		idtSize;
+  /*
+   * Default handler used when disconnecting interrupts.
+   */
+  rtems_raw_irq_connect_data	defaultRawEntry;
+  /*
+   * Table containing initials/current value.
+   */
+  rtems_raw_irq_connect_data*	rawIrqHdlTbl;
+}rtems_raw_irq_global_settings;
+
+#include <rtems/score/idtr.h>
+
+/*
+ * C callable function enabling to get handler currently connected to a vector
+ *
+ */
+rtems_raw_irq_hdl get_hdl_from_vector(rtems_vector_offset);
+
+/*
+ * C callable function enabling to set up one raw idt entry
+ */
+extern int i386_set_idt_entry (const rtems_raw_irq_connect_data*);
+
+/*
+ * C callable function enabling to get one current raw idt entry
+ */
+extern int i386_get_current_idt_entry (rtems_raw_irq_connect_data*);
+
+/*
+ * C callable function enabling to remove one current raw idt entry
+ */
+extern int i386_delete_idt_entry (const rtems_raw_irq_connect_data*);
+
+/*
+ * C callable function enabling to init idt.
+ *
+ * CAUTION : this function assumes that the IDTR register
+ * has been already set.
+ */
+extern int i386_init_idt (rtems_raw_irq_global_settings* config);
+
+/*
+ * C callable function enabling to get actual idt configuration
+ */
+extern int i386_get_idt_config (rtems_raw_irq_global_settings** config);
+
+
+/*
+ * See page 11.12 Figure 11-8.
+ *
+ */
+/**
+ * @brief describes one entry of Global/Local Descriptor Table
+ */
+typedef struct {
+  unsigned int limit_15_0 		: 16;
+  unsigned int base_address_15_0	: 16;
+  unsigned int base_address_23_16	: 8;
+  unsigned int type			: 4;
+  unsigned int descriptor_type		: 1;
+  unsigned int privilege		: 2;
+  unsigned int present			: 1;
+  unsigned int limit_19_16		: 4;
+  unsigned int available		: 1;
+  unsigned int fixed_value_bits		: 1;
+  unsigned int operation_size		: 1;
+  unsigned int granularity		: 1;
+  unsigned int base_address_31_24	: 8;
+} RTEMS_PACKED segment_descriptors;
+
+/*
+ * C callable function enabling to get easilly usable info from
+ * the actual value of GDT register.
+ */
+extern void i386_get_info_from_GDTR (segment_descriptors** table,
+                                     uint16_t* limit);
+/*
+ * C callable function enabling to change the value of GDT register. Must be called
+ * with interrupts masked at processor level!!!.
+ */
+extern void i386_set_GDTR (segment_descriptors*,
+                           uint16_t limit);
+
+/**
+ * @brief Allows to set a GDT entry.
+ *
+ * Puts global descriptor \p sd to the global descriptor table on index
+ * \p segment_selector_index
+ *
+ * @param[in] segment_selector_index index to GDT entry
+ * @param[in] sd structure to be coppied to given \p segment_selector in GDT
+ * @retval  0 FAILED out of GDT range or index is 0, which is not valid
+ *                   index in GDT
+ * @retval  1 SUCCESS
+ */
+extern uint32_t i386_raw_gdt_entry (uint16_t segment_selector_index,
+                               segment_descriptors* sd);
+
+/**
+ * @brief fills \p sd with provided \p base in appropriate fields of \p sd
+ *
+ * @param[in] base 32-bit address to be set as descriptor's base
+ * @param[out] sd descriptor being filled with \p base
+ */
+extern void i386_fill_segment_desc_base (uint32_t base,
+                                         segment_descriptors* sd);
+
+/**
+ * @brief fills \p sd with provided \p limit in appropriate fields of \p sd
+ *
+ * sets granularity bit if necessary
+ *
+ * @param[in] limit 32-bit value representing number of limit bytes
+ * @param[out] sd descriptor being filled with \p limit
+ */
+extern void i386_fill_segment_desc_limit (uint32_t limit,
+                                          segment_descriptors* sd);
+
+/*
+ * C callable function enabling to set up one raw interrupt handler
+ */
+extern uint32_t i386_set_gdt_entry (uint16_t segment_selector,
+                                    uint32_t base,
+                                    uint32_t limit);
+
+/**
+ * @brief Returns next empty descriptor in GDT.
+ *
+ * Number of descriptors that can be returned depends on \a GDT_SIZE
+ *
+ * @retval  0 FAILED GDT is full
+ * @retval  <1;65535> segment_selector number as index to GDT
+ */
+extern uint16_t i386_next_empty_gdt_entry (void);
+
+/**
+ * @brief Copies GDT entry at index \p segment_selector to structure
+ * pointed to by \p struct_to_fill
+ *
+ * @param[in] segment_selector index to GDT table specifying descriptor to copy
+ * @param[out] struct_to_fill pointer to memory where will be descriptor coppied
+ * @retval  0 FAILED segment_selector out of GDT range
+ * @retval  <1;65535> retrieved segment_selector
+ */
+extern uint16_t i386_cpy_gdt_entry (uint16_t segment_selector,
+                                    segment_descriptors* struct_to_fill);
+
+/**
+ * @brief Returns pointer to GDT table at index given by \p segment_selector
+ *
+ * @param[in] sgmnt_selector index to GDT table for specifying descriptor to get
+ * @retval  NULL FAILED segment_selector out of GDT range
+ * @retval  pointer to GDT table at \p segment_selector
+ */
+extern segment_descriptors* i386_get_gdt_entry (uint16_t sgmnt_selector);
+
+/**
+ * @brief Extracts base address from GDT entry pointed to by \p gdt_entry
+ *
+ * @param[in]  gdt_entry pointer to entry from which base should be retrieved
+ * @retval base address from GDT entry
+*/
+RTEMS_INLINE_ROUTINE void* i386_base_gdt_entry (segment_descriptors* gdt_entry)
+{
+    return (void*)(gdt_entry->base_address_15_0 |
+            (gdt_entry->base_address_23_16<<16) |
+            (gdt_entry->base_address_31_24<<24));
+}
+
+/**
+ * @brief Extracts limit in bytes from GDT entry pointed to by \p gdt_entry
+ *
+ * @param[in]  gdt_entry pointer to entry from which limit should be retrieved
+ * @retval limit value in bytes from GDT entry
+ */
+extern uint32_t i386_limit_gdt_entry (segment_descriptors* gdt_entry);
+
+/*
+ * See page 11.18 Figure 11-12.
+ *
+ */
+
+typedef struct {
+  unsigned int offset			: 12;
+  unsigned int page			: 10;
+  unsigned int directory 		: 10;
+}la_bits;
+
+typedef union {
+  la_bits	bits;
+  unsigned int	address;
+}linear_address;
+
+
+/*
+ * See page 11.20 Figure 11-14.
+ *
+ */
+
+typedef struct {
+  unsigned int present	 		: 1;
+  unsigned int writable			: 1;
+  unsigned int user			: 1;
+  unsigned int write_through		: 1;
+  unsigned int cache_disable		: 1;
+  unsigned int accessed			: 1;
+  unsigned int reserved1		: 1;
+  unsigned int page_size		: 1;
+  unsigned int reserved2		: 1;
+  unsigned int available		: 3;
+  unsigned int page_frame_address	: 20;
+}page_dir_bits;
+
+typedef union {
+  page_dir_bits	bits;
+  unsigned int	dir_entry;
+}page_dir_entry;
+
+typedef struct {
+  unsigned int present	 		: 1;
+  unsigned int writable			: 1;
+  unsigned int user			: 1;
+  unsigned int write_through		: 1;
+  unsigned int cache_disable		: 1;
+  unsigned int accessed			: 1;
+  unsigned int dirty			: 1;
+  unsigned int reserved2		: 2;
+  unsigned int available		: 3;
+  unsigned int page_frame_address	: 20;
+}page_table_bits;
+
+typedef union {
+  page_table_bits	bits;
+  unsigned int		table_entry;
+} page_table_entry;
+
+/*
+ * definitions related to page table entry
+ */
+#define PG_SIZE 0x1000
+#define MASK_OFFSET 0xFFF
+#define MAX_ENTRY (PG_SIZE/sizeof(page_dir_entry))
+#define FOUR_MB       0x400000
+#define MASK_FLAGS 0x1A
+
+#define PTE_PRESENT  		0x01
+#define PTE_WRITABLE 		0x02
+#define PTE_USER		0x04
+#define PTE_WRITE_THROUGH	0x08
+#define PTE_CACHE_DISABLE	0x10
+
+typedef struct {
+  page_dir_entry pageDirEntry[MAX_ENTRY];
+} page_directory;
+
+typedef struct {
+  page_table_entry pageTableEntry[MAX_ENTRY];
+} page_table;
+
+/* Simpler names for the i80x86 I/O instructions */
+#define outport_byte( _port, _value ) i386_outport_byte( _port, _value )
+#define outport_word( _port, _value ) i386_outport_word( _port, _value )
+#define outport_long( _port, _value ) i386_outport_long( _port, _value )
+#define inport_byte( _port, _value )  i386_inport_byte( _port, _value )
+#define inport_word( _port, _value )  i386_inport_word( _port, _value )
+#define inport_long( _port, _value )  i386_inport_long( _port, _value )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !ASM */
+
+#endif
diff --git a/cpukit/score/cpu/i386/include/rtems/score/idtr.h b/cpukit/score/cpu/i386/include/rtems/score/idtr.h
new file mode 100644
index 0000000000..a79af40792
--- /dev/null
+++ b/cpukit/score/cpu/i386/include/rtems/score/idtr.h
@@ -0,0 +1,66 @@
+/**
+ * @file
+ * 
+ * @brief Intel I386 Data Structures
+ * 
+ * This file contains definitions for data structure related
+ *          to Intel system programming. More information can be found
+ *          on Intel site and more precisely in the following book :
+ *
+ *              Pentium Processor familly
+ *              Developper's Manual
+ *
+ *              Volume 3 : Architecture and Programming Manual
+ *
+ * Formerly contained in and extracted from libcpu/i386/cpu.h.
+ */
+
+/*
+ * COPYRIGHT (C) 1998  Eric Valette (valette@crf.canon.fr)
+ *                     Canon Centre Recherche France.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ *  Applications must not include this file directly.
+ */
+
+#ifndef _RTEMS_SCORE_IDTR_H
+#define _RTEMS_SCORE_IDTR_H
+
+/*
+ * See page 14.9 Figure 14-2.
+ *
+ */
+typedef struct
+{
+  unsigned int low_offsets_bits:16;
+  unsigned int segment_selector:16;
+  unsigned int fixed_value_bits:8;
+  unsigned int gate_type:5;
+  unsigned int privilege:2;
+  unsigned int present:1;
+  unsigned int high_offsets_bits:16;
+} interrupt_gate_descriptor;
+
+/*
+ * C callable function enabling to create a interrupt_gate_descriptor
+ */
+extern void create_interrupt_gate_descriptor (interrupt_gate_descriptor*, rtems_raw_irq_hdl);
+
+/*
+ * C callable function enabling to get easily usable info from
+ * the actual value of IDT register.
+ */
+extern void i386_get_info_from_IDTR (interrupt_gate_descriptor** table,
+				unsigned* limit);
+
+/*
+ * C callable function enabling to change the value of IDT register. Must be called
+ * with interrupts masked at processor level!!!.
+ */
+extern void i386_set_IDTR (interrupt_gate_descriptor* table,
+		      unsigned limit);
+
+#endif
diff --git a/cpukit/score/cpu/i386/include/rtems/score/interrupts.h b/cpukit/score/cpu/i386/include/rtems/score/interrupts.h
new file mode 100644
index 0000000000..3a7971c1ff
--- /dev/null
+++ b/cpukit/score/cpu/i386/include/rtems/score/interrupts.h
@@ -0,0 +1,85 @@
+/**
+ * @file
+ * 
+ * @brief Intel I386 Interrupt Macros
+ *
+ * Formerly contained in and extracted from libcpu/i386/cpu.h
+ */
+
+/*
+ *  COPYRIGHT (c) 1998 valette@crf.canon.fr
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ *  Applications must not include this file directly.
+ */
+
+#ifndef _RTEMS_SCORE_INTERRUPTS_H
+#define _RTEMS_SCORE_INTERRUPTS_H
+
+#ifndef ASM
+
+struct 	__rtems_raw_irq_connect_data__;
+
+typedef void (*rtems_raw_irq_hdl)		(void);
+typedef void (*rtems_raw_irq_enable)		(const struct __rtems_raw_irq_connect_data__*);
+typedef void (*rtems_raw_irq_disable)		(const struct __rtems_raw_irq_connect_data__*);
+typedef int  (*rtems_raw_irq_is_enabled)	(const struct __rtems_raw_irq_connect_data__*);
+
+/**
+ * @name Interrupt Level Macros
+ * 
+ */
+/**@{**/
+#if !defined(RTEMS_PARAVIRT)
+#define i386_disable_interrupts( _level ) \
+  { \
+    __asm__ volatile ( "pushf ; \
+                    cli ; \
+                    pop %0" \
+                   : "=rm" ((_level)) \
+    ); \
+  }
+
+#define i386_enable_interrupts( _level )  \
+  { \
+    __asm__ volatile ( "push %0 ; \
+                    popf" \
+                    : : "rm" ((_level)) : "cc" \
+    ); \
+  }
+
+#define i386_flash_interrupts( _level ) \
+  { \
+    __asm__ volatile ( "push %0 ; \
+                    popf ; \
+                    cli" \
+                    : : "rm" ((_level)) : "cc" \
+    ); \
+  }
+
+#define i386_get_interrupt_level( _level ) \
+  do { \
+    register uint32_t   _eflags; \
+    \
+    __asm__ volatile ( "pushf ; \
+                    pop %0" \
+                    : "=rm" ((_eflags)) \
+    ); \
+    \
+    _level = (_eflags & EFLAGS_INTR_ENABLE) ? 0 : 1; \
+  } while (0)
+#else
+uint32_t i386_disable_interrupts( void );
+void i386_enable_interrupts(uint32_t level);
+void i386_flash_interrupts(uint32_t level);
+void i386_set_interrupt_level(uint32_t new_level);
+uint32_t i386_get_interrupt_level( void );
+#endif /* PARAVIRT */
+
+/** @} */
+
+#endif
+#endif
diff --git a/cpukit/score/cpu/i386/include/rtems/score/registers.h b/cpukit/score/cpu/i386/include/rtems/score/registers.h
new file mode 100644
index 0000000000..254fef701b
--- /dev/null
+++ b/cpukit/score/cpu/i386/include/rtems/score/registers.h
@@ -0,0 +1,72 @@
+/**
+ * @file
+ * 
+ * @brief Intel CPU Constants and Definitions
+ * 
+ * This file contains definition and constants related to Intel Cpu
+ */
+
+/*
+ *  COPYRIGHT (c) 1998 valette@crf.canon.fr
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _RTEMS_SCORE_REGISTERS_H
+#define _RTEMS_SCORE_REGISTERS_H
+
+/*
+ * definition related to EFLAGS
+ */
+#define EFLAGS_CARRY			0x1
+#define EFLAGS_PARITY			0x4
+
+#define EFLAGS_AUX_CARRY		0x10
+#define EFLAGS_ZERO			0x40
+#define EFLAGS_SIGN			0x80
+
+#define EFLAGS_TRAP			0x100
+#define EFLAGS_INTR_ENABLE		0x200
+#define EFLAGS_DIRECTION		0x400
+#define EFLAGS_OVERFLOW			0x800
+
+#define	EFLAGS_IOPL_MASK		0x3000
+#define EFLAGS_NESTED_TASK		0x8000
+
+#define EFLAGS_RESUME			0x10000
+#define EFLAGS_VIRTUAL_MODE		0x20000
+#define EFLAGS_ALIGN_CHECK		0x40000
+#define EFLAGS_VIRTUAL_INTR		0x80000
+
+#define EFLAGS_VIRTUAL_INTR_PEND	0x100000
+#define EFLAGS_ID			0x200000
+
+/*
+ * definitions related to CR0
+ */
+#define CR0_PROTECTION_ENABLE		0x1
+#define CR0_MONITOR_COPROC		0x2
+#define CR0_COPROC_SOFT_EMUL		0x4
+#define CR0_FLOATING_INSTR_EXCEPTION	0x8
+
+#define CR0_EXTENSION_TYPE		0x10
+#define CR0_NUMERIC_ERROR		0x20
+
+#define CR0_WRITE_PROTECT		0x10000
+#define CR0_ALIGMENT_MASK		0x40000
+
+#define CR0_NO_WRITE_THROUGH		0x20000000
+#define CR0_PAGE_LEVEL_CACHE_DISABLE	0x40000000
+#define CR0_PAGING			0x80000000
+
+/*
+ * definitions related to CR3
+ */
+
+#define CR3_PAGE_CACHE_DISABLE		0x10
+#define CR3_PAGE_WRITE_THROUGH		0x8
+#define CR3_PAGE_DIRECTORY_MASK		0xFFFFF000
+
+#endif
diff --git a/cpukit/score/cpu/i386/include/rtems/score/types.h b/cpukit/score/cpu/i386/include/rtems/score/types.h
new file mode 100644
index 0000000000..00555d41b5
--- /dev/null
+++ b/cpukit/score/cpu/i386/include/rtems/score/types.h
@@ -0,0 +1,46 @@
+/**
+ * @file
+ * 
+ * @brief Intel I386 CPU Type Definitions
+ * 
+ * This include file contains type definitions pertaining to the Intel
+ * i386 processor family.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-1999.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _RTEMS_SCORE_TYPES_H
+#define _RTEMS_SCORE_TYPES_H
+
+#include <rtems/score/basedefs.h>
+
+#ifndef ASM
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  This section defines the basic types for this processor.
+ */
+
+/** Type that can store a 32-bit integer or a pointer. */
+typedef uintptr_t CPU_Uint32ptr;
+
+typedef void i386_isr;
+typedef i386_isr ( *i386_isr_entry )( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* !ASM */
+
+#endif