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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-09-10 11:10:04 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-09-10 11:29:54 +0200 |
| commit | 4768ae0feb0d6fdfa02fbd7a8c0e9965efd505e9 (patch) | |
| tree | 9811416646cec1a3023fae1756e7c8f4a315a7e0 /cpukit/score/cpu/h8300/rtems/score | |
| parent | bsp/altera-cyclone-v: Add BSP_USE_UART_INTERRUPTS (diff) | |
| download | rtems-4768ae0feb0d6fdfa02fbd7a8c0e9965efd505e9.tar.bz2 | |
bsps/arm: Fix invalidate instruction cache
Do not invalidate the entire L2 cache since it is a uniform cache in
_CPU_cache_invalidate_entire_instruction(). For consitency do not touch
the L2 cache even for the range function
_CPU_cache_invalidate_instruction_range().
Diffstat (limited to 'cpukit/score/cpu/h8300/rtems/score')
0 files changed, 0 insertions, 0 deletions