Whitespace removal.

4 files changed, 46 insertions, 46 deletions

diff --git a/cpukit/score/cpu/c4x/cpu.c b/cpukit/score/cpu/c4x/cpu.c
index 582765f111..67331c1a2b 100644
--- a/cpukit/score/cpu/c4x/cpu.c
+++ b/cpukit/score/cpu/c4x/cpu.c
@@ -48,7 +48,7 @@ void _CPU_Initialize(void)
  *  C4x Specific Information:
  *
  */
- 
+
 void _CPU_ISR_install_raw_handler(
   uint32_t    vector,
   proc_ptr    new_handler,
@@ -61,7 +61,7 @@ void _CPU_ISR_install_raw_handler(
    *  This is where we install the interrupt handler into the "raw" interrupt
    *  table used by the CPU to dispatch interrupt handlers.
    */
-    
+
   ittp = c4x_get_ittp();
   *old_handler = ittp[ vector ];
   ittp[ vector ] = new_handler;
@@ -70,7 +70,7 @@ void _CPU_ISR_install_raw_handler(
 /*XXX */
 
 #define C4X_CACHE       1
-#define C4X_BASE_ST     (C4X_CACHE==1) ? 0x4800 : 0x4000 
+#define C4X_BASE_ST     (C4X_CACHE==1) ? 0x4800 : 0x4000
 
 void _CPU_Context_Initialize(
   Context_Control       *_the_context,
diff --git a/cpukit/score/cpu/c4x/rtems/score/c4x.h b/cpukit/score/cpu/c4x/rtems/score/c4x.h
index c7b8f75c58..13559b29e5 100644
--- a/cpukit/score/cpu/c4x/rtems/score/c4x.h
+++ b/cpukit/score/cpu/c4x/rtems/score/c4x.h
@@ -33,29 +33,29 @@ extern "C" {
  *  dependent features are present in a particular member
  *  of the family.
  */
- 
+
 #if defined(_C30)
 #define CPU_MODEL_NAME  "C30"
 
 #elif defined(_C31)
 #define CPU_MODEL_NAME  "C31"
- 
+
 #elif defined(_C32)
 #define CPU_MODEL_NAME  "C32"
- 
+
 #elif defined(_C33)
 #define CPU_MODEL_NAME  "C33"
- 
+
 #elif defined(_C40)
 #define CPU_MODEL_NAME  "C40"
- 
+
 #elif defined(_C44)
 #define CPU_MODEL_NAME  "C44"
- 
+
 #else
- 
+
 #error "Unsupported CPU Model"
- 
+
 #endif
 
 /*
@@ -69,7 +69,7 @@ extern "C" {
  *  point registers", the notion of floating point is very inherent to
  *  applications.  In addition, the calling conventions require that
  *  only a few extended registers be preserved across subroutine calls.
- *  The overhead of including these few registers in the basic 
+ *  The overhead of including these few registers in the basic
  *  context is small compared to the overhead of managing the notion
  *  of separate floating point contexts.  So we decided to pretend that
  *  there is no FPU on the C3x or C4x.
@@ -156,7 +156,7 @@ static inline unsigned int cpu_st_get(void)
 
 #define c4x_global_interrupts_get() \
   (cpu_st_get() & C4X_ST_GIE)
-  
+
 #define c4x_global_interrupts_disable() \
   cpu_st_bit_clear(C4X_ST_GIE)
 
@@ -191,7 +191,7 @@ static inline unsigned int c3x_get_if(void)
 
 static inline void c3x_set_if(unsigned int _if_value)
 {
-  __asm__( "ldi %0, if" : : "g" (_if_value) : "if", "cc"); 
+  __asm__( "ldi %0, if" : : "g" (_if_value) : "if", "cc");
 }
 
 /*
@@ -211,7 +211,7 @@ static inline unsigned int c3x_get_ie(void)
 
 static inline void c3x_set_ie(unsigned int _ie_value)
 {
-  __asm__ volatile ( "ldi %0, ie" : : "g" (_ie_value) : "ie", "cc"); 
+  __asm__ volatile ( "ldi %0, ie" : : "g" (_ie_value) : "ie", "cc");
 }
 
 /*
@@ -222,7 +222,7 @@ static inline void c3x_set_ie(unsigned int _ie_value)
  *  c3x_ie_mask_flash   - temporarily restores previous IE mask
  *  c3x_ie_mask_set     - sets a specific set of the IE mask
  */
- 
+
 #define c3x_ie_mask_all( _isr_cookie ) \
   do { \
     __asm__("ldi  ie,%0\n" \
@@ -280,7 +280,7 @@ static inline unsigned int c4x_get_iif(void)
 
 static inline void c4x_set_iif(unsigned int _iif_value)
 {
-  __asm__( "ldi %0, iif" : : "g" (_iif_value) : "iif", "cc"); 
+  __asm__( "ldi %0, iif" : : "g" (_iif_value) : "iif", "cc");
 }
 
 /*
@@ -300,7 +300,7 @@ static inline unsigned int c4x_get_iie(void)
 
 static inline void c4x_set_iie(unsigned int _iie_value)
 {
-  __asm__( "ldi %0, iie" : : "g" (_iie_value) : "iie", "cc"); 
+  __asm__( "ldi %0, iie" : : "g" (_iie_value) : "iie", "cc");
 }
 
 /*
@@ -331,15 +331,15 @@ static inline void c4x_set_iie(unsigned int _iie_value)
  */
 
 static inline void * c4x_get_ittp(void)
-{ 
+{
   register unsigned int _if_value;
-  
+
   __asm__( "ldi if, %0" : "=r" (_if_value) );
-  return (void *)((_if_value & 0xffff0000) >> 8); 
-}  
+  return (void *)((_if_value & 0xffff0000) >> 8);
+}
 
 static inline void c4x_set_ittp(void *_ittp_value)
-{  
+{
   unsigned int _if_value;
   unsigned int _ittp_field;
 
@@ -356,7 +356,7 @@ static inline void c4x_set_ittp(void *_ittp_value)
 #else
   c3x_set_if( _if_value );
 #endif
-}  
+}
 
 #endif /* ifndef ASM */
 
diff --git a/cpukit/score/cpu/c4x/rtems/score/cpu.h b/cpukit/score/cpu/c4x/rtems/score/cpu.h
index 8c15ec6f52..fb30a04b5d 100644
--- a/cpukit/score/cpu/c4x/rtems/score/cpu.h
+++ b/cpukit/score/cpu/c4x/rtems/score/cpu.h
@@ -48,7 +48,7 @@ extern "C" {
  *
  *  C4x Specific Information:
  *
- *  We might as well try to inline this code until there is a 
+ *  We might as well try to inline this code until there is a
  *  code space problem.
  */
 
@@ -164,7 +164,7 @@ extern "C" {
 
 /*
  *  Does the RTEMS invoke the user's ISR with the vector number and
- *  a pointer to the saved interrupt frame (1) or just the vector 
+ *  a pointer to the saved interrupt frame (1) or just the vector
  *  number (0)?
  *
  *  C4x Specific Information:
@@ -194,7 +194,7 @@ extern "C" {
  *
  *  C4x Specific Information:
  *
- *  See c4x.h for more details but the bottom line is that the 
+ *  See c4x.h for more details but the bottom line is that the
  *  few extended registers required to be preserved across subroutines
  *  calls are considered part of the integer context.  This eliminates
  *  overhead.
@@ -242,7 +242,7 @@ extern "C" {
  *
  *  C4x Specific Information:
  *
- *  There is no known reason to make the IDLE task floating point and 
+ *  There is no known reason to make the IDLE task floating point and
  *  no point in wasting the memory or increasing the context switch
  *  time for the IDLE task.
  */
@@ -276,7 +276,7 @@ extern "C" {
  *
  *  C4x Specific Information:
  *
- *  There is no reason to avoid the deferred FP switch logic on this 
+ *  There is no reason to avoid the deferred FP switch logic on this
  *  CPU family.
  */
 
@@ -434,27 +434,27 @@ extern "C" {
  *
  *  From email with Michael Hayes:
  *  > > But what are the rules for what is passed in what registers?
- *  
+ *
  *  Args are passed in the following registers (in order):
- *  
+ *
  *  AR2, R2, R3, RC, RS, RE
- *  
+ *
  *  However, the first and second floating point values are always in R2
  *  and R3 (and all other floats are on the stack).  Structs are always
  *  passed on the stack.  If the last argument is an ellipsis, the
  *  previous argument is passed on the stack so that its address can be
  *  taken for the stdargs macros.
- *  
+ *
  *   > > What is assumed to be preserved across calls?
- *  
- *  AR3, AR4, AR5, AR6, AR7   
+ *
+ *  AR3, AR4, AR5, AR6, AR7
  *  R4, R5, R8              (using STI/LDI)
  *  R6, R7                  (using STF/LDF)
- *  
+ *
  *   > > What is assumed to be scratch registers?
- *  
+ *
  *  R0, R1, R2, R3, AR0, AR1, AR2, IR0, IR1, BK, RS, RE, RC, R9, R10, R11
- *  
+ *
  *  Based on this information, the task specific context is quite small
  *  but the interrupt context is much larger.  In fact, it could
  *  easily be argued that there is no point in distinguishing between
@@ -627,7 +627,7 @@ SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
  *
  *  C4x Specific Information:
  *
- *  Based on the information provided in section 7.6.1 (p. 7-26) 
+ *  Based on the information provided in section 7.6.1 (p. 7-26)
  *  titled "TMS320C30 and TMS320C31 Interrupt Vector Table" and section
  *  7.6.2 "TMS320C32 Interrupt Vector Table" of the TMS32C3x User's
  *  Guide (rev L, July 1997), vectors are numbered 0x00 - 0x3F.  Thus
@@ -993,7 +993,7 @@ void _CPU_Context_Initialize(
  *  There does not appear to be a simple way to do this on this
  *  processor family that is better than the generic algorithm.
  *  Almost certainly, a hand-optimized assembly version of the
- *  generic algorithm could be written although it is not 
+ *  generic algorithm could be written although it is not
  *  worth the development effort at this time.
  */
 
@@ -1065,14 +1065,14 @@ void _CPU_Initialize(void);
 /*
  *  _CPU_ISR_install_raw_handler
  *
- *  This routine installs a "raw" interrupt handler directly into the 
+ *  This routine installs a "raw" interrupt handler directly into the
  *  processor's vector table.
  *
  *  C4x Specific Information:
  *
  *  XXXanswer
  */
- 
+
 void _CPU_ISR_install_raw_handler(
   uint32_t    vector,
   proc_ptr    new_handler,
@@ -1199,18 +1199,18 @@ void _CPU_Context_restore_fp(
  *
  *  XXXanswer
  */
- 
+
 static inline uint32_t CPU_swap_u32(
   uint32_t value
 )
 {
   uint32_t   byte1, byte2, byte3, byte4, swapped;
- 
+
   byte4 = (value >> 24) & 0xff;
   byte3 = (value >> 16) & 0xff;
   byte2 = (value >> 8)  & 0xff;
   byte1 =  value        & 0xff;
- 
+
   swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
   return( swapped );
 }
diff --git a/cpukit/score/cpu/c4x/rtems/tic4x/c4xio.h b/cpukit/score/cpu/c4x/rtems/tic4x/c4xio.h
index 9d2548ebac..87a20ee91d 100644
--- a/cpukit/score/cpu/c4x/rtems/tic4x/c4xio.h
+++ b/cpukit/score/cpu/c4x/rtems/tic4x/c4xio.h
@@ -90,7 +90,7 @@ struct c4x_timer {
 /*
  *  IO Flags
  *
- *  NOTE: iof on c3x, iiof on c4x 
+ *  NOTE: iof on c3x, iiof on c4x
  */
 
 #ifdef _TMS320C40