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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2016-01-25 10:20:28 +0100 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2016-01-26 09:07:30 +0100 |
commit | a8865f8b415788c4e9bb7f68e38d41aec0e485db (patch) | |
tree | d7b70c608239be68c6476b0d9e9893e099ec8be6 /cpukit/score/cpu/arm/rtems | |
parent | score: Add RTEMS_ALIGNED() (diff) | |
download | rtems-a8865f8b415788c4e9bb7f68e38d41aec0e485db.tar.bz2 |
score: Introduce CPU_CACHE_LINE_BYTES
Add CPU_CACHE_LINE_BYTES for the maximum cache line size in bytes. The
actual processor may use no cache or a smaller cache line size.
Diffstat (limited to 'cpukit/score/cpu/arm/rtems')
-rw-r--r-- | cpukit/score/cpu/arm/rtems/score/cpu.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h b/cpukit/score/cpu/arm/rtems/score/cpu.h index 089d429341..89b76090cc 100644 --- a/cpukit/score/cpu/arm/rtems/score/cpu.h +++ b/cpukit/score/cpu/arm/rtems/score/cpu.h @@ -144,8 +144,10 @@ #define CPU_STACK_GROWS_UP FALSE -/* XXX Why 32? */ -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) +/* FIXME: Is this the right value? */ +#define CPU_CACHE_LINE_BYTES 32 + +#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) /* * The interrupt mask disables only normal interrupts (IRQ). |