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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2007-11-06 22:51:08 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2007-11-06 22:51:08 +0000 |
| commit | 661e5de43bea5199f8e7a9f5acb85eae1daaf9ea (patch) | |
| tree | 514f1503907df66655d574d3547fe5c5b8951f84 /cpukit/score/cpu/arm/rtems | |
| parent | 2007-11-03 Ray Xu <rayx.cn@gmail.com> (diff) | |
| download | rtems-661e5de43bea5199f8e7a9f5acb85eae1daaf9ea.tar.bz2 | |
2007-11-03 Ray Xu <rayx.cn@gmail.com>
* cpu.c, cpu_asm.S, score/cpu.h : add support for ARM<->THUMB veneer
thumb new dir to controll CPSR/SPRS in thumb mode
2007-05-09 Ray Xu <rayx.cn@gmail.com>
* cpu.c: move do_data_abort() to libbsp/arm/shared/abort/
implement a compact do_data_abort() in simple_abort.c
Diffstat (limited to 'cpukit/score/cpu/arm/rtems')
| -rw-r--r-- | cpukit/score/cpu/arm/rtems/asm.h | 13 | ||||
| -rw-r--r-- | cpukit/score/cpu/arm/rtems/score/cpu.h | 20 |
2 files changed, 33 insertions, 0 deletions
diff --git a/cpukit/score/cpu/arm/rtems/asm.h b/cpukit/score/cpu/arm/rtems/asm.h index 5c33a2565a..bbb9760156 100644 --- a/cpukit/score/cpu/arm/rtems/asm.h +++ b/cpukit/score/cpu/arm/rtems/asm.h @@ -94,6 +94,19 @@ #define SPSR REG(SPSR) +#define NUM_IRQ_VECTOR 6 // IRQ number +#define NUM_FIQ_VECTOR 7 // IRQ number + // // +#define CPSR_IRQ_DISABLE 0x80 // FIQ disabled when =1 +#define CPSR_FIQ_DISABLE 0x40 // FIQ disabled when =1 +#define CPSR_THUMB_ENABLE 0x20 // Thumb mode when =1 +#define CPSR_FIQ_MODE 0x11 +#define CPSR_IRQ_MODE 0x12 +#define CPSR_SUPERVISOR_MODE 0x13 +#define CPSR_UNDEF_MODE 0x1B + +#define CPSR_MODE_BITS 0x1F + /* * Define macros to handle section beginning and ends. */ diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h b/cpukit/score/cpu/arm/rtems/score/cpu.h index f03ff2baab..cf99701e9c 100644 --- a/cpukit/score/cpu/arm/rtems/score/cpu.h +++ b/cpukit/score/cpu/arm/rtems/score/cpu.h @@ -512,7 +512,26 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; * Disable all interrupts for an RTEMS critical section. The previous * level is returned in _level. */ +#if (defined(__THUMB_INTERWORK__) || defined(__thumb__)) +extern unsigned int _CPU_ISR_Disable_Thumb(void) __attribute__ ((naked)); +extern void _CPU_ISR_Enable_Thumb( int ) __attribute__ ((naked)); +extern void _CPU_ISR_Flash_Thumb(int) __attribute__ ((naked)); +extern void _CPU_ISR_Set_level_Thumb(int ) __attribute__ ((naked)); +extern uint32_t _CPU_ISR_Get_level_Thumb(void ) __attribute__ ((naked)); + +#define _CPU_ISR_Disable(_level) \ + (_level) = _CPU_ISR_Disable_Thumb() + +#define _CPU_ISR_Enable(a) _CPU_ISR_Enable_Thumb(a) + +#define _CPU_ISR_Flash(a) _CPU_ISR_Flash_Thumb(a) + +#define _CPU_ISR_Set_level(a) _CPU_ISR_Set_level_Thumb(a) + +#define _CPU_ISR_Get_level(a) _CPU_ISR_Get_level_Thumb(a) + +#else /*For ARM mode*/ #define _CPU_ISR_Disable( _level ) \ { \ int reg; \ @@ -575,6 +594,7 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; : "0" (reg), "r" (new_level)); \ } +#endif /*(defined(__THUMB_INTERWORK__) || defined(__thumb__))*/ uint32_t _CPU_ISR_Get_level( void ); |