diff options
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2016-11-13 15:18:58 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2016-11-18 07:30:31 +0100 |
| commit | 04bd2617269880afaafa8f0647aaeda50b50698c (patch) | |
| tree | 6557663e60ceafbd1c36b82598e0e382efaf4217 /cpukit/score/cpu/arm/rtems | |
| parent | Fix untar mkdir when the directory exists. (diff) | |
| download | rtems-04bd2617269880afaafa8f0647aaeda50b50698c.tar.bz2 | |
arm: Use TPIDRPRW for current per-CPU control
Use the previously unused TPIDRPRW register to get the per-CPU control
of the current processor. This avoids instructions in
GET_SELF_CPU_CONTROL which are not available in Thumb mode.
Diffstat (limited to 'cpukit/score/cpu/arm/rtems')
| -rw-r--r-- | cpukit/score/cpu/arm/rtems/asm.h | 12 | ||||
| -rw-r--r-- | cpukit/score/cpu/arm/rtems/score/cpuimpl.h | 23 |
2 files changed, 28 insertions, 7 deletions
diff --git a/cpukit/score/cpu/arm/rtems/asm.h b/cpukit/score/cpu/arm/rtems/asm.h index d22514d60a..ec5ddc94ac 100644 --- a/cpukit/score/cpu/arm/rtems/asm.h +++ b/cpukit/score/cpu/arm/rtems/asm.h @@ -187,14 +187,12 @@ #endif /* __thumb__ */ .endm -.macro GET_SELF_CPU_CONTROL REG, TMP - ldr \REG, =_Per_CPU_Information +.macro GET_SELF_CPU_CONTROL REG #ifdef RTEMS_SMP - /* Use ARMv7 Multiprocessor Affinity Register (MPIDR) */ - mrc p15, 0, \TMP, c0, c0, 5 - - and \TMP, \TMP, #0xff - add \REG, \REG, \TMP, asl #PER_CPU_CONTROL_SIZE_LOG2 + /* Use PL1 only Thread ID Register (TPIDRPRW) */ + mrc p15, 0, \REG, c13, c0, 4 +#else + ldr \REG, =_Per_CPU_Information #endif .endm diff --git a/cpukit/score/cpu/arm/rtems/score/cpuimpl.h b/cpukit/score/cpu/arm/rtems/score/cpuimpl.h index 6b8b601cb0..1e9e101219 100644 --- a/cpukit/score/cpu/arm/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/arm/rtems/score/cpuimpl.h @@ -21,6 +21,29 @@ extern "C" { #endif +#ifdef ARM_MULTILIB_ARCH_V4 + +#ifdef RTEMS_SMP + +static inline struct Per_CPU_Control *_ARM_Get_current_per_CPU_control( void ) +{ + struct Per_CPU_Control *cpu_self; + + /* Use PL1 only Thread ID Register (TPIDRPRW) */ + __asm__ volatile ( + "mrc p15, 0, %0, c13, c0, 4" + : "=r" ( cpu_self ) + ); + + return cpu_self; +} + +#define _CPU_Get_current_per_CPU_control() _ARM_Get_current_per_CPU_control() + +#endif /* RTEMS_SMP */ + +#endif /* ARM_MULTILIB_ARCH_V4 */ + #ifdef __cplusplus } #endif |