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| author | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-07-02 14:33:11 +0200 |
|---|---|---|
| committer | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-07-04 15:55:57 +0200 |
| commit | 0cb50ab25b3e2cb9ccf0f4961e0229415e211cb7 (patch) | |
| tree | 91e5283ffb2fab25af73eb916e527e84e5dc81f7 /cpukit/score/cpu/arm/rtems/score/cpu.h | |
| parent | arm/raspberrypi: Enable HYP to SVC switch for this BSP. (diff) | |
| download | rtems-0cb50ab25b3e2cb9ccf0f4961e0229415e211cb7.tar.bz2 | |
score/arm: Ensure that copile time alignment is 64 bytes for Cortex-A multilib.
Some/many Cortex-A cores have data cache line length 64 bytes and maximum
value has to be used for system structures alignment.
Diffstat (limited to 'cpukit/score/cpu/arm/rtems/score/cpu.h')
| -rw-r--r-- | cpukit/score/cpu/arm/rtems/score/cpu.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h b/cpukit/score/cpu/arm/rtems/score/cpu.h index 91e4ec6211..adaf8091d3 100644 --- a/cpukit/score/cpu/arm/rtems/score/cpu.h +++ b/cpukit/score/cpu/arm/rtems/score/cpu.h @@ -145,8 +145,11 @@ #define CPU_STACK_GROWS_UP FALSE -/* FIXME: Is this the right value? */ -#define CPU_CACHE_LINE_BYTES 32 +#if defined(ARM_MULTILIB_CACHE_LINE_MAX_64) + #define CPU_CACHE_LINE_BYTES 32 +#else + #define CPU_CACHE_LINE_BYTES 64 +#endif #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) |