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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-11-10 11:08:37 +0100 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-11-10 11:10:46 +0100 |
commit | 8f6dd3ca1fa9c7772746fcd2f487e504e6968598 (patch) | |
tree | 5f0a4c34107aa1f21192696381ee442a9b945f9e /cpukit/score/cpu/arm/armv7m-context-initialize.c | |
parent | bsps/riscv: Skip init on not configured processors (diff) | |
download | rtems-8f6dd3ca1fa9c7772746fcd2f487e504e6968598.tar.bz2 |
arm: Fix Armv7-M TLS support
Set the thread ID register in the CPU context.
Update #3835.
Close #4753.
Diffstat (limited to 'cpukit/score/cpu/arm/armv7m-context-initialize.c')
-rw-r--r-- | cpukit/score/cpu/arm/armv7m-context-initialize.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cpukit/score/cpu/arm/armv7m-context-initialize.c b/cpukit/score/cpu/arm/armv7m-context-initialize.c index 58c7269193..a078c8f757 100644 --- a/cpukit/score/cpu/arm/armv7m-context-initialize.c +++ b/cpukit/score/cpu/arm/armv7m-context-initialize.c @@ -61,7 +61,7 @@ void _CPU_Context_Initialize( context->register_sp = stack_area_end; if ( tls_area != NULL ) { - _TLS_Initialize_area( tls_area ); + context->thread_id = (uint32_t) _TLS_Initialize_area( tls_area ); } } |