diff options
author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2020-09-22 08:31:34 -0500 |
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committer | Joel Sherrill <joel@rtems.org> | 2020-10-05 16:11:39 -0500 |
commit | 8387c52e476e18c42d5f3986e01cbb1916f13a2c (patch) | |
tree | ca9219330ea133ec66de05c7fe56fa59903ec3ad /cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h | |
parent | spmsgq_err01: Use correct max values and fix 64bit (diff) | |
download | rtems-8387c52e476e18c42d5f3986e01cbb1916f13a2c.tar.bz2 |
score: Add AArch64 port
This adds a CPU port for AArch64(ARMv8) with support for exceptions and
interrupts.
Diffstat (limited to 'cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h')
-rw-r--r-- | cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h new file mode 100644 index 0000000000..4c3da6794a --- /dev/null +++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSScoreCPU + * + * @brief CPU Port Implementation API + */ + +/* + * Copyright (C) 2020 On-Line Applications Research Corporation (OAR) + * Written by Kinsey Moore <kinsey.moore@oarcorp.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTEMS_SCORE_CPUIMPL_H +#define _RTEMS_SCORE_CPUIMPL_H + +#include <rtems/score/cpu.h> + +/** + * @defgroup RTEMSScoreCPUAArch64 AArch64 + * + * @ingroup RTEMSScoreCPU + * + * @brief ARM AArch64 Architecture Support + * + * @{ + */ + +#define CPU_PER_CPU_CONTROL_SIZE 0 +#define CPU_INTERRUPT_FRAME_SIZE 240 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +void _CPU_Context_volatile_clobber( uintptr_t pattern ); + +void _CPU_Context_validate( uintptr_t pattern ); + +RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +{ + __asm__ volatile ( ".inst 0x0" ); +} + +RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +{ + __asm__ volatile ( "nop" ); +} + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +/** @} */ + +#endif /* _RTEMS_SCORE_CPUIMPL_H */ |