diff options
author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2020-12-07 14:51:10 -0600 |
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committer | Joel Sherrill <joel@rtems.org> | 2020-12-10 11:37:50 -0600 |
commit | f046af5804cdac0f6afa0f6e30447f17e8d73a6f (patch) | |
tree | 280c81d1f967ce4599115154e1fd95695827148d /cpukit/score/cpu/aarch64/include/rtems/score/cpu.h | |
parent | bsps: Remove ARM GIC SGI target filter (diff) | |
download | rtems-f046af5804cdac0f6afa0f6e30447f17e8d73a6f.tar.bz2 |
cpukit/aarch64: Use hex consistently for offsets
Diffstat (limited to 'cpukit/score/cpu/aarch64/include/rtems/score/cpu.h')
-rw-r--r-- | cpukit/score/cpu/aarch64/include/rtems/score/cpu.h | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h index d86543b12a..380d1380fb 100644 --- a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h @@ -124,31 +124,31 @@ #define CPU_MAXIMUM_PROCESSORS 32 -#define AARCH64_CONTEXT_CONTROL_THREAD_ID_OFFSET 112 +#define AARCH64_CONTEXT_CONTROL_THREAD_ID_OFFSET 0x70 #ifdef AARCH64_MULTILIB_VFP - #define AARCH64_CONTEXT_CONTROL_D8_OFFSET 120 + #define AARCH64_CONTEXT_CONTROL_D8_OFFSET 0x78 #endif -#define AARCH64_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 104 +#define AARCH64_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 0x68 #ifdef RTEMS_SMP #if defined(AARCH64_MULTILIB_VFP) - #define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112 + #define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x70 #else - #define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48 + #define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x30 #endif #endif -#define AARCH64_EXCEPTION_FRAME_SIZE 848 +#define AARCH64_EXCEPTION_FRAME_SIZE 0x350 -#define AARCH64_EXCEPTION_FRAME_REGISTER_SP_OFFSET 248 -#define AARCH64_EXCEPTION_FRAME_REGISTER_LR_OFFSET 240 -#define AARCH64_EXCEPTION_FRAME_REGISTER_DAIF_OFFSET 264 -#define AARCH64_EXCEPTION_FRAME_REGISTER_SYNDROME_OFFSET 280 -#define AARCH64_EXCEPTION_FRAME_REGISTER_VECTOR_OFFSET 296 -#define AARCH64_EXCEPTION_FRAME_REGISTER_FPSR_OFFSET 312 -#define AARCH64_EXCEPTION_FRAME_REGISTER_Q0_OFFSET 336 +#define AARCH64_EXCEPTION_FRAME_REGISTER_SP_OFFSET 0xF8 +#define AARCH64_EXCEPTION_FRAME_REGISTER_LR_OFFSET 0xF0 +#define AARCH64_EXCEPTION_FRAME_REGISTER_DAIF_OFFSET 0x108 +#define AARCH64_EXCEPTION_FRAME_REGISTER_SYNDROME_OFFSET 0x118 +#define AARCH64_EXCEPTION_FRAME_REGISTER_VECTOR_OFFSET 0x128 +#define AARCH64_EXCEPTION_FRAME_REGISTER_FPSR_OFFSET 0x138 +#define AARCH64_EXCEPTION_FRAME_REGISTER_Q0_OFFSET 0x150 #ifndef ASM |