LIBPCI: converted to BSD header

1 files changed, 26 insertions, 26 deletions

diff --git a/cpukit/libpci/pci_cfg_static.c b/cpukit/libpci/pci_cfg_static.c
index ad3182e91e..5ec224238d 100644
--- a/cpukit/libpci/pci_cfg_static.c
+++ b/cpukit/libpci/pci_cfg_static.c
@@ -45,36 +45,36 @@ static int pci_init_dev(struct pci_dev *dev, void *unused)
 	/* Set command to reset values, it disables bus
 	 * mastering and address responses.
 	 */
-	PCI_CFG_W16(pcidev, PCI_COMMAND, 0);
+	PCI_CFG_W16(pcidev, PCIR_COMMAND, 0);
 
 	/* Clear any already set status bits */
-	PCI_CFG_W16(pcidev, PCI_STATUS, 0xf900);
+	PCI_CFG_W16(pcidev, PCIR_STATUS, 0xf900);
 
 	/* Set latency timer to 64 */
-	PCI_CFG_W8(pcidev, PCI_LATENCY_TIMER, 64);
+	PCI_CFG_W8(pcidev, PCIR_LATTIMER, 64);
 
 	/* Set System IRQ of PIN */
-	PCI_CFG_W8(pcidev, PCI_INTERRUPT_LINE, dev->sysirq);
+	PCI_CFG_W8(pcidev, PCIR_INTLINE, dev->sysirq);
 
 	cmd = dev->command;
 
 	if ((dev->flags & PCI_DEV_BRIDGE) == 0) {
 		/* Disable Cardbus CIS Pointer */
-		PCI_CFG_W32(pcidev, PCI_CARDBUS_CIS, 0);
+		PCI_CFG_W32(pcidev, PCIR_CIS, 0);
 
-		romofs = PCI_ROM_ADDRESS;
+		romofs = PCIR_BIOS;
 		maxbars = 6;
 	} else {
 		/* Init Bridge */
 
 		/* Configure bridge (no support for 64-bit) */
-		PCI_CFG_W32(pcidev, PCI_PREF_BASE_UPPER32, 0);
-		PCI_CFG_W32(pcidev, PCI_PREF_LIMIT_UPPER32, 0);
+		PCI_CFG_W32(pcidev, PCIR_PMBASEH_1, 0);
+		PCI_CFG_W32(pcidev, PCIR_PMLIMITH_1, 0);
 
 		bridge = (struct pci_bus *)dev;
 		tmp = (64 << 24) | (bridge->sord << 16) |
 			(bridge->num << 8) | bridge->pri;
-		PCI_CFG_W32(pcidev, PCI_PRIMARY_BUS, tmp);
+		PCI_CFG_W32(pcidev, PCIR_PRIBUS_1, tmp);
 
 		/*** Setup I/O Bridge Window ***/
 		res = &dev->resources[BRIDGE_RES_IO];
@@ -82,44 +82,44 @@ static int pci_init_dev(struct pci_dev *dev, void *unused)
 			tmp16 = ((res->end-1) & 0x0000f000) |
 				((res->start & 0x0000f000) >> 8);
 			tmp = ((res->end-1) & 0xffff0000) | (res->start >> 16);
-			cmd |= PCI_COMMAND_IO;
+			cmd |= PCIM_CMD_PORTEN;
 		} else {
 			tmp16 = 0x00ff;
 			tmp = 0;
 		}
 		/* I/O Limit and Base */
-		PCI_CFG_W16(pcidev, PCI_IO_BASE, tmp16);
-		PCI_CFG_W32(pcidev, PCI_IO_BASE_UPPER16, tmp);
+		PCI_CFG_W16(pcidev, PCIR_IOBASEL_1, tmp16);
+		PCI_CFG_W32(pcidev, PCIR_IOBASEH_1, tmp);
 
 		/*** Setup MEMIO Bridge Window ***/
 		res = &dev->resources[BRIDGE_RES_MEMIO];
 		if (res->size > 0) {
 			tmp = ((res->end-1) & 0xffff0000) |
 				(res->start >> 16);
-			cmd |= PCI_COMMAND_MEMORY;
+			cmd |= PCIM_CMD_MEMEN;
 		} else {
 			tmp = 0x0000ffff;
 		}
 		/* MEMIO Limit and Base */
-		PCI_CFG_W32(pcidev, PCI_MEMORY_BASE, tmp);
+		PCI_CFG_W32(pcidev, PCIR_MEMBASE_1, tmp);
 
 		/*** Setup MEM Bridge Window ***/
 		res = &dev->resources[BRIDGE_RES_MEM];
 		if (res->size > 0) {
 			tmp = ((res->end-1) & 0xffff0000) |
 				(res->start >> 16);
-			cmd |= PCI_COMMAND_MEMORY;
+			cmd |= PCIM_CMD_MEMEN;
 		} else {
 			tmp = 0x0000ffff;
 		}
 		/* MEM Limit and Base */
-		PCI_CFG_W32(pcidev, PCI_PREF_MEMORY_BASE, tmp);
+		PCI_CFG_W32(pcidev, PCIR_PMBASEL_1, tmp);
 		/* 64-bit space not supported */
-		PCI_CFG_W32(pcidev, PCI_PREF_BASE_UPPER32, 0);
-		PCI_CFG_W32(pcidev, PCI_PREF_LIMIT_UPPER32, 0);
+		PCI_CFG_W32(pcidev, PCIR_PMBASEH_1, 0);
+		PCI_CFG_W32(pcidev, PCIR_PMLIMITH_1, 0);
 
-		cmd |= PCI_COMMAND_MASTER;
-		romofs = PCI_ROM_ADDRESS1;
+		cmd |= PCIM_CMD_BUSMASTEREN;
+		romofs = PCIR_BIOS_1;
 		maxbars = 2;
 	}
 
@@ -127,20 +127,20 @@ static int pci_init_dev(struct pci_dev *dev, void *unused)
 	for (i = 0; i < maxbars; i++) {
 		res = &dev->resources[i];
 		if (res->flags & PCI_RES_TYPE_MASK) {
-			PCI_CFG_W32(pcidev, PCI_BASE_ADDRESS_0 + 4*i,
+			PCI_CFG_W32(pcidev, PCIR_BAR(0) + 4*i,
 								res->start);
 			if ((res->flags & PCI_RES_TYPE_MASK) == PCI_RES_IO)
-				cmd |= PCI_COMMAND_IO;
+				cmd |= PCIM_CMD_PORTEN;
 			else
-				cmd |= PCI_COMMAND_MEMORY;
+				cmd |= PCIM_CMD_MEMEN;
 		}
 	}
 	res = &dev->resources[DEV_RES_ROM];
 	if (res->flags & PCI_RES_TYPE_MASK) {
-		PCI_CFG_W32(pcidev, romofs, res->start|PCI_ROM_ADDRESS_ENABLE);
-		cmd |= PCI_COMMAND_MEMORY;
+		PCI_CFG_W32(pcidev, romofs, res->start|PCIM_BIOS_ENABLE);
+		cmd |= PCIM_CMD_MEMEN;
 	}
-	PCI_CFG_W16(pcidev, PCI_COMMAND, cmd);
+	PCI_CFG_W16(pcidev, PCIR_COMMAND, cmd);
 
 	return 0;
 }