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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-27 15:04:38 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-27 15:06:55 +0200 |
| commit | 44c2d393bdd58e4eedfccdfd406afc6914cc4acb (patch) | |
| tree | 74b7fffc48e2157a12773ef55d368354d1a05913 /cpukit/libmisc/dummy | |
| parent | riscv: Rework CPU counter support (diff) | |
| download | rtems-44c2d393bdd58e4eedfccdfd406afc6914cc4acb.tar.bz2 | |
bsp/riscv: Fix inter-processor interrupts
The previous version worked only on a patched Qemu. Writes to mip are
illegal according to the The RISC-V Instruction Set Manual, Volume II:
Privileged Architecture, Privileged Architecture Version 1.10.
Update #3433.
Diffstat (limited to 'cpukit/libmisc/dummy')
0 files changed, 0 insertions, 0 deletions