Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step.  It
copied header files from arbitrary locations into the build tree.  The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

* The make preinstall step itself needs time and disk space.

* Errors in header files show up in the build tree copy.  This makes it
  hard for editors to open the right file to fix the error.

* There is no clear relationship between source and build tree header
  files.  This makes an audit of the build process difficult.

* The visibility of all header files in the build tree makes it
  difficult to enforce API barriers.  For example it is discouraged to
  use BSP-specifics in the cpukit.

* An introduction of a new build system is difficult.

* Include paths specified by the -B option are system headers.  This
  may suppress warnings.

* The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step.   All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc.  Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

* cpukit/include

* cpukit/score/cpu/@RTEMS_CPU@/include

* cpukit/libnetworking

The new BSP include directories are:

* bsps/include

* bsps/@RTEMS_CPU@/include

* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed.  The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

3 files changed, 680 insertions, 0 deletions

diff --git a/cpukit/include/linux/i2c-dev.h b/cpukit/include/linux/i2c-dev.h
new file mode 100644
index 0000000000..c0db3fe06c
--- /dev/null
+++ b/cpukit/include/linux/i2c-dev.h
@@ -0,0 +1,137 @@
+/**
+ * @file
+ *
+ * @brief RTEMS Port of Linux I2C Device API
+ *
+ * @ingroup I2CLinux
+ */
+
+/*
+ * Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _UAPI_LINUX_I2C_DEV_H
+#define _UAPI_LINUX_I2C_DEV_H
+
+#include <stdint.h>
+
+/**
+ * @addtogroup I2CLinux
+ *
+ * @{
+ */
+
+/**
+ * @name I2C IO Control Commands
+ *
+ * @{
+ */
+
+/**
+ * @brief Sets the count of transfer retries in case a slave
+ * device does not acknowledge a transaction.
+ *
+ * The argument type is unsigned long.
+ */
+#define I2C_RETRIES 0x701
+
+/**
+ * @brief Sets the transfer timeout in 10ms units.
+ *
+ * The argument type is unsigned long.
+ */
+#define I2C_TIMEOUT 0x702
+
+/**
+ * @brief Sets the slave address.
+ *
+ * It is an error to set a slave address already used by another slave device.
+ *
+ * The argument type is unsigned long.
+ */
+#define I2C_SLAVE 0x703
+
+/**
+ * @brief Forces setting the slave address.
+ *
+ * The argument type is unsigned long.
+ */
+#define I2C_SLAVE_FORCE 0x706
+
+/**
+ * @brief Enables 10-bit addresses if argument is non-zero, otherwise
+ * disables 10-bit addresses.
+ *
+ * The argument type is unsigned long.
+ */
+#define I2C_TENBIT 0x704
+
+/**
+ * @brief Gets the I2C controller functionality information.
+ *
+ * The argument type is a pointer to an unsigned long.
+ */
+#define I2C_FUNCS 0x705
+
+/**
+ * @brief Performs a combined read/write transfer.
+ *
+ * Only one stop condition is signalled.
+ *
+ * The argument type is a pointer to struct i2c_rdwr_ioctl_data.
+ */
+#define I2C_RDWR 0x707
+
+/**
+ * @brief Enables System Management Bus (SMBus) Packet Error Checking (PEC)
+ * if argument is non-zero, otherwise disables PEC.
+ *
+ * The argument type is unsigned long.
+ */
+#define I2C_PEC 0x708
+
+/**
+ * @brief Performs an SMBus transfer.
+ *
+ * The argument type is a pointer to struct i2c_smbus_ioctl_data.
+ */
+#define I2C_SMBUS 0x720
+
+/** @} */
+
+/**
+ * @brief Argument type for I2C_SMBUS IO control call.
+ */
+struct i2c_smbus_ioctl_data {
+  uint8_t read_write;
+  uint8_t command;
+  uint32_t size;
+  union i2c_smbus_data *data;
+};
+
+/**
+ * @brief Argument type for I2C_RDWR IO control call.
+ */
+struct i2c_rdwr_ioctl_data {
+  struct i2c_msg *msgs;
+  uint32_t nmsgs;
+};
+
+/**
+ * @brief Maximum count of messages for one IO control call.
+ */
+#define I2C_RDRW_IOCTL_MAX_MSGS 42
+
+/** @} */
+
+#endif /* _UAPI_LINUX_I2C_DEV_H */
diff --git a/cpukit/include/linux/i2c.h b/cpukit/include/linux/i2c.h
new file mode 100644
index 0000000000..b113545cce
--- /dev/null
+++ b/cpukit/include/linux/i2c.h
@@ -0,0 +1,275 @@
+/**
+ * @file
+ *
+ * @brief RTEMS Port of Linux I2C API
+ *
+ * @ingroup I2CLinux
+ */
+
+/*
+ * Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _UAPI_LINUX_I2C_H
+#define _UAPI_LINUX_I2C_H
+
+#include <stdint.h>
+
+/**
+ * @defgroup I2CLinux Linux I2C User-Space API
+ *
+ * @ingroup I2C
+ *
+ * @brief RTEMS port of Linux I2C user-space API.
+ *
+ * Additional documentation is available through the Linux sources, see:
+ *
+ * - /usr/src/linux/include/uapi/linux/i2c.h,
+ * - /usr/src/linux/include/uapi/linux/i2c-dev.h
+ * - https://www.kernel.org/doc/Documentation/i2c/i2c-protocol
+ * - https://www.kernel.org/doc/Documentation/i2c/dev-interface
+ *
+ * @{
+ */
+
+/**
+ * @name I2C Message Flags
+ *
+ * @{
+ */
+
+/**
+ * @brief I2C message flag to indicate a 10-bit address.
+ *
+ * The controller must support this as indicated by the I2C_FUNC_10BIT_ADDR
+ * functionality.
+ *
+ * @see i2c_msg.
+ */
+#define I2C_M_TEN 0x0010
+
+/**
+ * @brief I2C message flag to indicate a read transfer (from slave to master).
+ *
+ * @see i2c_msg.
+ */
+#define I2C_M_RD 0x0001
+
+/**
+ * @brief I2C message flag to signal a stop condition even if this is not the
+ * last message.
+ *
+ * The controller must support this as indicated by the
+ * @ref I2C_FUNC_PROTOCOL_MANGLING functionality.
+ *
+ * @see i2c_msg.
+ */
+#define I2C_M_STOP 0x8000
+
+/**
+ * @brief I2C message flag to omit start condition and slave address.
+ *
+ * The controller must support this as indicated by the
+ * @ref I2C_FUNC_NOSTART functionality.
+ *
+ * @see i2c_msg.
+ */
+#define I2C_M_NOSTART 0x4000
+
+/**
+ * @brief I2C message flag to reverse the direction flag.
+ *
+ * The controller must support this as indicated by the
+ * @ref I2C_FUNC_PROTOCOL_MANGLING functionality.
+ *
+ * @see i2c_msg.
+ */
+#define I2C_M_REV_DIR_ADDR 0x2000
+
+/**
+ * @brief I2C message flag to ignore a non-acknowledge.
+ *
+ * The controller must support this as indicated by the
+ * @ref I2C_FUNC_PROTOCOL_MANGLING functionality.
+ *
+ * @see i2c_msg.
+ */
+#define I2C_M_IGNORE_NAK 0x1000
+
+/**
+ * @brief I2C message flag to omit a master acknowledge/non-acknowledge in a
+ * read transfer.
+ *
+ * The controller must support this as indicated by the
+ * @ref I2C_FUNC_PROTOCOL_MANGLING functionality.
+ *
+ * @see i2c_msg.
+ */
+#define I2C_M_NO_RD_ACK 0x0800
+
+/**
+ * @brief I2C message flag to indicate that the message data length is the
+ * first received byte.
+ *
+ * The message data buffer must be large enough to store up to 32 bytes, the
+ * initial length byte and the SMBus PEC (if used).  Initialize the message
+ * length to one.  The message length is incremented by the count of received
+ * data bytes.
+ *
+ * @see i2c_msg.
+ */
+#define I2C_M_RECV_LEN 0x0400
+
+/** @} */
+
+/**
+ * @brief I2C transfer message.
+ */
+struct i2c_msg {
+  /**
+   * @brief The slave address.
+   *
+   * In case the @ref I2C_M_TEN flag is set, then this is a 10-bit address,
+   * otherwise it is a 7-bit address.
+   */
+  uint16_t addr;
+
+  /**
+   * @brief The message flags.
+   *
+   * Valid flags are
+   * - @ref I2C_M_TEN,
+   * - @ref I2C_M_RD,
+   * - @ref I2C_M_STOP,
+   * - @ref I2C_M_NOSTART,
+   * - @ref I2C_M_REV_DIR_ADDR,
+   * - @ref I2C_M_IGNORE_NAK,
+   * - @ref I2C_M_NO_RD_ACK, and
+   * - @ref I2C_M_RECV_LEN.
+   */
+  uint16_t flags;
+
+  /**
+   * @brief The message data length in bytes.
+   */
+  uint16_t len;
+
+  /**
+   * @brief Pointer to the message data.
+   */
+  uint8_t *buf;
+};
+
+/**
+ * @name I2C Controller Functionality
+ *
+ * @{
+ */
+
+#define I2C_FUNC_I2C 0x00000001
+#define I2C_FUNC_10BIT_ADDR 0x00000002
+#define I2C_FUNC_PROTOCOL_MANGLING 0x00000004
+#define I2C_FUNC_SMBUS_PEC 0x00000008
+#define I2C_FUNC_NOSTART 0x00000010
+#define I2C_FUNC_SMBUS_BLOCK_PROC_CALL 0x00008000
+#define I2C_FUNC_SMBUS_QUICK 0x00010000
+#define I2C_FUNC_SMBUS_READ_BYTE 0x00020000
+#define I2C_FUNC_SMBUS_WRITE_BYTE 0x00040000
+#define I2C_FUNC_SMBUS_READ_BYTE_DATA 0x00080000
+#define I2C_FUNC_SMBUS_WRITE_BYTE_DATA 0x00100000
+#define I2C_FUNC_SMBUS_READ_WORD_DATA 0x00200000
+#define I2C_FUNC_SMBUS_WRITE_WORD_DATA 0x00400000
+#define I2C_FUNC_SMBUS_PROC_CALL 0x00800000
+#define I2C_FUNC_SMBUS_READ_BLOCK_DATA 0x01000000
+#define I2C_FUNC_SMBUS_WRITE_BLOCK_DATA 0x02000000
+#define I2C_FUNC_SMBUS_READ_I2C_BLOCK 0x04000000
+#define I2C_FUNC_SMBUS_WRITE_I2C_BLOCK 0x08000000
+
+#define I2C_FUNC_SMBUS_BYTE \
+  (I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE)
+
+#define I2C_FUNC_SMBUS_BYTE_DATA \
+  (I2C_FUNC_SMBUS_READ_BYTE_DATA | I2C_FUNC_SMBUS_WRITE_BYTE_DATA)
+
+#define I2C_FUNC_SMBUS_WORD_DATA \
+  (I2C_FUNC_SMBUS_READ_WORD_DATA | I2C_FUNC_SMBUS_WRITE_WORD_DATA)
+
+#define I2C_FUNC_SMBUS_BLOCK_DATA \
+  (I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_BLOCK_DATA)
+
+#define I2C_FUNC_SMBUS_I2C_BLOCK \
+  (I2C_FUNC_SMBUS_READ_I2C_BLOCK | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)
+
+#define I2C_FUNC_SMBUS_EMUL \
+  (I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA \
+    | I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_PROC_CALL \
+    | I2C_FUNC_SMBUS_WRITE_BLOCK_DATA | I2C_FUNC_SMBUS_I2C_BLOCK \
+    | I2C_FUNC_SMBUS_PEC)
+
+/** @} */
+
+/**
+ * @brief Maximum SMBus data block count.
+ */
+#define I2C_SMBUS_BLOCK_MAX 32
+
+/**
+ * @brief SMBus data.
+ */
+union i2c_smbus_data {
+  uint8_t byte;
+  uint16_t word;
+  uint8_t block[I2C_SMBUS_BLOCK_MAX + 2];
+};
+
+/**
+ * @name SMBus Transfer Read and Write Markers
+ *
+ * @{
+ */
+
+#define I2C_SMBUS_READ 1
+
+#define I2C_SMBUS_WRITE 0
+
+/** @} */
+
+/**
+ * @name SMBus Transaction Types
+ *
+ * @{
+ */
+
+#define I2C_SMBUS_QUICK 0
+
+#define I2C_SMBUS_BYTE 1
+
+#define I2C_SMBUS_BYTE_DATA 2
+
+#define I2C_SMBUS_WORD_DATA 3
+
+#define I2C_SMBUS_PROC_CALL 4
+
+#define I2C_SMBUS_BLOCK_DATA 5
+
+#define I2C_SMBUS_I2C_BLOCK_BROKEN 6
+
+#define I2C_SMBUS_BLOCK_PROC_CALL 7
+
+#define I2C_SMBUS_I2C_BLOCK_DATA 8
+
+/** @} */
+
+/** @} */
+
+#endif /* _UAPI_LINUX_I2C_H */
diff --git a/cpukit/include/linux/spi/spidev.h b/cpukit/include/linux/spi/spidev.h
new file mode 100644
index 0000000000..e2fdb4b7e1
--- /dev/null
+++ b/cpukit/include/linux/spi/spidev.h
@@ -0,0 +1,268 @@
+/**
+ * @file
+ *
+ * @brief RTEMS Port of Linux SPI API
+ *
+ * @ingroup SPILinux
+ */
+
+/*
+ * Copyright (c) 2016 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _UAPI_LINUX_SPI_H
+#define _UAPI_LINUX_SPI_H
+
+#include <sys/ioccom.h>
+#include <stddef.h>
+#include <stdint.h>
+
+/**
+ * @defgroup SPILinux Linux SPI User-Space API
+ *
+ * @ingroup SPI
+ *
+ * @brief RTEMS port of Linux SPI user-space API.
+ *
+ * Additional documentation is available through the Linux sources, see
+ *
+ * /usr/src/linux/include/uapi/linux/spidev.h.
+ *
+ * @{
+ */
+
+/**
+ * @name SPI Transfer Flags
+ *
+ * @{
+ */
+
+/**
+ * @brief SPI transfer flag which sets the clock phase.
+ */
+#define SPI_CPHA 0x01
+
+/**
+ * @brief SPI transfer flag which sets the clock polarity.
+ */
+#define SPI_CPOL 0x02
+
+/**
+ * @brief SPI transfer flag which sets SPI Mode 0 (clock starts low, sample on
+ * leading edge).
+ */
+#define SPI_MODE_0 0
+
+/**
+ * @brief SPI transfer flag which sets SPI Mode 0 (clock starts low, sample on
+ * trailing edge).
+ */
+#define SPI_MODE_1 SPI_CPHA
+
+/**
+ * @brief SPI transfer flag which sets SPI Mode 0 (clock starts high, sample on
+ * leading edge).
+ */
+#define SPI_MODE_2 SPI_CPOL
+
+/**
+ * @brief SPI transfer flag which sets SPI Mode 0 (clock starts high, sample on
+ * trailing edge).
+ */
+#define SPI_MODE_3 (SPI_CPOL | SPI_CPHA)
+
+/**
+ * @brief SPI transfer flag which selects the device by setting the chip select
+ * line.
+ */
+#define SPI_CS_HIGH 0x04
+
+/**
+ * @brief SPI transfer flag which triggers data transmission with the LSB being
+ * sent first.
+ */
+#define SPI_LSB_FIRST 0x08
+
+/**
+ * @brief SPI transfer flag which uses a shared wire for master input/slave
+ * output as well as master output/slave input.
+ */
+#define SPI_3WIRE 0x10
+
+/**
+ * @brief SPI transfer flag which initiates the loopback mode.
+ */
+#define SPI_LOOP 0x20
+
+/**
+ * @brief SPI transfer flag which indicates that no chip select is needed due to
+ * only one device on the bus.
+ */
+#define SPI_NO_CS 0x40
+
+/**
+ * @brief SPI transfer flag which pulls the slave to low level during pause.
+ */
+#define SPI_READY 0x80
+
+/**
+ * @brief SPI transfer flag which sets up dual mode for transmission.
+ */
+#define SPI_TX_DUAL 0x100
+
+/**
+ * @brief SPI transfer flag which sets up quad mode for transmission.
+ */
+#define SPI_TX_QUAD 0x200
+
+/**
+ * @brief SPI transfer flag which sets up dual mode for reception.
+ */
+#define SPI_RX_DUAL 0x400
+
+/**
+ * @brief SPI transfer flag which sets up quad mode for reception.
+ */
+#define SPI_RX_QUAD 0x800
+
+/** @} */
+
+#define SPI_IOC_MAGIC 's'
+
+/**
+ * @brief SPI transfer message.
+ */
+struct spi_ioc_transfer {
+  /**
+   * @brief Buffer for receive data.
+   */
+  void *rx_buf;
+
+  /**
+   * @brief Buffer for transmit data.
+   */
+  const void *tx_buf;
+
+  /**
+   * @brief Length of receive and transmit buffers in bytes.
+   */
+  size_t len;
+
+  /**
+   * @brief Sets the bit-rate of the device.
+   */
+  uint32_t speed_hz;
+
+  /**
+   * @brief Sets the delay after a transfer before the chip select status is
+   * changed and the next transfer is triggered.
+   */
+  uint16_t delay_usecs;
+
+  /**
+   * @brief Sets the device wordsize.
+   */
+  uint8_t bits_per_word;
+
+  /**
+   * @brief If true, device is deselected after transfer ended and before a new
+   * transfer is started.
+   */
+  uint8_t cs_change;
+
+  /**
+   * @brief Amount of bits that are used for reading.
+   */
+  uint8_t rx_nbits;
+
+  /**
+   * @brief Amount of bits that are used for writing.
+   */
+  uint8_t tx_nbits;
+
+  /**
+   * @brief Sets one of the possible modes that can be used for SPI transfers
+   * (dependent on clock phase and polarity).
+   */
+  uint32_t mode;
+
+  /**
+   * @brief Indicates which device is currently used.
+   */
+  uint8_t cs;
+};
+
+/**
+ * @brief Calculates the size of the SPI message array.
+ */
+#define SPI_MSGSIZE(n) \
+  (((n) * sizeof(struct spi_ioc_transfer) < IOCPARM_MAX) ? \
+    (n) * sizeof(struct spi_ioc_transfer) : 0)
+
+/**
+ * @brief Transfers an array with SPI messages.
+ */
+#define SPI_IOC_MESSAGE(n) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(n)])
+
+/**
+ * @brief Reads the least-significant 8-bits of the SPI default mode.
+ */
+#define SPI_IOC_RD_MODE _IOR(SPI_IOC_MAGIC, 1, uint8_t)
+
+/**
+ * @brief Writes the SPI default mode (the most-significant 24-bits of the mode are
+ * set to zero).
+ */
+#define SPI_IOC_WR_MODE _IOW(SPI_IOC_MAGIC, 1, uint8_t)
+
+/**
+ * @brief Reads the SPI default least-significant bit first setting.
+ */
+#define SPI_IOC_RD_LSB_FIRST _IOR(SPI_IOC_MAGIC, 2, uint8_t)
+
+/**
+ * @brief Writes the SPI default least-significant-bit first setting.
+ */
+#define SPI_IOC_WR_LSB_FIRST _IOW(SPI_IOC_MAGIC, 2, uint8_t)
+
+/**
+ * @brief Reads the SPI default bits per word.
+ */
+#define SPI_IOC_RD_BITS_PER_WORD _IOR(SPI_IOC_MAGIC, 3, uint8_t)
+
+/**
+ * @brief Writes the SPI default bits per word.
+ */
+#define SPI_IOC_WR_BITS_PER_WORD _IOW(SPI_IOC_MAGIC, 3, uint8_t)
+
+/**
+ * @brief Reads the SPI default speed in Hz.
+ */
+#define SPI_IOC_RD_MAX_SPEED_HZ _IOR(SPI_IOC_MAGIC, 4, uint32_t)
+
+/**
+ * @brief Writes the SPI default speed in Hz.
+ */
+#define SPI_IOC_WR_MAX_SPEED_HZ _IOW(SPI_IOC_MAGIC, 4, uint32_t)
+
+/**
+ * @brief Reads the full 32-bit SPI default mode.
+ */
+#define SPI_IOC_RD_MODE32 _IOR(SPI_IOC_MAGIC, 5, uint32_t)
+
+/**
+ * @brief Writes the full 32-bit SPI default mode.
+ */
+#define SPI_IOC_WR_MODE32 _IOW(SPI_IOC_MAGIC, 5, uint32_t)
+
+#endif /* _UAPI_LINUX_SPI_H */