diff options
| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2007-09-06 13:25:42 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2007-09-06 13:25:42 +0000 |
| commit | e16e0caf72ca74b2f94c04ebeaac63bc460c5e6c (patch) | |
| tree | 7ac3782574e95031c0d1fbe418a45fe6117046ac /c | |
| parent | 2007-09-06 Daniel Hellstrom <daniel@gaisler.com> (diff) | |
| download | rtems-e16e0caf72ca74b2f94c04ebeaac63bc460c5e6c.tar.bz2 | |
2007-09-06 Daniel Hellstrom <daniel@gaisler.com>
* Makefile.am: Add the following new drivers: PCI, b1553BRM,
SpaceWire(GRSPW), CAN (GRCAN,OC_CAN), Raw UART.
* shared/include/apbuart.h, shared/include/apbuart_pci.h,
shared/include/apbuart_rasta.h, shared/include/b1553brm.h,
shared/include/b1553brm_pci.h, shared/include/b1553brm_rasta.h,
shared/include/debug_defs.h, shared/include/grcan.h,
shared/include/grcan_rasta.h, shared/include/grcan_spwrtc.h,
shared/include/grspw.h, shared/include/grspw_pci.h,
shared/include/grspw_rasta.h, shared/include/occan.h,
shared/include/occan_pci.h, shared/include/pci.h: New files.
Diffstat (limited to 'c')
18 files changed, 2402 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/sparc/ChangeLog b/c/src/lib/libbsp/sparc/ChangeLog index 76ac229f1d..a8ec7f5029 100644 --- a/c/src/lib/libbsp/sparc/ChangeLog +++ b/c/src/lib/libbsp/sparc/ChangeLog @@ -1,3 +1,17 @@ +2007-09-06 Daniel Hellstrom <daniel@gaisler.com> + + * Makefile.am: Add the following new drivers: PCI, b1553BRM, + SpaceWire(GRSPW), CAN (GRCAN,OC_CAN), Raw UART. + * shared/include/apbuart.h, shared/include/apbuart_pci.h, + shared/include/apbuart_rasta.h, shared/include/b1553brm.h, + shared/include/b1553brm_pci.h, shared/include/b1553brm_rasta.h, + shared/include/debug_defs.h, shared/include/grcan.h, + shared/include/grcan_rasta.h, shared/include/grcan_spwrtc.h, + shared/include/grspw.h, shared/include/grspw_pci.h, + shared/include/grspw_rasta.h, shared/include/occan.h, + shared/include/occan_pci.h, shared/include/pci.h: New files. + + 2007-09-05 Daniel Hellstrom <daniel@gaisler.com> * shared/bspstart.c: LEON2 and LEON3 Data cache snooping detection on diff --git a/c/src/lib/libbsp/sparc/Makefile.am b/c/src/lib/libbsp/sparc/Makefile.am index c161d57d8e..3f2bfff9a4 100644 --- a/c/src/lib/libbsp/sparc/Makefile.am +++ b/c/src/lib/libbsp/sparc/Makefile.am @@ -18,5 +18,46 @@ EXTRA_DIST += shared/start.S EXTRA_DIST += shared/include/ambapp.h EXTRA_DIST += shared/amba/ambapp.c +# PCI bus +EXTRA_DIST += shared/include/pci.h +EXTRA_DIST += shared/pci/pcifinddevice.c + +# DEBUG +EXTRA_DIST += shared/include/debug_defs.h + +# SpaceWire (GRSPW) +EXTRA_DIST += shared/spw/grspw.c +EXTRA_DIST += shared/spw/grspw_pci.c +EXTRA_DIST += shared/spw/grspw_rasta.c +EXTRA_DIST += shared/include/grspw.h +EXTRA_DIST += shared/include/grspw_pci.h +EXTRA_DIST += shared/include/grspw_rasta.h + +# UART (APBUART) +EXTRA_DIST += shared/uart/apbuart.c +EXTRA_DIST += shared/uart/apbuart_pci.c +EXTRA_DIST += shared/uart/apbuart_rasta.c +EXTRA_DIST += shared/include/apbuart.h +EXTRA_DIST += shared/include/apbuart_pci.h +EXTRA_DIST += shared/include/apbuart_rasta.h + +# CAN (OC_CAN, GRCAN) +EXTRA_DIST += shared/can/occan.c +EXTRA_DIST += shared/can/occan_pci.c +EXTRA_DIST += shared/can/grcan.c +EXTRA_DIST += shared/can/grcan_rasta.c +EXTRA_DIST += shared/include/occan.h +EXTRA_DIST += shared/include/occan_pci.h +EXTRA_DIST += shared/include/grcan.h +EXTRA_DIST += shared/include/grcan_rasta.h + +# MIL-STD-B1553 (Core1553BRM) +EXTRA_DIST += shared/1553/b1553brm.c +EXTRA_DIST += shared/1553/b1553brm_pci.c +EXTRA_DIST += shared/1553/b1553brm_rasta.c +EXTRA_DIST += shared/include/b1553brm.h +EXTRA_DIST += shared/include/b1553brm_pci.h +EXTRA_DIST += shared/include/b1553brm_rasta.h + include $(top_srcdir)/../../../automake/subdirs.am include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/lib/libbsp/sparc/shared/include/apbuart.h b/c/src/lib/libbsp/sparc/shared/include/apbuart.h new file mode 100644 index 0000000000..c8a6e35fec --- /dev/null +++ b/c/src/lib/libbsp/sparc/shared/include/apbuart.h @@ -0,0 +1,83 @@ +/* + * Driver interface for APBUART + * + * COPYRIGHT (c) 2007. + * Gaisler Research + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + */ + +#ifndef __APBUART_H__ +#define __APBUART_H__ + +#include <ambapp.h> + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + unsigned int hw_dovr; + unsigned int hw_parity; + unsigned int hw_frame; + unsigned int sw_dovr; + unsigned int rx_cnt; + unsigned int tx_cnt; +} apbuart_stats; + +#define APBUART_START 0 +#define APBUART_STOP 1 +#define APBUART_SET_RXFIFO_LEN 2 +#define APBUART_SET_TXFIFO_LEN 3 +#define APBUART_SET_BAUDRATE 4 +#define APBUART_SET_SCALER 5 +#define APBUART_SET_BLOCKING 6 +#define APBUART_SET_ASCII_MODE 7 + + +#define APBUART_GET_STATS 16 +#define APBUART_CLR_STATS 17 + +#define APBUART_BLK_RX 0x1 +#define APBUART_BLK_TX 0x2 +#define APBUART_BLK_FLUSH 0x4 + + +#define APBUART_CTRL_RE 0x1 +#define APBUART_CTRL_TE 0x2 +#define APBUART_CTRL_RI 0x4 +#define APBUART_CTRL_TI 0x8 +#define APBUART_CTRL_PS 0x10 +#define APBUART_CTRL_PE 0x20 +#define APBUART_CTRL_FL 0x40 +#define APBUART_CTRL_LB 0x80 +#define APBUART_CTRL_EC 0x100 +#define APBUART_CTRL_TF 0x200 +#define APBUART_CTRL_RF 0x400 + +#define APBUART_STATUS_DR 0x1 +#define APBUART_STATUS_TS 0x2 +#define APBUART_STATUS_TE 0x4 +#define APBUART_STATUS_BR 0x8 +#define APBUART_STATUS_OV 0x10 +#define APBUART_STATUS_PE 0x20 +#define APBUART_STATUS_FE 0x40 +#define APBUART_STATUS_TH 0x80 +#define APBUART_STATUS_RH 0x100 +#define APBUART_STATUS_TF 0x200 +#define APBUART_STATUS_RF 0x400 + +/* Register APBUART driver + * bus = pointer to AMBA bus description used to search for APBUART(s). + * (&amba_conf for LEON3), (LEON2: see amba_scan) + */ +int apbuart_register (amba_confarea_type * bus); + +#ifdef __cplusplus +} +#endif + +#endif /* __APBUART_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/apbuart_pci.h b/c/src/lib/libbsp/sparc/shared/include/apbuart_pci.h new file mode 100644 index 0000000000..ac3a548912 --- /dev/null +++ b/c/src/lib/libbsp/sparc/shared/include/apbuart_pci.h @@ -0,0 +1,43 @@ +/* + * APBUART via PCI - driver interface + * + * COPYRIGHT (c) 2007. + * Gaisler Research + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + */ + +#ifndef __APBUART_PCI_H__ +#define __APBUART_PCI_H__ + +#include <apbuart.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Register APBUART driver, if APBUART devices are found. + * bus = pointer to AMBA bus description used to search for APBUART(s). + * + */ + +int apbuart_pci_register (amba_confarea_type * bus); + +/* This function must be called on APBUART interrupt. Called from the + * PCI interrupt handler. + * irq = AMBA IRQ assigned to the APBUART device, is found by reading + * pending register on IRQMP connected to the APBUART device. + * + */ +void apbuartpci_interrupt_handler (int irq, void *arg); + +extern void (*apbuart_pci_int_reg) (void *handler, int irq, void *arg); + +#ifdef __cplusplus +} +#endif + +#endif /* __APBUART_PCI_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/apbuart_rasta.h b/c/src/lib/libbsp/sparc/shared/include/apbuart_rasta.h new file mode 100644 index 0000000000..183ceec781 --- /dev/null +++ b/c/src/lib/libbsp/sparc/shared/include/apbuart_rasta.h @@ -0,0 +1,43 @@ +/* + * APBUART RASTA via PCI - driver interface + * + * COPYRIGHT (c) 2007. + * Gaisler Research + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + */ + +#ifndef __APBUART_RASTA_H__ +#define __APBUART_RASTA_H__ + +#include <apbuart.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Register APBUART driver, if APBUART devices are found. + * bus = pointer to AMBA bus description used to search for APBUART(s). + * + */ + +int apbuart_rasta_register(amba_confarea_type *bus); + +/* This function must be called on APBUART interrupt. Called from the + * RASTA interrupt handler. + * irq = AMBA IRQ assigned to the APBUART device, is found by reading + * pending register on IRQMP connected to the APBUART device. + * + */ +void apbuartrasta_interrupt_handler(int irq, void *arg); + +extern void (*apbuart_rasta_int_reg)(void *handler, int irq, void *arg); + +#ifdef __cplusplus +} +#endif + +#endif /* __APBUART_RASTA_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/b1553brm.h b/c/src/lib/libbsp/sparc/shared/include/b1553brm.h new file mode 100644 index 0000000000..e2d8a29242 --- /dev/null +++ b/c/src/lib/libbsp/sparc/shared/include/b1553brm.h @@ -0,0 +1,169 @@ + /* + * Macros used for brm controller + * + * COPYRIGHT (c) 2006. + * Gaisler Research + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + */ + +#ifndef __B1553BRM_H__ +#define __B1553BRM_H__ + +#include <ambapp.h> + +#ifdef __cplusplus +extern "C" { +#endif + +struct brm_reg { + volatile unsigned int ctrl; /* 0x00 */ + volatile unsigned int oper; /* 0x04 */ + volatile unsigned int cur_cmd; /* 0x08 */ + volatile unsigned int imask; /* 0x0C */ + volatile unsigned int ipend; /* 0x10 */ + volatile unsigned int ipoint; /* 0x14 */ + volatile unsigned int bit_reg; /* 0x18 */ + volatile unsigned int ttag; /* 0x1C */ + volatile unsigned int dpoint; /* 0x20 */ + volatile unsigned int sw; /* 0x24 */ + volatile unsigned int initcount; /* 0x28 */ + volatile unsigned int mcpoint; /* 0x2C */ + volatile unsigned int mdpoint; /* 0x30 */ + volatile unsigned int mbc; /* 0x34 */ + volatile unsigned int mfilta; /* 0x38 */ + volatile unsigned int mfiltb; /* 0x3C */ + volatile unsigned int rt_cmd_leg[16]; /* 0x40-0x80 */ + volatile unsigned int enhanced; /* 0x84 */ + + volatile unsigned int dummy[31]; + + volatile unsigned int w_ctrl; /* 0x100 */ + volatile unsigned int w_irqctrl; /* 0x104 */ + volatile unsigned int w_ahbaddr; /* 0x108 */ +}; + +struct bm_msg { + unsigned short miw; + unsigned short cw1; + unsigned short cw2; + unsigned short sw1; + unsigned short sw2; + unsigned short time; + unsigned short data[32]; +}; + +struct rt_msg { + unsigned short miw; + unsigned short time; + unsigned short data[32]; + unsigned short desc; +}; + +/* + * rtaddr[0] and subaddr[0] : RT address and subaddress (for rt-rt receive addresses) + * rtaddr[1] and subaddr[1] : Only for RT-RT. Transmit addresses. + * + * wc : word count, or mode code if subaddress 0 or 31. + * + * ctrl, bit 0 (TR) : 1 - transmit, 0 - receive. Ignored for rt-rt + * bit 1 (RTRT) : 1 - rt to rt, 0 - normal + * bit 2 (AB) : 1 - Bus B, 0 - Bus A + * bit 4:3 (Retry) : 1 - 1, 2 - 2, 3 - 3, 0 - 4 + * bit 5 (END) : End of list + * bit 15 (BAME) : Message error. Set by BRM if protocol error is detected + * + * tsw[0] : status word + * tsw[1] : Only for rt-rt, status word 2 + * + * data : data to be transmitted, or received data + * + */ +struct bc_msg { + unsigned char rtaddr[2]; + unsigned char subaddr[2]; + unsigned short wc; + unsigned short ctrl; + unsigned short tsw[2]; + unsigned short data[32]; +}; + +/* BC control bits */ +#define BC_TR 0x0001 +#define BC_RTRT 0x0002 +#define BC_BUSA 0x0004 +#define BC_EOL 0x0020 +#define BC_BAME 0x8000 + +#define BRM_MBC_IRQ 1 /* Monitor Block Counter irq */ +#define BRM_CBA_IRQ 2 /* Command Block Accessed irq */ +#define BRM_RTF_IRQ 4 /* Retry Fail irq */ +#define BRM_ILLOP_IRQ 8 /* Illogical Opcode irq */ +#define BRM_BC_ILLCMD_IRQ 16 /* BC Illocigal Command irq */ +#define BRM_EOL_IRQ 32 /* End Of List irq */ +#define BRM_RT_ILLCMD_IRQ 128 /* RT Illegal Command irq */ +#define BRM_IXEQ0_IRQ 256 /* Index Equal Zero irq */ +#define BRM_BDRCV_IRQ 512 /* Broadcast Command Received irq */ +#define BRM_SUBAD_IRQ 1024 /* Subaddress Accessed irq */ +#define BRM_MERR_IRQ 4096 /* Message Error irq */ +#define BRM_TAPF_IRQ 8192 /* Terminal Address Parity Fail irq */ +#define BRM_WRAPF_IRQ 16384 /* Wrap Fail irq */ +#define BRM_DMAF_IRQ 32768 /* DMA Fail irq */ + + +#define BRM_SET_MODE 0 +#define BRM_SET_BUS 1 +#define BRM_SET_MSGTO 2 +#define BRM_SET_RT_ADDR 3 +#define BRM_SET_STD 4 +#define BRM_SET_BCE 5 +#define BRM_TX_BLOCK 7 +#define BRM_RX_BLOCK 8 + +#define BRM_DO_LIST 10 +#define BRM_LIST_DONE 11 + +#define BRM_CLR_STATUS 12 +#define BRM_GET_STATUS 13 +#define BRM_SET_EVENTID 14 + +#define GET_ERROR_DESCRIPTOR(event_in) (event_in>>16) + + +#define BRM_MODE_BC 0x0 +#define BRM_MODE_RT 0x1 +#define BRM_MODE_BM 0x2 +#define BRM_MODE_BM_RT 0x3 /* both RT and BM */ + + +/* Register RAMON FPGA BRM driver, calls brm_register */ +int brm_register_leon3_ramon_fpga(void); + +/* Register RAMON ASIC BRM driver, calls brm_register */ +int brm_register_leon3_ramon_asic(void); + +#define BRM_FREQ_12MHZ 0 +#define BRM_FREQ_16MHZ 1 +#define BRM_FREQ_20MHZ 2 +#define BRM_FREQ_24MHZ 3 +#define BRM_FREQ_MASK 0x3 + +#define CLKDIV_MASK 0xf + +#define CLKSEL_MASK 0x7 + +/* Register BRM driver + * See (struct brm_reg).w_ctrl for clksel and clkdiv. + * See Enhanced register (the least signinficant 2 bits) in BRM Core for brm_freq + * bus = &amba_conf for LEON3. (LEON2 not yet supported for this driver) + */ +int b1553brm_register(amba_confarea_type *bus, unsigned int clksel, unsigned int clkdiv, unsigned int brm_freq); + +#ifdef __cplusplus +} +#endif + +#endif /* __BRM_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/b1553brm_pci.h b/c/src/lib/libbsp/sparc/shared/include/b1553brm_pci.h new file mode 100644 index 0000000000..5e47e462f0 --- /dev/null +++ b/c/src/lib/libbsp/sparc/shared/include/b1553brm_pci.h @@ -0,0 +1,57 @@ + /* + * Macros used for brm controller + * + * COPYRIGHT (c) 2006. + * Gaisler Research + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + */ + +#ifndef __B1553BRM_PCI_H__ +#define __B1553BRM_PCI_H__ + +#include <b1553brm.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Register BRM driver + * See (struct brm_reg).w_ctrl for clksel and clkdiv. + * See Enhanced register (the least signinficant 2 bits) in BRM Core for brm_freq + * bus = &amba_conf for LEON3. (LEON2 not yet supported for this driver) + * + * Memory setup: + * memarea = 128k aligned pointer to memory (if zero malloc will be used) (as the CPU sees it) + * hw_address = address that HW must use to access memarea. (used in the translation process) + */ + +int b1553brm_pci_register( + amba_confarea_type *bus, + unsigned int clksel, + unsigned int clkdiv, + unsigned int brm_freq, + unsigned int memarea, + unsigned int hw_address + ); + + +/* This function must be called on BRM interrupt. Called from the + * PCI interrupt handler. irq = AMBA IRQ MASK assigned to the BRM device, + * is found by reading pending register on IRQMP connected to BRM + * device. + * + * Return 0=not handled. nono-zero=handled + */ +int b1553brm_pci_interrupt_handler(int irq, void *arg); + +extern void (*b1553brm_pci_int_reg)(void *handler, int irq, void *arg); + +#ifdef __cplusplus +} +#endif + +#endif /* __B1553BRM_PCI_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/b1553brm_rasta.h b/c/src/lib/libbsp/sparc/shared/include/b1553brm_rasta.h new file mode 100644 index 0000000000..9f77bc855d --- /dev/null +++ b/c/src/lib/libbsp/sparc/shared/include/b1553brm_rasta.h @@ -0,0 +1,57 @@ + /* + * Macros used for brm controller + * + * COPYRIGHT (c) 2006. + * Gaisler Research + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + */ + +#ifndef __B1553BRM_RASTA_H__ +#define __B1553BRM_RASTA_H__ + +#include <b1553brm.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Register BRM driver + * See (struct brm_reg).w_ctrl for clksel and clkdiv. + * See Enhanced register (the least signinficant 2 bits) in BRM Core for brm_freq + * bus = &amba_conf for LEON3. (LEON2 not yet supported for this driver) + * + * Memory setup: + * memarea = 128k aligned pointer to memory (if zero malloc will be used) (as the CPU sees it) + * hw_address = address that HW must use to access memarea. (used in the translation process) + */ + +int b1553brm_rasta_register( + amba_confarea_type *bus, + unsigned int clksel, + unsigned int clkdiv, + unsigned int brm_freq, + unsigned int memarea, + unsigned int hw_address + ); + + +/* This function must be called on BRM interrupt. Called from the + * PCI interrupt handler. irq = AMBA IRQ MASK assigned to the BRM device, + * is found by reading pending register on IRQMP connected to BRM + * device. + * + * Return 0=not handled. nono-zero=handled + */ +int b1553brm_rasta_interrupt_handler(int irq, void *arg); + +extern void (*b1553brm_rasta_int_reg)(void *handler, int irq, void *arg); + +#ifdef __cplusplus +} +#endif + +#endif /* __B1553BRM_RASTA_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/debug_defs.h b/c/src/lib/libbsp/sparc/shared/include/debug_defs.h new file mode 100644 index 0000000000..970230eb0a --- /dev/null +++ b/c/src/lib/libbsp/sparc/shared/include/debug_defs.h @@ -0,0 +1,40 @@ + +#ifndef __DEBUG_DEFS_H__ +#define __DEBUG_DEFS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef DEBUG + + #ifndef DEBUG_FLAGS + #define DEBUG_FLAGS 0 + #endif + + extern int DEBUG_printf(const char *fmt, ...); + #define DBG(fmt, args...) do { printk(" : %03d @ %18s()]:" fmt , __LINE__,__FUNCTION__,## args); } while(0) + #define DBG2(fmt) do { printk(" : %03d @ %18s()]:" fmt , __LINE__,__FUNCTION__); } while(0) + #define DBGC(c,fmt, args...) do { if (DEBUG_FLAGS & c) { printk(" : %03d @ %18s()]:" fmt , __LINE__,__FUNCTION__,## args); }} while(0) + +#else + + #define DBG(fmt, args...) + #define DBG2(fmt, args...) + #define DBGC(c, fmt, args...) + +#endif + +#ifdef DEBUGFUNCS + #define FUNCDBG() do { printk("%s\n\r",__FUNCTION__); } while(0) + extern int DEBUG_printf(const char *fmt, ...); +#else + #define FUNCDBG() +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __DEBUG_DEFS_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/grcan.h b/c/src/lib/libbsp/sparc/shared/include/grcan.h new file mode 100644 index 0000000000..88c15c1282 --- /dev/null +++ b/c/src/lib/libbsp/sparc/shared/include/grcan.h @@ -0,0 +1,203 @@ +/* + * Macros used for grcan controller + * + * COPYRIGHT (c) 2007. + * Gaisler Research + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + */ + +#ifndef __GRCAN_H__ +#define __GRCAN_H__ + +#include <ambapp.h> + +#ifdef __cplusplus +extern "C" { +#endif + +struct grcan_regs { + volatile unsigned int conf; /* 0x00 */ + volatile unsigned int stat; /* 0x04 */ + volatile unsigned int ctrl; /* 0x08 */ + volatile unsigned int dummy0[3]; /* 0x0C-0x014 */ + volatile unsigned int smask; /* 0x18 */ + volatile unsigned int scode; /* 0x1C */ + + volatile unsigned int dummy1[56]; /* 0x20-0xFC */ + + volatile unsigned int pimsr; /* 0x100 */ + volatile unsigned int pimr; /* 0x104 */ + volatile unsigned int pisr; /* 0x108 */ + volatile unsigned int pir; /* 0x10C */ + volatile unsigned int imr; /* 0x110 */ + volatile unsigned int picr; /* 0x114 */ + + volatile unsigned int dummy2[58]; /* 0x118-0x1FC */ + + volatile unsigned int tx0ctrl; /* 0x200 */ + volatile unsigned int tx0addr; /* 0x204 */ + volatile unsigned int tx0size; /* 0x208 */ + volatile unsigned int tx0wr; /* 0x20C */ + volatile unsigned int tx0rd; /* 0x210 */ + volatile unsigned int tx0irq; /* 0x214 */ + + volatile unsigned int dummy3[58]; /* 0x218-0x2FC */ + + volatile unsigned int rx0ctrl; /* 0x300 */ + volatile unsigned int rx0addr; /* 0x304 */ + volatile unsigned int rx0size; /* 0x308 */ + volatile unsigned int rx0wr; /* 0x30C */ + volatile unsigned int rx0rd; /* 0x310 */ + volatile unsigned int rx0irq; /* 0x314 */ + volatile unsigned int rx0mask; /* 0x318 */ + volatile unsigned int rx0code; /* 0x31C */ +}; + +struct grcan_stats { + unsigned int passive_cnt; + unsigned int overrun_cnt; + unsigned int rxsync_cnt; + unsigned int txsync_cnt; + unsigned int txloss_cnt; + unsigned int ahberr_cnt; + unsigned int ints; +}; + +struct grcan_timing { + unsigned char scaler; + unsigned char ps1; + unsigned char ps2; + unsigned int rsj; + unsigned char bpr; +}; + +struct grcan_selection { + int selection; + int enable0; + int enable1; +}; + +struct grcan_filter { + unsigned long long mask; + unsigned long long code; +}; + +/* CAN MESSAGE */ +typedef struct { + char extended; /* 1= Extended Frame (29-bit id), 0= STD Frame (11-bit id) */ + char rtr; /* RTR - Remote Transmission Request */ + char unused; /* unused */ + unsigned char len; + unsigned char data[8]; + unsigned int id; +} CANMsg; + +#define GRCAN_CFG_ABORT 0x00000001 +#define GRCAN_CFG_ENABLE0 0x00000002 +#define GRCAN_CFG_ENABLE1 0x00000004 +#define GRCAN_CFG_SELECTION 0x00000008 +#define GRCAN_CFG_SILENT 0x00000010 +#define GRCAN_CFG_BPR 0x00000300 +#define GRCAN_CFG_RSJ 0x00007000 +#define GRCAN_CFG_PS1 0x00f00000 +#define GRCAN_CFG_PS2 0x000f0000 +#define GRCAN_CFG_SCALER 0xff000000 + +#define GRCAN_CFG_BPR_BIT 8 +#define GRCAN_CFG_RSJ_BIT 12 +#define GRCAN_CFG_PS1_BIT 20 +#define GRCAN_CFG_PS2_BIT 16 +#define GRCAN_CFG_SCALER_BIT 24 + +#define GRCAN_CTRL_RESET 0x2 +#define GRCAN_CTRL_ENABLE 0x1 + +#define GRCAN_TXCTRL_ENABLE 1 +#define GRCAN_TXCTRL_ONGOING 1 + +#define GRCAN_RXCTRL_ENABLE 1 +#define GRCAN_RXCTRL_ONGOING 1 + +/* Relative offset of IRQ sources to AMBA Plug&Play */ +#define GRCAN_IRQ_IRQ 0 +#define GRCAN_IRQ_TXSYNC 1 +#define GRCAN_IRQ_RXSYNC 2 + +#define GRCAN_ERR_IRQ 0x1 +#define GRCAN_OFF_IRQ 0x2 +#define GRCAN_OR_IRQ 0x4 +#define GRCAN_RXAHBERR_IRQ 0x8 +#define GRCAN_TXAHBERR_IRQ 0x10 +#define GRCAN_RXIRQ_IRQ 0x20 +#define GRCAN_TXIRQ_IRQ 0x40 +#define GRCAN_RXFULL_IRQ 0x80 +#define GRCAN_TXEMPTY_IRQ 0x100 +#define GRCAN_RX_IRQ 0x200 +#define GRCAN_TX_IRQ 0x400 +#define GRCAN_RXSYNC_IRQ 0x800 +#define GRCAN_TXSYNC_IRQ 0x1000 +#define GRCAN_RXERR_IRQ 0x2000 +#define GRCAN_TXERR_IRQ 0x4000 +#define GRCAN_RXMISS_IRQ 0x8000 +#define GRCAN_TXLOSS_IRQ 0x10000 + +#define GRCAN_STAT_PASS 0x1 +#define GRCAN_STAT_OFF 0x2 +#define GRCAN_STAT_OR 0x4 +#define GRCAN_STAT_AHBERR 0x8 +#define GRCAN_STAT_ACTIVE 0x10 +#define GRCAN_STAT_RXERRCNT 0xff00 +#define GRCAN_STAT_TXERRCNT 0xff0000 + +/* IOCTL Commands controlling operational + * mode + */ +#define GRCAN_IOC_START 1 /* Bring the link up after open or bus-off */ +#define GRCAN_IOC_STOP 2 /* stop to change baud rate/config or closing down */ +#define GRCAN_IOC_ISSTARTED 3 /* return RTEMS_SUCCESSFUL when started, othervise EBUSY */ +#define GRCAN_IOC_FLUSH 4 /* Waits until all TX messages has been sent */ + +/* IOCTL Commands that require connection + * to be stopped + */ +#define GRCAN_IOC_SET_SILENT 16 /* enable silent mode read only state */ +#define GRCAN_IOC_SET_ABORT 17 /* enable/disable stopping link on AHB Error */ +#define GRCAN_IOC_SET_SELECTION 18 /* Set Enable0,Enable1,Selection */ +#define GRCAN_IOC_SET_SPEED 19 /* Set baudrate by using driver's baud rate timing calculation routines */ +#define GRCAN_IOC_SET_BTRS 20 /* Set baudrate by specifying the timing registers manually */ + +/* IOCTL Commands can be called whenever */ +#define GRCAN_IOC_SET_RXBLOCK 32 /* Enable/disable Blocking on reception (until at least one message has been received) */ +#define GRCAN_IOC_SET_TXBLOCK 33 /* Enable/disable Blocking on transmission (until at least one message has been transmitted) */ +#define GRCAN_IOC_SET_TXCOMPLETE 34 /* Enable/disable Blocking until all requested messages has been sent */ +#define GRCAN_IOC_SET_RXCOMPLETE 35 /* Enable/disable Blocking until all requested has been received */ +#define GRCAN_IOC_GET_STATS 36 /* Get Statistics */ +#define GRCAN_IOC_CLR_STATS 37 /* Clear Statistics */ +#define GRCAN_IOC_SET_AFILTER 38 /* Set Acceptance filters, provide pointer to "struct grcan_filter" or NULL to disable filtering (let all messages pass) */ +#define GRCAN_IOC_SET_SFILTER 40 /* Set Sync Messages RX/TX filters, NULL disables the IRQ completely */ +#define GRCAN_IOC_GET_STATUS 41 /* Get status register of GRCAN core */ + +struct grcan_device_info { + unsigned int base_address; + int irq; +}; + +/* Use hard coded addresses and IRQs to find hardware */ +int grcan_register_abs(struct grcan_device_info *devices, int dev_cnt); + +/* Use prescanned AMBA Plug&Play information to find all GRFIFO cores */ +int grcan_register(amba_confarea_type *abus); +#if 0 +void grcan_register(unsigned int baseaddr, unsigned int ram_base); +void grcan_interrupt_handler(rtems_vector_number v); +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/grcan_rasta.h b/c/src/lib/libbsp/sparc/shared/include/grcan_rasta.h new file mode 100644 index 0000000000..d0b5b66853 --- /dev/null +++ b/c/src/lib/libbsp/sparc/shared/include/grcan_rasta.h @@ -0,0 +1,24 @@ + +#ifndef __GRCAN_RASTA_H__ +#define __GRCAN_RASTA_H__ + +#include <grcan.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Registers the GRCAN for RASTA + * + * rambase is address of the first GRCAN core has it's TX buffer, followed by + * it's RX buffer + */ +int grcan_rasta_ram_register(amba_confarea_type *abus, int rambase); + +extern void (*grcan_rasta_int_reg)(void *handler, int irq, void *arg); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/grcan_spwrtc.h b/c/src/lib/libbsp/sparc/shared/include/grcan_spwrtc.h new file mode 100644 index 0000000000..b78ae4549c --- /dev/null +++ b/c/src/lib/libbsp/sparc/shared/include/grcan_spwrtc.h @@ -0,0 +1,9 @@ + +#ifndef __GRCAN_SPWRTC_H__ +#define __GRCAN_SPWRTC_H__ + +#include <grcan.h> + +/* Registers the GRCAN for SPW-RTC */ + +#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/grspw.h b/c/src/lib/libbsp/sparc/shared/include/grspw.h new file mode 100644 index 0000000000..f63da4af7c --- /dev/null +++ b/c/src/lib/libbsp/sparc/shared/include/grspw.h @@ -0,0 +1,135 @@ +/* + * Macros used for Spacewire bus + * + * COPYRIGHT (c) 2007. + * Gaisler Research + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#ifndef __GRSPW_H__ +#define __GRSPW_H__ + +#include <ambapp.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#define SPW_LINKERR_EVENT RTEMS_EVENT_0 + +typedef struct { + unsigned int rxsize; + unsigned int txdsize; + unsigned int txhsize; +} spw_ioctl_packetsize; + +typedef struct { + unsigned int hlen; + char *hdr; + unsigned int dlen; + char *data; + unsigned int sent; +} spw_ioctl_pkt_send; + +typedef struct { + unsigned int tx_link_err; + unsigned int rx_rmap_header_crc_err; + unsigned int rx_rmap_data_crc_err; + unsigned int rx_eep_err; + unsigned int rx_truncated; + unsigned int parity_err; + unsigned int escape_err; + unsigned int credit_err; + unsigned int write_sync_err; + unsigned int disconnect_err; + unsigned int early_ep; + unsigned int invalid_address; + unsigned int packets_sent; + unsigned int packets_received; +} spw_stats; + +typedef struct { + unsigned int nodeaddr; + unsigned int destkey; + unsigned int clkdiv; + unsigned int rxmaxlen; + unsigned int timer; + unsigned int disconnect; + unsigned int promiscuous; + unsigned int rmapen; + unsigned int rmapbufdis; + unsigned int linkdisabled; + unsigned int linkstart; + + unsigned int check_rmap_err; /* check incoming packets for rmap errors */ + unsigned int rm_prot_id; /* remove protocol id from incoming packets */ + unsigned int tx_blocking; /* use blocking tx */ + unsigned int tx_block_on_full; /* block when all tx_buffers are used */ + unsigned int rx_blocking; /* block when no data is available */ + unsigned int disable_err; /* disable link automatically when link error is detected */ + unsigned int link_err_irq; /* generate an interrupt when link error occurs */ + rtems_id event_id; /* task id that should receive link err irq event */ + + unsigned int is_rmap; + unsigned int is_rxunaligned; + unsigned int is_rmapcrc; +} spw_config; + +#define SPACEWIRE_IOCTRL_SET_NODEADDR 1 +#define SPACEWIRE_IOCTRL_SET_RXBLOCK 2 +#define SPACEWIRE_IOCTRL_SET_DESTKEY 4 +#define SPACEWIRE_IOCTRL_SET_CLKDIV 5 +#define SPACEWIRE_IOCTRL_SET_TIMER 6 +#define SPACEWIRE_IOCTRL_SET_DISCONNECT 7 +#define SPACEWIRE_IOCTRL_SET_PROMISCUOUS 8 +#define SPACEWIRE_IOCTRL_SET_RMAPEN 9 +#define SPACEWIRE_IOCTRL_SET_RMAPBUFDIS 10 +#define SPACEWIRE_IOCTRL_SET_CHECK_RMAP 11 +#define SPACEWIRE_IOCTRL_SET_RM_PROT_ID 12 +#define SPACEWIRE_IOCTRL_SET_TXBLOCK 14 +#define SPACEWIRE_IOCTRL_SET_DISABLE_ERR 15 +#define SPACEWIRE_IOCTRL_SET_LINK_ERR_IRQ 16 +#define SPACEWIRE_IOCTRL_SET_EVENT_ID 17 +#define SPACEWIRE_IOCTRL_SET_PACKETSIZE 20 +#define SPACEWIRE_IOCTRL_GET_LINK_STATUS 23 +#define SPACEWIRE_IOCTRL_GET_CONFIG 25 +#define SPACEWIRE_IOCTRL_GET_STATISTICS 26 +#define SPACEWIRE_IOCTRL_CLR_STATISTICS 27 +#define SPACEWIRE_IOCTRL_SEND 28 +#define SPACEWIRE_IOCTRL_LINKDISABLE 29 +#define SPACEWIRE_IOCTRL_LINKSTART 30 +#define SPACEWIRE_IOCTRL_SET_TXBLOCK_ON_FULL 31 +#define SPACEWIRE_IOCTRL_SET_COREFREQ 32 + +#define SPACEWIRE_IOCTRL_START 64 +#define SPACEWIRE_IOCTRL_STOP 65 + +int grspw_register(amba_confarea_type *bus); + + +#if 0 +struct grspw_buf; + +struct grspw_buf { + grspw_buf *next; /* next packet in chain */ + + /* Always used */ + unsigned int dlen; /* data length of '*data' */ + unsigned int max_dlen; /* allocated length of '*data' */ + void *data; /* pointer to beginning of cargo data */ + + /* Only used when transmitting */ + unsigned int hlen; /* length of header '*header' */ + unsigned int max_hlen; /* allocated length of '*header' */ + void *header; /* pointer to beginning of header data */ +}; +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __GRSPW_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/grspw_pci.h b/c/src/lib/libbsp/sparc/shared/include/grspw_pci.h new file mode 100644 index 0000000000..7266f1398d --- /dev/null +++ b/c/src/lib/libbsp/sparc/shared/include/grspw_pci.h @@ -0,0 +1,49 @@ + /* + * Macros used for GRSPW controller + * + * COPYRIGHT (c) 2006. + * Gaisler Research + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + */ + +#ifndef __GRSPW_PCI_H__ +#define __GRSPW_PCI_H__ + +#include <grspw.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Register GRSPW Driver + * bus = &amba_conf for LEON3 + * + * Memory setup: + * memarea = 128k aligned pointer to memory (if zero malloc will be used) (as the CPU sees it) + * hw_address = address that HW must use to access memarea. (used in the translation process) + */ + +int grspw_pci_register (amba_confarea_type * bus, + unsigned int memarea, unsigned int hw_address); + + +/* This function must be called on BRM interrupt. Called from the + * PCI interrupt handler. irq = AMBA IRQ MASK assigned to the BRM device, + * is found by reading pending register on IRQMP connected to BRM + * device. + * + * Return 0=not handled. nono-zero=handled + */ +unsigned int grspw_pci_interrupt_handler (int irq, void *arg); + +extern void (*grspw_pci_int_reg) (void *handler, int irq, void *arg); + +#ifdef __cplusplus +} +#endif + +#endif /* __GRSPW_PCI_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/grspw_rasta.h b/c/src/lib/libbsp/sparc/shared/include/grspw_rasta.h new file mode 100644 index 0000000000..2f6f2bd81e --- /dev/null +++ b/c/src/lib/libbsp/sparc/shared/include/grspw_rasta.h @@ -0,0 +1,49 @@ + /* + * Macros used for RASTA PCI GRSPW controller + * + * COPYRIGHT (c) 2006. + * Gaisler Research + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + */ + +#ifndef __GRSPW_RASTA_H__ +#define __GRSPW_RASTA_H__ + +#include <grspw.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Register GRSPW Driver + * bus = &amba_conf for LEON3 + * + * Memory setup: + * ram_base = 128k aligned pointer to memory (as the CPU sees it) + */ + +int grspw_rasta_register( + amba_confarea_type *bus, + unsigned int ram_base + ); + +/* This function must be called on GRSPW interrupt. Called from the + * PCI interrupt handler. irq = AMBA IRQ MASK assigned to the GRSPW device, + * is found by reading pending register on IRQMP connected to GRSPW + * device. + * + */ +void grspw_rasta_interrupt_handler(unsigned int status); + +/* callback to register interrupt handler */ +extern void (*grspw_rasta_int_reg)(void *handler, int irq, void *arg); + +#ifdef __cplusplus +} +#endif + +#endif /* __GRSPW_RASTA_PCI_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/occan.h b/c/src/lib/libbsp/sparc/shared/include/occan.h new file mode 100644 index 0000000000..227b56f8fb --- /dev/null +++ b/c/src/lib/libbsp/sparc/shared/include/occan.h @@ -0,0 +1,165 @@ +/* Gaisler wrapper to OpenCores CAN, driver interface + * + * COPYRIGHT (c) 2007. + * Gaisler Research. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * Author: Daniel Hellström, Gaisler Research AB, www.gaisler.com + */ + + +#ifndef __OCCAN_H__ +#define __OCCAN_H__ + +#include <ambapp.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* CAN MESSAGE */ +typedef struct { + char extended; /* 1= Extended Frame (29-bit id), 0= STD Frame (11-bit id) */ + char rtr; /* RTR - Remote Transmission Request */ + char sshot; /* single shot */ + unsigned char len; + unsigned char data[8]; + unsigned int id; +} CANMsg; + +typedef struct { + /* tx/rx stats */ + unsigned int rx_msgs; + unsigned int tx_msgs; + + /* Error Interrupt counters */ + unsigned int err_warn; + unsigned int err_dovr; + unsigned int err_errp; + unsigned int err_arb; + unsigned int err_bus; + + /**** BUS ERRORS (err_arb) ****/ + + /* ALC 4-0 */ + unsigned int err_arb_bitnum[32]; /* At what bit arbitration is lost */ + + /******************************/ + + /**** BUS ERRORS (err_bus) ****/ + + /* ECC 7-6 */ + unsigned int err_bus_bit; /* Bit error */ + unsigned int err_bus_form; /* Form Error */ + unsigned int err_bus_stuff; /* Stuff Error */ + unsigned int err_bus_other; /* Other Error */ + + /* ECC 5 */ + unsigned int err_bus_rx; /* Errors during Reception */ + unsigned int err_bus_tx; /* Errors during Transmission */ + + /* ECC 4:0 */ + unsigned int err_bus_segs[32]; /* Segment (Where in frame error occured) + * See OCCAN_SEG_* defines for indexes + */ + + /******************************/ + + + /* total number of interrupts */ + unsigned int ints; + + /* software monitoring hw errors */ + unsigned int tx_buf_error; + + /* Software fifo overrun */ + unsigned int rx_sw_dovr; + +} occan_stats; + +/* indexes into occan_stats.err_bus_segs[index] */ +#define OCCAN_SEG_ID28 0x02 /* ID field bit 28:21 */ +#define OCCAN_SEG_ID20 0x06 /* ID field bit 20:18 */ +#define OCCAN_SEG_ID17 0x07 /* ID field bit 17:13 */ +#define OCCAN_SEG_ID12 0x0f /* ID field bit 12:5 */ +#define OCCAN_SEG_ID4 0x0e /* ID field bit 4:0 */ + +#define OCCAN_SEG_START 0x03 /* Start of Frame */ +#define OCCAN_SEG_SRTR 0x04 /* Bit SRTR */ +#define OCCAN_SEG_IDE 0x05 /* Bit IDE */ +#define OCCAN_SEG_RTR 0x0c /* Bit RTR */ +#define OCCAN_SEG_RSV0 0x09 /* Reserved bit 0 */ +#define OCCAN_SEG_RSV1 0x0d /* Reserved bit 1 */ + +#define OCCAN_SEG_DLEN 0x0b /* Data Length code */ +#define OCCAN_SEG_DFIELD 0x0a /* Data Field */ + +#define OCCAN_SEG_CRC_SEQ 0x08 /* CRC Sequence */ +#define OCCAN_SEG_CRC_DELIM 0x18 /* CRC Delimiter */ + +#define OCCAN_SEG_ACK_SLOT 0x19 /* Acknowledge slot */ +#define OCCAN_SEG_ACK_DELIM 0x1b /* Acknowledge delimiter */ +#define OCCAN_SEG_EOF 0x1a /* End Of Frame */ +#define OCCAN_SEG_INTERMISSION 0x12 /* Intermission */ +#define OCCAN_SEG_ACT_ERR 0x11 /* Active error flag */ +#define OCCAN_SEG_PASS_ERR 0x16 /* Passive error flag */ +#define OCCAN_SEG_DOMINANT 0x13 /* Tolerate dominant bits */ +#define OCCAN_SEG_EDELIM 0x17 /* Error delimiter */ +#define OCCAN_SEG_OVERLOAD 0x1c /* overload flag */ + + +#define CANMSG_OPT_RTR 0x40 /* RTR Frame */ +#define CANMSG_OPT_EXTENDED 0x80 /* Exteneded frame */ +#define CANMSG_OPT_SSHOT 0x01 /* Single Shot, no retry */ + +#define OCCAN_IOC_START 1 +#define OCCAN_IOC_STOP 2 + +#define OCCAN_IOC_GET_CONF 3 +#define OCCAN_IOC_GET_STATS 4 +#define OCCAN_IOC_GET_STATUS 5 + +#define OCCAN_IOC_SET_SPEED 6 +#define OCCAN_IOC_SPEED_AUTO 7 +#define OCCAN_IOC_SET_LINK 8 +#define OCCAN_IOC_SET_FILTER 9 +#define OCCAN_IOC_SET_BLK_MODE 10 +#define OCCAN_IOC_SET_BUFLEN 11 +#define OCCAN_IOC_SET_BTRS 12 + + +struct occan_afilter { + unsigned char code[4]; + unsigned char mask[4]; + int single_mode; +}; + +#define OCCAN_STATUS_RESET 0x01 +#define OCCAN_STATUS_OVERRUN 0x02 +#define OCCAN_STATUS_WARN 0x04 +#define OCCAN_STATUS_ERR_PASSIVE 0x08 +#define OCCAN_STATUS_ERR_BUSOFF 0x10 +#define OCCAN_STATUS_QUEUE_ERROR 0x80 + +#define OCCAN_BLK_MODE_RX 0x1 +#define OCCAN_BLK_MODE_TX 0x2 + +int occan_register(amba_confarea_type *bus); + + +#define OCCAN_SPEED_500K 500000 +#define OCCAN_SPEED_250K 250000 +#define OCCAN_SPEED_125K 125000 +#define OCCAN_SPEED_75K 75000 +#define OCCAN_SPEED_50K 50000 +#define OCCAN_SPEED_25K 25000 +#define OCCAN_SPEED_10K 10000 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/occan_pci.h b/c/src/lib/libbsp/sparc/shared/include/occan_pci.h new file mode 100644 index 0000000000..f5da14c679 --- /dev/null +++ b/c/src/lib/libbsp/sparc/shared/include/occan_pci.h @@ -0,0 +1,42 @@ + /* + * OC_CAN controller via PCI - driver interface + * + * COPYRIGHT (c) 2007. + * Gaisler Research + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + */ + +#ifndef __OCCAN_PCI_H__ +#define __OCCAN_PCI_H__ + +#include <occan.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Register OC_CAN driver + * bus = pointer to AMBA bus description used to search for OC_CAN contrller(s). + */ + +int occan_pci_register(amba_confarea_type *bus); + +/* This function must be called on OC_CAN interrupt. Called from the + * PCI interrupt handler. irq = AMBA IRQ assigned to the OC_CAN device, + * is found by reading pending register on IRQMP connected to the OC_CAN + * device. + * + */ +void occanpci_interrupt_handler(int irq, void *arg); + +extern void (*occan_pci_int_reg)(void *handler, int irq, void *arg); + +#ifdef __cplusplus +} +#endif + +#endif /* __OCCAN_PCI_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/pci.h b/c/src/lib/libbsp/sparc/shared/include/pci.h new file mode 100644 index 0000000000..67ed88d6ee --- /dev/null +++ b/c/src/lib/libbsp/sparc/shared/include/pci.h @@ -0,0 +1,1179 @@ +/* + * + * PCI defines and function prototypes + * Copyright 1994, Drew Eckhardt + * Copyright 1997, 1998 Martin Mares <mj@atrey.karlin.mff.cuni.cz> + * + * For more information, please consult the following manuals (look at + * http://www.pcisig.com/ for how to get them): + * + * PCI BIOS Specification + * PCI Local Bus Specification + * PCI to PCI Bridge Specification + * PCI System Design Guide + * + * pci.h,v 1.2.4.2 2004/11/10 22:15:01 joel Exp + */ + +#ifndef RTEMS_PCI_H +#define RTEMS_PCI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Under PCI, each device has 256 bytes of configuration address space, + * of which the first 64 bytes are standardized as follows: + */ +#define PCI_VENDOR_ID 0x00 /* 16 bits */ +#define PCI_DEVICE_ID 0x02 /* 16 bits */ +#define PCI_COMMAND 0x04 /* 16 bits */ +#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ +#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ +#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ +#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ +#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ +#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ +#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ +#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ +#define PCI_COMMAND_SERR 0x100 /* Enable SERR */ +#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ + +#define PCI_STATUS 0x06 /* 16 bits */ +#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ +#define PCI_STATUS_UDF 0x40 /* Support User Definable Features */ + +#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ +#define PCI_STATUS_PARITY 0x100 /* Detected parity error */ +#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ +#define PCI_STATUS_DEVSEL_FAST 0x000 +#define PCI_STATUS_DEVSEL_MEDIUM 0x200 +#define PCI_STATUS_DEVSEL_SLOW 0x400 +#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ +#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ +#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ +#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ +#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ + +#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 + revision */ +#define PCI_REVISION_ID 0x08 /* Revision ID */ +#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ +#define PCI_CLASS_DEVICE 0x0a /* Device class */ + +#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ +#define PCI_LATENCY_TIMER 0x0d /* 8 bits */ +#define PCI_HEADER_TYPE 0x0e /* 8 bits */ +#define PCI_HEADER_TYPE_NORMAL 0 +#define PCI_HEADER_TYPE_BRIDGE 1 +#define PCI_HEADER_TYPE_CARDBUS 2 + +#define PCI_BIST 0x0f /* 8 bits */ +#define PCI_BIST_CODE_MASK 0x0f /* Return result */ +#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ +#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ + +/* + * Base addresses specify locations in memory or I/O space. + * Decoded size can be determined by writing a value of + * 0xffffffff to the register, and reading it back. Only + * 1 bits are decoded. + */ +#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ +#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ +#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ +#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ +#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ +#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ +#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ +#define PCI_BASE_ADDRESS_SPACE_IO 0x01 +#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 +#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 +#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ +#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M */ +#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ +#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ +#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) +#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) +/* bit 1 is reserved if address_space = 1 */ + +/* Header type 0 (normal devices) */ +#define PCI_CARDBUS_CIS 0x28 +#define PCI_SUBSYSTEM_VENDOR_ID 0x2c +#define PCI_SUBSYSTEM_ID 0x2e +#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ +#define PCI_ROM_ADDRESS_ENABLE 0x01 +#define PCI_ROM_ADDRESS_MASK (~0x7ffUL) + +/* 0x34-0x3b are reserved */ +#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ +#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ +#define PCI_MIN_GNT 0x3e /* 8 bits */ +#define PCI_MAX_LAT 0x3f /* 8 bits */ + +/* Header type 1 (PCI-to-PCI bridges) */ +#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ +#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ +#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ +#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ +#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ +#define PCI_IO_LIMIT 0x1d +#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ +#define PCI_IO_RANGE_TYPE_16 0x00 +#define PCI_IO_RANGE_TYPE_32 0x01 +#define PCI_IO_RANGE_MASK ~0x0f +#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ +#define PCI_MEMORY_BASE 0x20 /* Memory range behind */ +#define PCI_MEMORY_LIMIT 0x22 +#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f +#define PCI_MEMORY_RANGE_MASK ~0x0f +#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ +#define PCI_PREF_MEMORY_LIMIT 0x26 +#define PCI_PREF_RANGE_TYPE_MASK 0x0f +#define PCI_PREF_RANGE_TYPE_32 0x00 +#define PCI_PREF_RANGE_TYPE_64 0x01 +#define PCI_PREF_RANGE_MASK ~0x0f +#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ +#define PCI_PREF_LIMIT_UPPER32 0x2c +#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ +#define PCI_IO_LIMIT_UPPER16 0x32 +/* 0x34-0x3b is reserved */ +#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ +/* 0x3c-0x3d are same as for htype 0 */ +#define PCI_BRIDGE_CONTROL 0x3e +#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ +#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ +#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ +#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ +#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ +#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ +#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ + +/* Header type 2 (CardBus bridges) */ +/* 0x14-0x15 reserved */ +#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ +#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ +#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ +#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ +#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ +#define PCI_CB_MEMORY_BASE_0 0x1c +#define PCI_CB_MEMORY_LIMIT_0 0x20 +#define PCI_CB_MEMORY_BASE_1 0x24 +#define PCI_CB_MEMORY_LIMIT_1 0x28 +#define PCI_CB_IO_BASE_0 0x2c +#define PCI_CB_IO_BASE_0_HI 0x2e +#define PCI_CB_IO_LIMIT_0 0x30 +#define PCI_CB_IO_LIMIT_0_HI 0x32 +#define PCI_CB_IO_BASE_1 0x34 +#define PCI_CB_IO_BASE_1_HI 0x36 +#define PCI_CB_IO_LIMIT_1 0x38 +#define PCI_CB_IO_LIMIT_1_HI 0x3a +#define PCI_CB_IO_RANGE_MASK ~0x03 +/* 0x3c-0x3d are same as for htype 0 */ +#define PCI_CB_BRIDGE_CONTROL 0x3e +#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ +#define PCI_CB_BRIDGE_CTL_SERR 0x02 +#define PCI_CB_BRIDGE_CTL_ISA 0x04 +#define PCI_CB_BRIDGE_CTL_VGA 0x08 +#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 +#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ +#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ +#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ +#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 +#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 +#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 +#define PCI_CB_SUBSYSTEM_ID 0x42 +#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ +/* 0x48-0x7f reserved */ + +/* Device classes and subclasses */ + +#define PCI_CLASS_NOT_DEFINED 0x0000 +#define PCI_CLASS_NOT_DEFINED_VGA 0x0001 + +#define PCI_BASE_CLASS_STORAGE 0x01 +#define PCI_CLASS_STORAGE_SCSI 0x0100 +#define PCI_CLASS_STORAGE_IDE 0x0101 +#define PCI_CLASS_STORAGE_FLOPPY 0x0102 +#define PCI_CLASS_STORAGE_IPI 0x0103 +#define PCI_CLASS_STORAGE_RAID 0x0104 +#define PCI_CLASS_STORAGE_OTHER 0x0180 + +#define PCI_BASE_CLASS_NETWORK 0x02 +#define PCI_CLASS_NETWORK_ETHERNET 0x0200 +#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 +#define PCI_CLASS_NETWORK_FDDI 0x0202 +#define PCI_CLASS_NETWORK_ATM 0x0203 +#define PCI_CLASS_NETWORK_OTHER 0x0280 + +#define PCI_BASE_CLASS_DISPLAY 0x03 +#define PCI_CLASS_DISPLAY_VGA 0x0300 +#define PCI_CLASS_DISPLAY_XGA 0x0301 +#define PCI_CLASS_DISPLAY_OTHER 0x0380 + +#define PCI_BASE_CLASS_MULTIMEDIA 0x04 +#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 +#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 +#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 + +#define PCI_BASE_CLASS_MEMORY 0x05 +#define PCI_CLASS_MEMORY_RAM 0x0500 +#define PCI_CLASS_MEMORY_FLASH 0x0501 +#define PCI_CLASS_MEMORY_OTHER 0x0580 + +#define PCI_BASE_CLASS_BRIDGE 0x06 +#define PCI_CLASS_BRIDGE_HOST 0x0600 +#define PCI_CLASS_BRIDGE_ISA 0x0601 +#define PCI_CLASS_BRIDGE_EISA 0x0602 +#define PCI_CLASS_BRIDGE_MC 0x0603 +#define PCI_CLASS_BRIDGE_PCI 0x0604 +#define PCI_CLASS_BRIDGE_PCMCIA 0x0605 +#define PCI_CLASS_BRIDGE_NUBUS 0x0606 +#define PCI_CLASS_BRIDGE_CARDBUS 0x0607 +#define PCI_CLASS_BRIDGE_OTHER 0x0680 + +#define PCI_BASE_CLASS_COMMUNICATION 0x07 +#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 +#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 +#define PCI_CLASS_COMMUNICATION_OTHER 0x0780 + +#define PCI_BASE_CLASS_SYSTEM 0x08 +#define PCI_CLASS_SYSTEM_PIC 0x0800 +#define PCI_CLASS_SYSTEM_DMA 0x0801 +#define PCI_CLASS_SYSTEM_TIMER 0x0802 +#define PCI_CLASS_SYSTEM_RTC 0x0803 +#define PCI_CLASS_SYSTEM_OTHER 0x0880 + +#define PCI_BASE_CLASS_INPUT 0x09 +#define PCI_CLASS_INPUT_KEYBOARD 0x0900 +#define PCI_CLASS_INPUT_PEN 0x0901 +#define PCI_CLASS_INPUT_MOUSE 0x0902 +#define PCI_CLASS_INPUT_OTHER 0x0980 + +#define PCI_BASE_CLASS_DOCKING 0x0a +#define PCI_CLASS_DOCKING_GENERIC 0x0a00 +#define PCI_CLASS_DOCKING_OTHER 0x0a01 + +#define PCI_BASE_CLASS_PROCESSOR 0x0b +#define PCI_CLASS_PROCESSOR_386 0x0b00 +#define PCI_CLASS_PROCESSOR_486 0x0b01 +#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 +#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 +#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 +#define PCI_CLASS_PROCESSOR_CO 0x0b40 + +#define PCI_BASE_CLASS_SERIAL 0x0c +#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 +#define PCI_CLASS_SERIAL_ACCESS 0x0c01 +#define PCI_CLASS_SERIAL_SSA 0x0c02 +#define PCI_CLASS_SERIAL_USB 0x0c03 +#define PCI_CLASS_SERIAL_FIBER 0x0c04 + +#define PCI_CLASS_OTHERS 0xff + +/* + * Vendor and card ID's: sort these numerically according to vendor + * (and according to card ID within vendor). Send all updates to + * <linux-pcisupport@cck.uni-kl.de>. + */ +#define PCI_VENDOR_ID_COMPAQ 0x0e11 +#define PCI_DEVICE_ID_COMPAQ_1280 0x3033 +#define PCI_DEVICE_ID_COMPAQ_TRIFLEX 0x4000 +#define PCI_DEVICE_ID_COMPAQ_SMART2P 0xae10 +#define PCI_DEVICE_ID_COMPAQ_NETEL100 0xae32 +#define PCI_DEVICE_ID_COMPAQ_NETEL10 0xae34 +#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I 0xae35 +#define PCI_DEVICE_ID_COMPAQ_NETEL100D 0xae40 +#define PCI_DEVICE_ID_COMPAQ_NETEL100PI 0xae43 +#define PCI_DEVICE_ID_COMPAQ_NETEL100I 0xb011 +#define PCI_DEVICE_ID_COMPAQ_THUNDER 0xf130 +#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B 0xf150 + +#define PCI_VENDOR_ID_NCR 0x1000 +#define PCI_DEVICE_ID_NCR_53C810 0x0001 +#define PCI_DEVICE_ID_NCR_53C820 0x0002 +#define PCI_DEVICE_ID_NCR_53C825 0x0003 +#define PCI_DEVICE_ID_NCR_53C815 0x0004 +#define PCI_DEVICE_ID_NCR_53C860 0x0006 +#define PCI_DEVICE_ID_NCR_53C896 0x000b +#define PCI_DEVICE_ID_NCR_53C895 0x000c +#define PCI_DEVICE_ID_NCR_53C885 0x000d +#define PCI_DEVICE_ID_NCR_53C875 0x000f +#define PCI_DEVICE_ID_NCR_53C875J 0x008f + +#define PCI_VENDOR_ID_ATI 0x1002 +#define PCI_DEVICE_ID_ATI_68800 0x4158 +#define PCI_DEVICE_ID_ATI_215CT222 0x4354 +#define PCI_DEVICE_ID_ATI_210888CX 0x4358 +#define PCI_DEVICE_ID_ATI_215GB 0x4742 +#define PCI_DEVICE_ID_ATI_215GD 0x4744 +#define PCI_DEVICE_ID_ATI_215GI 0x4749 +#define PCI_DEVICE_ID_ATI_215GP 0x4750 +#define PCI_DEVICE_ID_ATI_215GQ 0x4751 +#define PCI_DEVICE_ID_ATI_215GT 0x4754 +#define PCI_DEVICE_ID_ATI_215GTB 0x4755 +#define PCI_DEVICE_ID_ATI_210888GX 0x4758 +#define PCI_DEVICE_ID_ATI_215LG 0x4c47 +#define PCI_DEVICE_ID_ATI_264LT 0x4c54 +#define PCI_DEVICE_ID_ATI_264VT 0x5654 + +#define PCI_VENDOR_ID_VLSI 0x1004 +#define PCI_DEVICE_ID_VLSI_82C592 0x0005 +#define PCI_DEVICE_ID_VLSI_82C593 0x0006 +#define PCI_DEVICE_ID_VLSI_82C594 0x0007 +#define PCI_DEVICE_ID_VLSI_82C597 0x0009 +#define PCI_DEVICE_ID_VLSI_82C541 0x000c +#define PCI_DEVICE_ID_VLSI_82C543 0x000d +#define PCI_DEVICE_ID_VLSI_82C532 0x0101 +#define PCI_DEVICE_ID_VLSI_82C534 0x0102 +#define PCI_DEVICE_ID_VLSI_82C535 0x0104 +#define PCI_DEVICE_ID_VLSI_82C147 0x0105 +#define PCI_DEVICE_ID_VLSI_VAS96011 0x0702 + +#define PCI_VENDOR_ID_ADL 0x1005 +#define PCI_DEVICE_ID_ADL_2301 0x2301 + +#define PCI_VENDOR_ID_NS 0x100b +#define PCI_DEVICE_ID_NS_87415 0x0002 +#define PCI_DEVICE_ID_NS_87410 0xd001 + +#define PCI_VENDOR_ID_TSENG 0x100c +#define PCI_DEVICE_ID_TSENG_W32P_2 0x3202 +#define PCI_DEVICE_ID_TSENG_W32P_b 0x3205 +#define PCI_DEVICE_ID_TSENG_W32P_c 0x3206 +#define PCI_DEVICE_ID_TSENG_W32P_d 0x3207 +#define PCI_DEVICE_ID_TSENG_ET6000 0x3208 + +#define PCI_VENDOR_ID_WEITEK 0x100e +#define PCI_DEVICE_ID_WEITEK_P9000 0x9001 +#define PCI_DEVICE_ID_WEITEK_P9100 0x9100 + +#define PCI_VENDOR_ID_DEC 0x1011 +#define PCI_DEVICE_ID_DEC_BRD 0x0001 +#define PCI_DEVICE_ID_DEC_TULIP 0x0002 +#define PCI_DEVICE_ID_DEC_TGA 0x0004 +#define PCI_DEVICE_ID_DEC_TULIP_FAST 0x0009 +#define PCI_DEVICE_ID_DEC_TGA2 0x000D +#define PCI_DEVICE_ID_DEC_FDDI 0x000F +#define PCI_DEVICE_ID_DEC_TULIP_PLUS 0x0014 +#define PCI_DEVICE_ID_DEC_21142 0x0019 +#define PCI_DEVICE_ID_DEC_21052 0x0021 +#define PCI_DEVICE_ID_DEC_21150 0x0022 +#define PCI_DEVICE_ID_DEC_21152 0x0024 + +#define PCI_VENDOR_ID_CIRRUS 0x1013 +#define PCI_DEVICE_ID_CIRRUS_7548 0x0038 +#define PCI_DEVICE_ID_CIRRUS_5430 0x00a0 +#define PCI_DEVICE_ID_CIRRUS_5434_4 0x00a4 +#define PCI_DEVICE_ID_CIRRUS_5434_8 0x00a8 +#define PCI_DEVICE_ID_CIRRUS_5436 0x00ac +#define PCI_DEVICE_ID_CIRRUS_5446 0x00b8 +#define PCI_DEVICE_ID_CIRRUS_5480 0x00bc +#define PCI_DEVICE_ID_CIRRUS_5464 0x00d4 +#define PCI_DEVICE_ID_CIRRUS_5465 0x00d6 +#define PCI_DEVICE_ID_CIRRUS_6729 0x1100 +#define PCI_DEVICE_ID_CIRRUS_6832 0x1110 +#define PCI_DEVICE_ID_CIRRUS_7542 0x1200 +#define PCI_DEVICE_ID_CIRRUS_7543 0x1202 +#define PCI_DEVICE_ID_CIRRUS_7541 0x1204 + +#define PCI_VENDOR_ID_IBM 0x1014 +#define PCI_DEVICE_ID_IBM_FIRE_CORAL 0x000a +#define PCI_DEVICE_ID_IBM_TR 0x0018 +#define PCI_DEVICE_ID_IBM_82G2675 0x001d +#define PCI_DEVICE_ID_IBM_MCA 0x0020 +#define PCI_DEVICE_ID_IBM_82351 0x0022 +#define PCI_DEVICE_ID_IBM_SERVERAID 0x002e +#define PCI_DEVICE_ID_IBM_TR_WAKE 0x003e +#define PCI_DEVICE_ID_IBM_MPIC 0x0046 +#define PCI_DEVICE_ID_IBM_3780IDSP 0x007d +#define PCI_DEVICE_ID_IBM_MPIC_2 0xffff + +#define PCI_VENDOR_ID_WD 0x101c +#define PCI_DEVICE_ID_WD_7197 0x3296 + +#define PCI_VENDOR_ID_AMD 0x1022 +#define PCI_DEVICE_ID_AMD_LANCE 0x2000 +#define PCI_DEVICE_ID_AMD_SCSI 0x2020 + +#define PCI_VENDOR_ID_TRIDENT 0x1023 +#define PCI_DEVICE_ID_TRIDENT_9397 0x9397 +#define PCI_DEVICE_ID_TRIDENT_9420 0x9420 +#define PCI_DEVICE_ID_TRIDENT_9440 0x9440 +#define PCI_DEVICE_ID_TRIDENT_9660 0x9660 +#define PCI_DEVICE_ID_TRIDENT_9750 0x9750 + +#define PCI_VENDOR_ID_AI 0x1025 +#define PCI_DEVICE_ID_AI_M1435 0x1435 + +#define PCI_VENDOR_ID_MATROX 0x102B +#define PCI_DEVICE_ID_MATROX_MGA_2 0x0518 +#define PCI_DEVICE_ID_MATROX_MIL 0x0519 +#define PCI_DEVICE_ID_MATROX_MYS 0x051A +#define PCI_DEVICE_ID_MATROX_MIL_2 0x051b +#define PCI_DEVICE_ID_MATROX_MIL_2_AGP 0x051f +#define PCI_DEVICE_ID_MATROX_MGA_IMP 0x0d10 + +#define PCI_VENDOR_ID_CT 0x102c +#define PCI_DEVICE_ID_CT_65545 0x00d8 +#define PCI_DEVICE_ID_CT_65548 0x00dc +#define PCI_DEVICE_ID_CT_65550 0x00e0 +#define PCI_DEVICE_ID_CT_65554 0x00e4 +#define PCI_DEVICE_ID_CT_65555 0x00e5 + +#define PCI_VENDOR_ID_MIRO 0x1031 +#define PCI_DEVICE_ID_MIRO_36050 0x5601 + +#define PCI_VENDOR_ID_NEC 0x1033 +#define PCI_DEVICE_ID_NEC_PCX2 0x0046 + +#define PCI_VENDOR_ID_FD 0x1036 +#define PCI_DEVICE_ID_FD_36C70 0x0000 + +#define PCI_VENDOR_ID_SI 0x1039 +#define PCI_DEVICE_ID_SI_5591_AGP 0x0001 +#define PCI_DEVICE_ID_SI_6202 0x0002 +#define PCI_DEVICE_ID_SI_503 0x0008 +#define PCI_DEVICE_ID_SI_ACPI 0x0009 +#define PCI_DEVICE_ID_SI_5597_VGA 0x0200 +#define PCI_DEVICE_ID_SI_6205 0x0205 +#define PCI_DEVICE_ID_SI_501 0x0406 +#define PCI_DEVICE_ID_SI_496 0x0496 +#define PCI_DEVICE_ID_SI_601 0x0601 +#define PCI_DEVICE_ID_SI_5107 0x5107 +#define PCI_DEVICE_ID_SI_5511 0x5511 +#define PCI_DEVICE_ID_SI_5513 0x5513 +#define PCI_DEVICE_ID_SI_5571 0x5571 +#define PCI_DEVICE_ID_SI_5591 0x5591 +#define PCI_DEVICE_ID_SI_5597 0x5597 +#define PCI_DEVICE_ID_SI_7001 0x7001 + +#define PCI_VENDOR_ID_HP 0x103c +#define PCI_DEVICE_ID_HP_J2585A 0x1030 +#define PCI_DEVICE_ID_HP_J2585B 0x1031 + +#define PCI_VENDOR_ID_PCTECH 0x1042 +#define PCI_DEVICE_ID_PCTECH_RZ1000 0x1000 +#define PCI_DEVICE_ID_PCTECH_RZ1001 0x1001 +#define PCI_DEVICE_ID_PCTECH_SAMURAI_0 0x3000 +#define PCI_DEVICE_ID_PCTECH_SAMURAI_1 0x3010 +#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020 + +#define PCI_VENDOR_ID_DPT 0x1044 +#define PCI_DEVICE_ID_DPT 0xa400 + +#define PCI_VENDOR_ID_OPTI 0x1045 +#define PCI_DEVICE_ID_OPTI_92C178 0xc178 +#define PCI_DEVICE_ID_OPTI_82C557 0xc557 +#define PCI_DEVICE_ID_OPTI_82C558 0xc558 +#define PCI_DEVICE_ID_OPTI_82C621 0xc621 +#define PCI_DEVICE_ID_OPTI_82C700 0xc700 +#define PCI_DEVICE_ID_OPTI_82C701 0xc701 +#define PCI_DEVICE_ID_OPTI_82C814 0xc814 +#define PCI_DEVICE_ID_OPTI_82C822 0xc822 +#define PCI_DEVICE_ID_OPTI_82C825 0xd568 + +#define PCI_VENDOR_ID_SGS 0x104a +#define PCI_DEVICE_ID_SGS_2000 0x0008 +#define PCI_DEVICE_ID_SGS_1764 0x0009 + +#define PCI_VENDOR_ID_BUSLOGIC 0x104B +#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140 +#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER 0x1040 +#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT 0x8130 + +#define PCI_VENDOR_ID_TI 0x104c +#define PCI_DEVICE_ID_TI_TVP4010 0x3d04 +#define PCI_DEVICE_ID_TI_TVP4020 0x3d07 +#define PCI_DEVICE_ID_TI_PCI1130 0xac12 +#define PCI_DEVICE_ID_TI_PCI1031 0xac13 +#define PCI_DEVICE_ID_TI_PCI1131 0xac15 +#define PCI_DEVICE_ID_TI_PCI1250 0xac16 +#define PCI_DEVICE_ID_TI_PCI1220 0xac17 + +#define PCI_VENDOR_ID_OAK 0x104e +#define PCI_DEVICE_ID_OAK_OTI107 0x0107 + +/* Winbond have two vendor IDs! See 0x10ad as well */ +#define PCI_VENDOR_ID_WINBOND2 0x1050 +#define PCI_DEVICE_ID_WINBOND2_89C940 0x0940 + +#define PCI_VENDOR_ID_MOTOROLA 0x1057 +#define PCI_DEVICE_ID_MOTOROLA_MPC105 0x0001 +#define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002 +#define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801 + +#define PCI_VENDOR_ID_PROMISE 0x105a +#define PCI_DEVICE_ID_PROMISE_20246 0x4d33 +#define PCI_DEVICE_ID_PROMISE_5300 0x5300 + +#define PCI_VENDOR_ID_N9 0x105d +#define PCI_DEVICE_ID_N9_I128 0x2309 +#define PCI_DEVICE_ID_N9_I128_2 0x2339 +#define PCI_DEVICE_ID_N9_I128_T2R 0x493d + +#define PCI_VENDOR_ID_UMC 0x1060 +#define PCI_DEVICE_ID_UMC_UM8673F 0x0101 +#define PCI_DEVICE_ID_UMC_UM8891A 0x0891 +#define PCI_DEVICE_ID_UMC_UM8886BF 0x673a +#define PCI_DEVICE_ID_UMC_UM8886A 0x886a +#define PCI_DEVICE_ID_UMC_UM8881F 0x8881 +#define PCI_DEVICE_ID_UMC_UM8886F 0x8886 +#define PCI_DEVICE_ID_UMC_UM9017F 0x9017 +#define PCI_DEVICE_ID_UMC_UM8886N 0xe886 +#define PCI_DEVICE_ID_UMC_UM8891N 0xe891 + +#define PCI_VENDOR_ID_X 0x1061 +#define PCI_DEVICE_ID_X_AGX016 0x0001 + +#define PCI_VENDOR_ID_PICOP 0x1066 +#define PCI_DEVICE_ID_PICOP_PT86C52X 0x0001 +#define PCI_DEVICE_ID_PICOP_PT80C524 0x8002 + +#define PCI_VENDOR_ID_APPLE 0x106b +#define PCI_DEVICE_ID_APPLE_BANDIT 0x0001 +#define PCI_DEVICE_ID_APPLE_GC 0x0002 +#define PCI_DEVICE_ID_APPLE_HYDRA 0x000e + +#define PCI_VENDOR_ID_NEXGEN 0x1074 +#define PCI_DEVICE_ID_NEXGEN_82C501 0x4e78 + +#define PCI_VENDOR_ID_QLOGIC 0x1077 +#define PCI_DEVICE_ID_QLOGIC_ISP1020 0x1020 +#define PCI_DEVICE_ID_QLOGIC_ISP1022 0x1022 + +#define PCI_VENDOR_ID_CYRIX 0x1078 +#define PCI_DEVICE_ID_CYRIX_5510 0x0000 +#define PCI_DEVICE_ID_CYRIX_PCI_MASTER 0x0001 +#define PCI_DEVICE_ID_CYRIX_5520 0x0002 +#define PCI_DEVICE_ID_CYRIX_5530_LEGACY 0x0100 +#define PCI_DEVICE_ID_CYRIX_5530_SMI 0x0101 +#define PCI_DEVICE_ID_CYRIX_5530_IDE 0x0102 +#define PCI_DEVICE_ID_CYRIX_5530_AUDIO 0x0103 +#define PCI_DEVICE_ID_CYRIX_5530_VIDEO 0x0104 + +#define PCI_VENDOR_ID_LEADTEK 0x107d +#define PCI_DEVICE_ID_LEADTEK_805 0x0000 + +#define PCI_VENDOR_ID_CONTAQ 0x1080 +#define PCI_DEVICE_ID_CONTAQ_82C599 0x0600 +#define PCI_DEVICE_ID_CONTAQ_82C693 0xc693 + +#define PCI_VENDOR_ID_FOREX 0x1083 + +#define PCI_VENDOR_ID_OLICOM 0x108d +#define PCI_DEVICE_ID_OLICOM_OC3136 0x0001 +#define PCI_DEVICE_ID_OLICOM_OC2315 0x0011 +#define PCI_DEVICE_ID_OLICOM_OC2325 0x0012 +#define PCI_DEVICE_ID_OLICOM_OC2183 0x0013 +#define PCI_DEVICE_ID_OLICOM_OC2326 0x0014 +#define PCI_DEVICE_ID_OLICOM_OC6151 0x0021 + +#define PCI_VENDOR_ID_SUN 0x108e +#define PCI_DEVICE_ID_SUN_EBUS 0x1000 +#define PCI_DEVICE_ID_SUN_HAPPYMEAL 0x1001 +#define PCI_DEVICE_ID_SUN_SIMBA 0x5000 +#define PCI_DEVICE_ID_SUN_PBM 0x8000 +#define PCI_DEVICE_ID_SUN_SABRE 0xa000 + +#define PCI_VENDOR_ID_CMD 0x1095 +#define PCI_DEVICE_ID_CMD_640 0x0640 +#define PCI_DEVICE_ID_CMD_643 0x0643 +#define PCI_DEVICE_ID_CMD_646 0x0646 +#define PCI_DEVICE_ID_CMD_647 0x0647 +#define PCI_DEVICE_ID_CMD_670 0x0670 + +#define PCI_VENDOR_ID_VISION 0x1098 +#define PCI_DEVICE_ID_VISION_QD8500 0x0001 +#define PCI_DEVICE_ID_VISION_QD8580 0x0002 + +#define PCI_VENDOR_ID_BROOKTREE 0x109e +#define PCI_DEVICE_ID_BROOKTREE_848 0x0350 +#define PCI_DEVICE_ID_BROOKTREE_849A 0x0351 +#define PCI_DEVICE_ID_BROOKTREE_8474 0x8474 + +#define PCI_VENDOR_ID_SIERRA 0x10a8 +#define PCI_DEVICE_ID_SIERRA_STB 0x0000 + +#define PCI_VENDOR_ID_ACC 0x10aa +#define PCI_DEVICE_ID_ACC_2056 0x0000 + +#define PCI_VENDOR_ID_WINBOND 0x10ad +#define PCI_DEVICE_ID_WINBOND_83769 0x0001 +#define PCI_DEVICE_ID_WINBOND_82C105 0x0105 +#define PCI_DEVICE_ID_WINBOND_83C553 0x0565 + +#define PCI_VENDOR_ID_DATABOOK 0x10b3 +#define PCI_DEVICE_ID_DATABOOK_87144 0xb106 + +#define PCI_VENDOR_ID_PLX 0x10b5 +#define PCI_DEVICE_ID_PLX_9050 0x9050 +#define PCI_DEVICE_ID_PLX_9060 0x9060 +#define PCI_DEVICE_ID_PLX_9060ES 0x906E +#define PCI_DEVICE_ID_PLX_9060SD 0x906D +#define PCI_DEVICE_ID_PLX_9080 0x9080 + +#define PCI_VENDOR_ID_MADGE 0x10b6 +#define PCI_DEVICE_ID_MADGE_MK2 0x0002 +#define PCI_DEVICE_ID_MADGE_C155S 0x1001 + +#define PCI_VENDOR_ID_3COM 0x10b7 +#define PCI_DEVICE_ID_3COM_3C339 0x3390 +#define PCI_DEVICE_ID_3COM_3C590 0x5900 +#define PCI_DEVICE_ID_3COM_3C595TX 0x5950 +#define PCI_DEVICE_ID_3COM_3C595T4 0x5951 +#define PCI_DEVICE_ID_3COM_3C595MII 0x5952 +#define PCI_DEVICE_ID_3COM_3C900TPO 0x9000 +#define PCI_DEVICE_ID_3COM_3C900COMBO 0x9001 +#define PCI_DEVICE_ID_3COM_3C905TX 0x9050 +#define PCI_DEVICE_ID_3COM_3C905T4 0x9051 +#define PCI_DEVICE_ID_3COM_3C905B_TX 0x9055 + +#define PCI_VENDOR_ID_SMC 0x10b8 +#define PCI_DEVICE_ID_SMC_EPIC100 0x0005 + +#define PCI_VENDOR_ID_AL 0x10b9 +#define PCI_DEVICE_ID_AL_M1445 0x1445 +#define PCI_DEVICE_ID_AL_M1449 0x1449 +#define PCI_DEVICE_ID_AL_M1451 0x1451 +#define PCI_DEVICE_ID_AL_M1461 0x1461 +#define PCI_DEVICE_ID_AL_M1489 0x1489 +#define PCI_DEVICE_ID_AL_M1511 0x1511 +#define PCI_DEVICE_ID_AL_M1513 0x1513 +#define PCI_DEVICE_ID_AL_M1521 0x1521 +#define PCI_DEVICE_ID_AL_M1523 0x1523 +#define PCI_DEVICE_ID_AL_M1531 0x1531 +#define PCI_DEVICE_ID_AL_M1533 0x1533 +#define PCI_DEVICE_ID_AL_M3307 0x3307 +#define PCI_DEVICE_ID_AL_M4803 0x5215 +#define PCI_DEVICE_ID_AL_M5219 0x5219 +#define PCI_DEVICE_ID_AL_M5229 0x5229 +#define PCI_DEVICE_ID_AL_M5237 0x5237 +#define PCI_DEVICE_ID_AL_M7101 0x7101 + +#define PCI_VENDOR_ID_MITSUBISHI 0x10ba + +#define PCI_VENDOR_ID_SURECOM 0x10bd +#define PCI_DEVICE_ID_SURECOM_NE34 0x0e34 + +#define PCI_VENDOR_ID_NEOMAGIC 0x10c8 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2070 0x0001 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128V 0x0002 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZV 0x0003 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2160 0x0004 + +#define PCI_VENDOR_ID_ASP 0x10cd +#define PCI_DEVICE_ID_ASP_ABP940 0x1200 +#define PCI_DEVICE_ID_ASP_ABP940U 0x1300 +#define PCI_DEVICE_ID_ASP_ABP940UW 0x2300 + +#define PCI_VENDOR_ID_MACRONIX 0x10d9 +#define PCI_DEVICE_ID_MACRONIX_MX98713 0x0512 +#define PCI_DEVICE_ID_MACRONIX_MX987x5 0x0531 + +#define PCI_VENDOR_ID_CERN 0x10dc +#define PCI_DEVICE_ID_CERN_SPSB_PMC 0x0001 +#define PCI_DEVICE_ID_CERN_SPSB_PCI 0x0002 +#define PCI_DEVICE_ID_CERN_HIPPI_DST 0x0021 +#define PCI_DEVICE_ID_CERN_HIPPI_SRC 0x0022 + +#define PCI_VENDOR_ID_NVIDIA 0x10de + +#define PCI_VENDOR_ID_IMS 0x10e0 +#define PCI_DEVICE_ID_IMS_8849 0x8849 + +#define PCI_VENDOR_ID_TEKRAM2 0x10e1 +#define PCI_DEVICE_ID_TEKRAM2_690c 0x690c + +#define PCI_VENDOR_ID_TUNDRA 0x10e3 +#define PCI_DEVICE_ID_TUNDRA_CA91C042 0x0000 + +#define PCI_VENDOR_ID_AMCC 0x10e8 +#define PCI_DEVICE_ID_AMCC_MYRINET 0x8043 +#define PCI_DEVICE_ID_AMCC_PARASTATION 0x8062 +#define PCI_DEVICE_ID_AMCC_S5933 0x807d +#define PCI_DEVICE_ID_AMCC_S5933_HEPC3 0x809c + +#define PCI_VENDOR_ID_INTERG 0x10ea +#define PCI_DEVICE_ID_INTERG_1680 0x1680 +#define PCI_DEVICE_ID_INTERG_1682 0x1682 + +#define PCI_VENDOR_ID_REALTEK 0x10ec +#define PCI_DEVICE_ID_REALTEK_8029 0x8029 +#define PCI_DEVICE_ID_REALTEK_8129 0x8129 +#define PCI_DEVICE_ID_REALTEK_8139 0x8139 + +#define PCI_VENDOR_ID_TRUEVISION 0x10fa +#define PCI_DEVICE_ID_TRUEVISION_T1000 0x000c + +#define PCI_VENDOR_ID_INIT 0x1101 +#define PCI_DEVICE_ID_INIT_320P 0x9100 +#define PCI_DEVICE_ID_INIT_360P 0x9500 + +#define PCI_VENDOR_ID_TTI 0x1103 +#define PCI_DEVICE_ID_TTI_HPT343 0x0003 + +#define PCI_VENDOR_ID_VIA 0x1106 +#define PCI_DEVICE_ID_VIA_82C505 0x0505 +#define PCI_DEVICE_ID_VIA_82C561 0x0561 +#define PCI_DEVICE_ID_VIA_82C586_1 0x0571 +#define PCI_DEVICE_ID_VIA_82C576 0x0576 +#define PCI_DEVICE_ID_VIA_82C585 0x0585 +#define PCI_DEVICE_ID_VIA_82C586_0 0x0586 +#define PCI_DEVICE_ID_VIA_82C595 0x0595 +#define PCI_DEVICE_ID_VIA_82C597_0 0x0597 +#define PCI_DEVICE_ID_VIA_82C926 0x0926 +#define PCI_DEVICE_ID_VIA_82C416 0x1571 +#define PCI_DEVICE_ID_VIA_82C595_97 0x1595 +#define PCI_DEVICE_ID_VIA_82C586_2 0x3038 +#define PCI_DEVICE_ID_VIA_82C586_3 0x3040 +#define PCI_DEVICE_ID_VIA_86C100A 0x6100 +#define PCI_DEVICE_ID_VIA_82C597_1 0x8597 + +#define PCI_VENDOR_ID_VORTEX 0x1119 +#define PCI_DEVICE_ID_VORTEX_GDT60x0 0x0000 +#define PCI_DEVICE_ID_VORTEX_GDT6000B 0x0001 +#define PCI_DEVICE_ID_VORTEX_GDT6x10 0x0002 +#define PCI_DEVICE_ID_VORTEX_GDT6x20 0x0003 +#define PCI_DEVICE_ID_VORTEX_GDT6530 0x0004 +#define PCI_DEVICE_ID_VORTEX_GDT6550 0x0005 +#define PCI_DEVICE_ID_VORTEX_GDT6x17 0x0006 +#define PCI_DEVICE_ID_VORTEX_GDT6x27 0x0007 +#define PCI_DEVICE_ID_VORTEX_GDT6537 0x0008 +#define PCI_DEVICE_ID_VORTEX_GDT6557 0x0009 +#define PCI_DEVICE_ID_VORTEX_GDT6x15 0x000a +#define PCI_DEVICE_ID_VORTEX_GDT6x25 0x000b +#define PCI_DEVICE_ID_VORTEX_GDT6535 0x000c +#define PCI_DEVICE_ID_VORTEX_GDT6555 0x000d +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x0100 +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x0101 +#define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x0102 +#define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x0103 +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x0104 +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x0105 +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP1 0x0110 +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP1 0x0111 +#define PCI_DEVICE_ID_VORTEX_GDT6537RP1 0x0112 +#define PCI_DEVICE_ID_VORTEX_GDT6557RP1 0x0113 +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP1 0x0114 +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP1 0x0115 +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP2 0x0120 +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP2 0x0121 +#define PCI_DEVICE_ID_VORTEX_GDT6537RP2 0x0122 +#define PCI_DEVICE_ID_VORTEX_GDT6557RP2 0x0123 +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP2 0x0124 +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP2 0x0125 + +#define PCI_VENDOR_ID_EF 0x111a +#define PCI_DEVICE_ID_EF_ATM_FPGA 0x0000 +#define PCI_DEVICE_ID_EF_ATM_ASIC 0x0002 + +#define PCI_VENDOR_ID_FORE 0x1127 +#define PCI_DEVICE_ID_FORE_PCA200PC 0x0210 +#define PCI_DEVICE_ID_FORE_PCA200E 0x0300 + +#define PCI_VENDOR_ID_IMAGINGTECH 0x112f +#define PCI_DEVICE_ID_IMAGINGTECH_ICPCI 0x0000 + +#define PCI_VENDOR_ID_PHILIPS 0x1131 +#define PCI_DEVICE_ID_PHILIPS_SAA7145 0x7145 +#define PCI_DEVICE_ID_PHILIPS_SAA7146 0x7146 + +#define PCI_VENDOR_ID_CYCLONE 0x113c +#define PCI_DEVICE_ID_CYCLONE_SDK 0x0001 + +#define PCI_VENDOR_ID_ALLIANCE 0x1142 +#define PCI_DEVICE_ID_ALLIANCE_PROMOTIO 0x3210 +#define PCI_DEVICE_ID_ALLIANCE_PROVIDEO 0x6422 +#define PCI_DEVICE_ID_ALLIANCE_AT24 0x6424 +#define PCI_DEVICE_ID_ALLIANCE_AT3D 0x643d + +#define PCI_VENDOR_ID_SK 0x1148 +#define PCI_DEVICE_ID_SK_FP 0x4000 +#define PCI_DEVICE_ID_SK_TR 0x4200 +#define PCI_DEVICE_ID_SK_GE 0x4300 + +#define PCI_VENDOR_ID_VMIC 0x114a +#define PCI_DEVICE_ID_VMIC_VME 0x7587 + +#define PCI_VENDOR_ID_DIGI 0x114f +#define PCI_DEVICE_ID_DIGI_EPC 0x0002 +#define PCI_DEVICE_ID_DIGI_RIGHTSWITCH 0x0003 +#define PCI_DEVICE_ID_DIGI_XEM 0x0004 +#define PCI_DEVICE_ID_DIGI_XR 0x0005 +#define PCI_DEVICE_ID_DIGI_CX 0x0006 +#define PCI_DEVICE_ID_DIGI_XRJ 0x0009 +#define PCI_DEVICE_ID_DIGI_EPCJ 0x000a +#define PCI_DEVICE_ID_DIGI_XR_920 0x0027 + +#define PCI_VENDOR_ID_MUTECH 0x1159 +#define PCI_DEVICE_ID_MUTECH_MV1000 0x0001 + +#define PCI_VENDOR_ID_RENDITION 0x1163 +#define PCI_DEVICE_ID_RENDITION_VERITE 0x0001 +#define PCI_DEVICE_ID_RENDITION_VERITE2100 0x2000 + +#define PCI_VENDOR_ID_TOSHIBA 0x1179 +#define PCI_DEVICE_ID_TOSHIBA_601 0x0601 +#define PCI_DEVICE_ID_TOSHIBA_TOPIC95 0x060a +#define PCI_DEVICE_ID_TOSHIBA_TOPIC97 0x060f + +#define PCI_VENDOR_ID_RICOH 0x1180 +#define PCI_DEVICE_ID_RICOH_RL5C465 0x0465 +#define PCI_DEVICE_ID_RICOH_RL5C466 0x0466 +#define PCI_DEVICE_ID_RICOH_RL5C475 0x0475 +#define PCI_DEVICE_ID_RICOH_RL5C478 0x0478 + +#define PCI_VENDOR_ID_ARTOP 0x1191 +#define PCI_DEVICE_ID_ARTOP_ATP8400 0x0004 +#define PCI_DEVICE_ID_ARTOP_ATP850UF 0x0005 + +#define PCI_VENDOR_ID_ZEITNET 0x1193 +#define PCI_DEVICE_ID_ZEITNET_1221 0x0001 +#define PCI_DEVICE_ID_ZEITNET_1225 0x0002 + +#define PCI_VENDOR_ID_OMEGA 0x119b +#define PCI_DEVICE_ID_OMEGA_82C092G 0x1221 + +#define PCI_VENDOR_ID_LITEON 0x11ad +#define PCI_DEVICE_ID_LITEON_LNE100TX 0x0002 + +#define PCI_VENDOR_ID_NP 0x11bc +#define PCI_DEVICE_ID_NP_PCI_FDDI 0x0001 + +#define PCI_VENDOR_ID_ATT 0x11c1 +#define PCI_DEVICE_ID_ATT_L56XMF 0x0440 + +#define PCI_VENDOR_ID_SPECIALIX 0x11cb +#define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000 +#define PCI_DEVICE_ID_SPECIALIX_XIO 0x4000 +#define PCI_DEVICE_ID_SPECIALIX_RIO 0x8000 + +#define PCI_VENDOR_ID_AURAVISION 0x11d1 +#define PCI_DEVICE_ID_AURAVISION_VXP524 0x01f7 + +#define PCI_VENDOR_ID_IKON 0x11d5 +#define PCI_DEVICE_ID_IKON_10115 0x0115 +#define PCI_DEVICE_ID_IKON_10117 0x0117 + +#define PCI_VENDOR_ID_ZORAN 0x11de +#define PCI_DEVICE_ID_ZORAN_36057 0x6057 +#define PCI_DEVICE_ID_ZORAN_36120 0x6120 + +#define PCI_VENDOR_ID_KINETIC 0x11f4 +#define PCI_DEVICE_ID_KINETIC_2915 0x2915 + +#define PCI_VENDOR_ID_COMPEX 0x11f6 +#define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112 +#define PCI_DEVICE_ID_COMPEX_RL2000 0x1401 + +#define PCI_VENDOR_ID_RP 0x11fe +#define PCI_DEVICE_ID_RP32INTF 0x0001 +#define PCI_DEVICE_ID_RP8INTF 0x0002 +#define PCI_DEVICE_ID_RP16INTF 0x0003 +#define PCI_DEVICE_ID_RP4QUAD 0x0004 +#define PCI_DEVICE_ID_RP8OCTA 0x0005 +#define PCI_DEVICE_ID_RP8J 0x0006 +#define PCI_DEVICE_ID_RPP4 0x000A +#define PCI_DEVICE_ID_RPP8 0x000B +#define PCI_DEVICE_ID_RP8M 0x000C + +#define PCI_VENDOR_ID_CYCLADES 0x120e +#define PCI_DEVICE_ID_CYCLOM_Y_Lo 0x0100 +#define PCI_DEVICE_ID_CYCLOM_Y_Hi 0x0101 +#define PCI_DEVICE_ID_CYCLOM_Z_Lo 0x0200 +#define PCI_DEVICE_ID_CYCLOM_Z_Hi 0x0201 + +#define PCI_VENDOR_ID_ESSENTIAL 0x120f +#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER 0x0001 + +#define PCI_VENDOR_ID_O2 0x1217 +#define PCI_DEVICE_ID_O2_6729 0x6729 +#define PCI_DEVICE_ID_O2_6730 0x673a +#define PCI_DEVICE_ID_O2_6832 0x6832 +#define PCI_DEVICE_ID_O2_6836 0x6836 + +#define PCI_VENDOR_ID_3DFX 0x121a +#define PCI_DEVICE_ID_3DFX_VOODOO 0x0001 +#define PCI_DEVICE_ID_3DFX_VOODOO2 0x0002 + +#define PCI_VENDOR_ID_SIGMADES 0x1236 +#define PCI_DEVICE_ID_SIGMADES_6425 0x6401 + +#define PCI_VENDOR_ID_CCUBE 0x123f + +#define PCI_VENDOR_ID_DIPIX 0x1246 + +#define PCI_VENDOR_ID_STALLION 0x124d +#define PCI_DEVICE_ID_STALLION_ECHPCI832 0x0000 +#define PCI_DEVICE_ID_STALLION_ECHPCI864 0x0002 +#define PCI_DEVICE_ID_STALLION_EIOPCI 0x0003 + +#define PCI_VENDOR_ID_OPTIBASE 0x1255 +#define PCI_DEVICE_ID_OPTIBASE_FORGE 0x1110 +#define PCI_DEVICE_ID_OPTIBASE_FUSION 0x1210 +#define PCI_DEVICE_ID_OPTIBASE_VPLEX 0x2110 +#define PCI_DEVICE_ID_OPTIBASE_VPLEXCC 0x2120 +#define PCI_DEVICE_ID_OPTIBASE_VQUEST 0x2130 + +#define PCI_VENDOR_ID_SATSAGEM 0x1267 +#define PCI_DEVICE_ID_SATSAGEM_PCR2101 0x5352 +#define PCI_DEVICE_ID_SATSAGEM_TELSATTURBO 0x5a4b + +#define PCI_VENDOR_ID_HUGHES 0x1273 +#define PCI_DEVICE_ID_HUGHES_DIRECPC 0x0002 + +#define PCI_VENDOR_ID_ENSONIQ 0x1274 +#define PCI_DEVICE_ID_ENSONIQ_AUDIOPCI 0x5000 + +#define PCI_VENDOR_ID_ALTEON 0x12ae +#define PCI_DEVICE_ID_ALTEON_ACENIC 0x0001 + +#define PCI_VENDOR_ID_PICTUREL 0x12c5 +#define PCI_DEVICE_ID_PICTUREL_PCIVST 0x0081 + +#define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2 +#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018 + +#define PCI_VENDOR_ID_CBOARDS 0x1307 +#define PCI_DEVICE_ID_CBOARDS_DAS1602_16 0x0001 + +#define PCI_VENDOR_ID_SYMPHONY 0x1c1c +#define PCI_DEVICE_ID_SYMPHONY_101 0x0001 + +#define PCI_VENDOR_ID_TEKRAM 0x1de1 +#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 + +#define PCI_VENDOR_ID_3DLABS 0x3d3d +#define PCI_DEVICE_ID_3DLABS_300SX 0x0001 +#define PCI_DEVICE_ID_3DLABS_500TX 0x0002 +#define PCI_DEVICE_ID_3DLABS_DELTA 0x0003 +#define PCI_DEVICE_ID_3DLABS_PERMEDIA 0x0004 +#define PCI_DEVICE_ID_3DLABS_MX 0x0006 + +#define PCI_VENDOR_ID_AVANCE 0x4005 +#define PCI_DEVICE_ID_AVANCE_ALG2064 0x2064 +#define PCI_DEVICE_ID_AVANCE_2302 0x2302 + +#define PCI_VENDOR_ID_NETVIN 0x4a14 +#define PCI_DEVICE_ID_NETVIN_NV5000SC 0x5000 + +#define PCI_VENDOR_ID_S3 0x5333 +#define PCI_DEVICE_ID_S3_PLATO_PXS 0x0551 +#define PCI_DEVICE_ID_S3_ViRGE 0x5631 +#define PCI_DEVICE_ID_S3_TRIO 0x8811 +#define PCI_DEVICE_ID_S3_AURORA64VP 0x8812 +#define PCI_DEVICE_ID_S3_TRIO64UVP 0x8814 +#define PCI_DEVICE_ID_S3_ViRGE_VX 0x883d +#define PCI_DEVICE_ID_S3_868 0x8880 +#define PCI_DEVICE_ID_S3_928 0x88b0 +#define PCI_DEVICE_ID_S3_864_1 0x88c0 +#define PCI_DEVICE_ID_S3_864_2 0x88c1 +#define PCI_DEVICE_ID_S3_964_1 0x88d0 +#define PCI_DEVICE_ID_S3_964_2 0x88d1 +#define PCI_DEVICE_ID_S3_968 0x88f0 +#define PCI_DEVICE_ID_S3_TRIO64V2 0x8901 +#define PCI_DEVICE_ID_S3_PLATO_PXG 0x8902 +#define PCI_DEVICE_ID_S3_ViRGE_DXGX 0x8a01 +#define PCI_DEVICE_ID_S3_ViRGE_GX2 0x8a10 +#define PCI_DEVICE_ID_S3_ViRGE_MX 0x8c01 +#define PCI_DEVICE_ID_S3_ViRGE_MXP 0x8c02 +#define PCI_DEVICE_ID_S3_ViRGE_MXPMV 0x8c03 +#define PCI_DEVICE_ID_S3_SONICVIBES 0xca00 + +#define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_DEVICE_ID_INTEL_82375 0x0482 +#define PCI_DEVICE_ID_INTEL_82424 0x0483 +#define PCI_DEVICE_ID_INTEL_82378 0x0484 +#define PCI_DEVICE_ID_INTEL_82430 0x0486 +#define PCI_DEVICE_ID_INTEL_82434 0x04a3 +#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221 +#define PCI_DEVICE_ID_INTEL_82092AA_1 0x1222 +#define PCI_DEVICE_ID_INTEL_7116 0x1223 +#define PCI_DEVICE_ID_INTEL_82596 0x1226 +#define PCI_DEVICE_ID_INTEL_82865 0x1227 +#define PCI_DEVICE_ID_INTEL_82557 0x1229 +#define PCI_DEVICE_ID_INTEL_82437 0x122d +#define PCI_DEVICE_ID_INTEL_82371FB_0 0x122e +#define PCI_DEVICE_ID_INTEL_82371FB_1 0x1230 +#define PCI_DEVICE_ID_INTEL_82371MX 0x1234 +#define PCI_DEVICE_ID_INTEL_82437MX 0x1235 +#define PCI_DEVICE_ID_INTEL_82441 0x1237 +#define PCI_DEVICE_ID_INTEL_82380FB 0x124b +#define PCI_DEVICE_ID_INTEL_82439 0x1250 +#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 +#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 +#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020 +#define PCI_DEVICE_ID_INTEL_82437VX 0x7030 +#define PCI_DEVICE_ID_INTEL_82439TX 0x7100 +#define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110 +#define PCI_DEVICE_ID_INTEL_82371AB 0x7111 +#define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112 +#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113 +#define PCI_DEVICE_ID_INTEL_82443LX_0 0x7180 +#define PCI_DEVICE_ID_INTEL_82443LX_1 0x7181 +#define PCI_DEVICE_ID_INTEL_82443BX_0 0x7190 +#define PCI_DEVICE_ID_INTEL_82443BX_1 0x7191 +#define PCI_DEVICE_ID_INTEL_82443BX_2 0x7192 +#define PCI_DEVICE_ID_INTEL_P6 0x84c4 +#define PCI_DEVICE_ID_INTEL_82450GX 0x84c5 + +#define PCI_VENDOR_ID_KTI 0x8e2e +#define PCI_DEVICE_ID_KTI_ET32P2 0x3000 + +#define PCI_VENDOR_ID_ADAPTEC 0x9004 +#define PCI_DEVICE_ID_ADAPTEC_7810 0x1078 +#define PCI_DEVICE_ID_ADAPTEC_7850 0x5078 +#define PCI_DEVICE_ID_ADAPTEC_7855 0x5578 +#define PCI_DEVICE_ID_ADAPTEC_5800 0x5800 +#define PCI_DEVICE_ID_ADAPTEC_1480A 0x6075 +#define PCI_DEVICE_ID_ADAPTEC_7860 0x6078 +#define PCI_DEVICE_ID_ADAPTEC_7861 0x6178 +#define PCI_DEVICE_ID_ADAPTEC_7870 0x7078 +#define PCI_DEVICE_ID_ADAPTEC_7871 0x7178 +#define PCI_DEVICE_ID_ADAPTEC_7872 0x7278 +#define PCI_DEVICE_ID_ADAPTEC_7873 0x7378 +#define PCI_DEVICE_ID_ADAPTEC_7874 0x7478 +#define PCI_DEVICE_ID_ADAPTEC_7895 0x7895 +#define PCI_DEVICE_ID_ADAPTEC_7880 0x8078 +#define PCI_DEVICE_ID_ADAPTEC_7881 0x8178 +#define PCI_DEVICE_ID_ADAPTEC_7882 0x8278 +#define PCI_DEVICE_ID_ADAPTEC_7883 0x8378 +#define PCI_DEVICE_ID_ADAPTEC_7884 0x8478 +#define PCI_DEVICE_ID_ADAPTEC_1030 0x8b78 + +#define PCI_VENDOR_ID_ADAPTEC2 0x9005 +#define PCI_DEVICE_ID_ADAPTEC2_2940U2 0x0010 +#define PCI_DEVICE_ID_ADAPTEC2_7890 0x001f +#define PCI_DEVICE_ID_ADAPTEC2_3940U2 0x0050 +#define PCI_DEVICE_ID_ADAPTEC2_7896 0x005f + +#define PCI_VENDOR_ID_ATRONICS 0x907f +#define PCI_DEVICE_ID_ATRONICS_2015 0x2015 + +#define PCI_VENDOR_ID_HOLTEK 0x9412 +#define PCI_DEVICE_ID_HOLTEK_6565 0x6565 + +#define PCI_VENDOR_ID_TIGERJET 0xe159 +#define PCI_DEVICE_ID_TIGERJET_300 0x0001 + +#define PCI_VENDOR_ID_ARK 0xedd8 +#define PCI_DEVICE_ID_ARK_STING 0xa091 +#define PCI_DEVICE_ID_ARK_STINGARK 0xa099 +#define PCI_DEVICE_ID_ARK_2000MT 0xa0a1 + +/* + * The PCI interface treats multi-function devices as independent + * devices. The slot/function address of each device is encoded + * in a single byte as follows: + * + * 7:3 = slot + * 2:0 = function + */ +#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) +#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) +#define PCI_FUNC(devfn) ((devfn) & 0x07) + +/* + * Error values that may be returned by the PCI bios. + */ +#define PCIBIOS_SUCCESSFUL 0x00 +#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 +#define PCIBIOS_BAD_VENDOR_ID 0x83 +#define PCIBIOS_DEVICE_NOT_FOUND 0x86 +#define PCIBIOS_BAD_REGISTER_NUMBER 0x87 +#define PCIBIOS_SET_FAILED 0x88 +#define PCIBIOS_BUFFER_TOO_SMALL 0x89 + +/* T. Straumann, 7/31/2001: increased to 32 - PMC slots are not + * scanned on mvme2306 otherwise + */ +#define PCI_MAX_DEVICES 32 +#define PCI_MAX_FUNCTIONS 8 + +typedef struct { + int (*read_config_byte)(unsigned char, unsigned char, unsigned char, + unsigned char, unsigned char *); + int (*read_config_word)(unsigned char, unsigned char, unsigned char, + unsigned char, unsigned short *); + int (*read_config_dword)(unsigned char, unsigned char, unsigned char, + unsigned char, unsigned int *); + int (*write_config_byte)(unsigned char, unsigned char, unsigned char, + unsigned char, unsigned char); + int (*write_config_word)(unsigned char, unsigned char, unsigned char, + unsigned char, unsigned short); + int (*write_config_dword)(unsigned char, unsigned char, unsigned char, + unsigned char, unsigned int); +}pci_config_access_functions; + +typedef struct { + volatile unsigned char* pci_config_addr; + volatile unsigned char* pci_config_data; + const pci_config_access_functions* pci_functions; +} pci_config; + +extern pci_config BSP_pci_configuration; + +extern inline int +pci_read_config_byte(unsigned char bus, unsigned char slot, unsigned char function, + unsigned char where, unsigned char * val) { + return BSP_pci_configuration.pci_functions->read_config_byte(bus, slot, function, where, val); +} + +extern inline int +pci_read_config_word(unsigned char bus, unsigned char slot, unsigned char function, + unsigned char where, unsigned short * val) { + return BSP_pci_configuration.pci_functions->read_config_word(bus, slot, function, where, val); +} + +extern inline int +pci_read_config_dword(unsigned char bus, unsigned char slot, unsigned char function, + unsigned char where, unsigned int * val) { + return BSP_pci_configuration.pci_functions->read_config_dword(bus, slot, function, where, val); +} + +extern inline int +pci_write_config_byte(unsigned char bus, unsigned char slot, unsigned char function, + unsigned char where, unsigned char val) { + return BSP_pci_configuration.pci_functions->write_config_byte(bus, slot, function, where, val); +} + +extern inline int +pci_write_config_word(unsigned char bus, unsigned char slot, unsigned char function, + unsigned char where, unsigned short val) { + return BSP_pci_configuration.pci_functions->write_config_word(bus, slot, function, where, val); +} + +extern inline int +pci_write_config_dword(unsigned char bus, unsigned char slot, unsigned char function, + unsigned char where, unsigned int val) { + return BSP_pci_configuration.pci_functions->write_config_dword(bus, slot, function, where, val); +} + +/* + * Return the number of PCI busses in the system + */ +extern unsigned char BusCountPCI(); +extern int init_pci(); + +extern int dma_to_pci(unsigned int addr, unsigned int paddr, unsigned int len); +extern int dma_from_pci(unsigned int addr, unsigned int paddr, unsigned int len); +extern void pci_mem_enable(unsigned char bus, unsigned char slot, unsigned char function); +extern void pci_master_enable(unsigned char bus, unsigned char slot, unsigned char function); + +/* scan for a specific device */ +/* find a particular PCI device + * (currently, only bus0 is scanned for device/fun0) + * + * RETURNS: zero on success, bus/dev/fun in *pbus / *pdev / *pfun + */ +int +BSP_pciFindDevice(unsigned short vendorid, unsigned short deviceid, + int instance, int *pbus, int *pdev, int *pfun); + +#ifdef __cplusplus +} +#endif + +#endif /* RTEMS_PCI_H */ |