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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2010-11-15 10:55:02 +0000 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2010-11-15 10:55:02 +0000 |
| commit | ddd5640ff64895e7d937bf69d8d8f8ffc507aad9 (patch) | |
| tree | e05873b61dbe6b17b253c92f3d74dfbacb34aa9a /c | |
| parent | 2010-11-12 Sebastian Huber <sebastian.huber@embedded-brains.de> (diff) | |
| download | rtems-ddd5640ff64895e7d937bf69d8d8f8ffc507aad9.tar.bz2 | |
2010-11-12 Sebastian Huber <sebastian.huber@embedded-brains.de>
* make/custom/dp2.cfg, startup/linkcmds.dp2: New files.
* Makefile.am, preinstall.am: Reflect change above. Install
<bsp/utility.h>. Install BestComm header files.
* configure.ac: Changed BSP options.
* include/mpc5200.h: Added module structures and register defines.
* bestcomm/bestcomm_api.c, bestcomm/bestcomm_api.h,
bestcomm/bestcomm_glue.c, bestcomm/bestcomm_glue.h,
bestcomm/bestcomm_priv.h, bestcomm/load_task.c,
bestcomm/tasksetup_bdtable.c, bestcomm/task_api/bestcomm_cntrl.h: C++
compatibility. Use special heap to manage the SRAM region. Use
interrupt extension API. Fixed warnings.
* console/console.c: Fixed console registration. Fixed warnings.
Added GPS module registration.
* ide/pcmcia_ide.h: Fixed clock value macros.
* ide/pcmcia_ide.c: Update for BestComm API changes.
DP2 specific initialization. Removed zero loop in PIO receive
function.
* include/bsp.h: Added DP2 variant. Removed obsolete defines.
* include/mscan-base.h, mscan/mscan-base.c: Use volatile qualifier.
Format.
* irq/irq.c: Fixed peripheral interrupt handling.
* network_5200/network.c: Update for BestComm API changes.
* start/start.S: U-Boot fixes.
* startup/cpuinit.c: Enable write-back cache strategy. Added special
memory regions.
* startup/linkcmds.brs5l: Fixed memory size.
Diffstat (limited to 'c')
25 files changed, 805 insertions, 650 deletions
diff --git a/c/src/lib/libbsp/powerpc/gen5200/ChangeLog b/c/src/lib/libbsp/powerpc/gen5200/ChangeLog index bd12afb670..7c270bd2c2 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/ChangeLog +++ b/c/src/lib/libbsp/powerpc/gen5200/ChangeLog @@ -1,3 +1,32 @@ +2010-11-12 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * make/custom/dp2.cfg, startup/linkcmds.dp2: New files. + * Makefile.am, preinstall.am: Reflect change above. Install + <bsp/utility.h>. Install BestComm header files. + * configure.ac: Changed BSP options. + * include/mpc5200.h: Added module structures and register defines. + * bestcomm/bestcomm_api.c, bestcomm/bestcomm_api.h, + bestcomm/bestcomm_glue.c, bestcomm/bestcomm_glue.h, + bestcomm/bestcomm_priv.h, bestcomm/load_task.c, + bestcomm/tasksetup_bdtable.c, bestcomm/task_api/bestcomm_cntrl.h: C++ + compatibility. Use special heap to manage the SRAM region. Use + interrupt extension API. Fixed warnings. + * console/console.c: Fixed console registration. Fixed warnings. + Added GPS module registration. + * ide/pcmcia_ide.h: Fixed clock value macros. + * ide/pcmcia_ide.c: Update for BestComm API changes. + DP2 specific initialization. Removed zero loop in PIO receive + function. + * include/bsp.h: Added DP2 variant. Removed obsolete defines. + * include/mscan-base.h, mscan/mscan-base.c: Use volatile qualifier. + Format. + * irq/irq.c: Fixed peripheral interrupt handling. + * network_5200/network.c: Update for BestComm API changes. + * start/start.S: U-Boot fixes. + * startup/cpuinit.c: Enable write-back cache strategy. Added special + memory regions. + * startup/linkcmds.brs5l: Fixed memory size. + 2010-06-30 Peter Dufault <dufault@hda.com> PR 1588/cpukit diff --git a/c/src/lib/libbsp/powerpc/gen5200/Makefile.am b/c/src/lib/libbsp/powerpc/gen5200/Makefile.am index 4dad531ecc..d285abfc24 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/Makefile.am +++ b/c/src/lib/libbsp/powerpc/gen5200/Makefile.am @@ -7,6 +7,10 @@ ACLOCAL_AMFLAGS = -I ../../../../aclocal include $(top_srcdir)/../../../../automake/compile.am include_bspdir = $(includedir)/bsp +include_bestcommdir = $(include_bspdir)/bestcomm +include_bestcomm_includedir = $(include_bestcommdir)/include +include_bestcomm_include_mgt5200dir = $(include_bestcomm_includedir)/mgt5200 +include_bestcomm_task_apidir = $(include_bestcommdir)/task_api dist_project_lib_DATA = bsp_specs @@ -37,6 +41,7 @@ EXTRA_DIST = startup/linkcmds.brs5l EXTRA_DIST += startup/linkcmds.icecube EXTRA_DIST += startup/linkcmds.pm520_cr825 EXTRA_DIST += startup/linkcmds.pm520_ze30 +EXTRA_DIST += startup/linkcmds.dp2 noinst_LIBRARIES += libbsp.a libbsp_a_SOURCES = @@ -59,6 +64,20 @@ libbsp_a_SOURCES += bestcomm/include/ppctypes.h \ bestcomm/task_api/bestcomm_api_mem.h bestcomm/task_api/bestcomm_cntrl.h \ bestcomm/task_api/tasksetup_bdtable.h \ bestcomm/task_api/tasksetup_general.h +include_bestcomm_HEADERS = bestcomm/bestcomm_priv.h \ + bestcomm/dma_image.h \ + bestcomm/dma_image.capi.h \ + bestcomm/bestcomm_api.h \ + bestcomm/bestcomm_glue.h +include_bestcomm_include_HEADERS = bestcomm/include/ppctypes.h \ + bestcomm/include/mgt5200/sdma.h \ + bestcomm/include/mgt5200/mgt5200.h +include_bestcomm_include_mgt5200_HEADERS = bestcomm/include/mgt5200/mgt5200.h \ + bestcomm/include/mgt5200/sdma.h +include_bestcomm_task_api_HEADERS = bestcomm/task_api/tasksetup_general.h \ + bestcomm/task_api/tasksetup_bdtable.h \ + bestcomm/task_api/bestcomm_cntrl.h \ + bestcomm/task_api/bestcomm_api_mem.h # clock # clock @@ -72,6 +91,7 @@ libbsp_a_SOURCES += ide/idecfg.c ide/pcmcia_ide.c ide/pcmcia_ide.h include_bsp_HEADERS = ../../shared/include/irq-generic.h \ ../../shared/include/irq-info.h \ + ../../shared/include/utility.h \ include/irq.h \ include/i2cdrv.h \ include/i2c.h \ diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_api.c b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_api.c index 42488cb87b..171882b803 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_api.c +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_api.c @@ -70,11 +70,6 @@ uint8 *MBarGlobal; sint64 MBarPhysOffsetGlobal; /* - * Offset to free space in SRAM after task code and buffer descriptors. - */ -uint32 SramOffsetGlobal = 0; - -/* * This flag is false when TaskStart() has not yet been called on a * task newly configured by TaskSetup() or TaskStop() has been called. * Otherwise it is true. It is possible that a task disabled itself @@ -185,48 +180,6 @@ int TasksAttachImage(sdma_regs *sdma) } /*! - * \brief This function returns the value of the internal variable - * used to keep track of used space in SRAM. - * - * \returns The number of bytes from the beginning of SRAM to the end - * used space in the SRAM. - * - * This function will return the offset to free space in the SRAM - * not used by the CAPI. \b Note: The returned value is based - * on what is in TasksSetSramOffset. This function can - * not determine what SRAM space was used by another process. There must - * be some way external to the CAPI to keep track of SRAM space. This - * function only returns the internal variable used to keep track of buffer - * descriptors. - */ -uint32 TasksGetSramOffset(void) -{ - return SramOffsetGlobal; -} - -/*! - * \brief This function stores the number of bytes from the - * beginning of SRAM to the end of the used space. - * - * \param sram_offset Number of bytes until the beginning of - * free space in the SRAM. - * - * This function sets the free space offset in SRAM. It must be called - * before setup in multi-task environments. It is the application's - * job to determine where the free space in SRAM is. This sets the - * base offset for the buffer descriptor variables during setup, so to - * deallocate buffers that have already been set this function should be - * called with a new offset. - */ -void TasksSetSramOffset(uint32 sram_offset) -{ - /* - * Set the SramOffsetGlobal variable to be used by TaskSetup_BDTable - */ - SramOffsetGlobal = sram_offset; -} - -/*! * \brief Start an initialized task running. * \param taskId Task handle passed back from a successful TaskSetup() * \param autoStartEnable Boolean for whether autostart bit is enabled. diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_api.h b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_api.h index f4dfa68fde..f1fa22d1d5 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_api.h +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_api.h @@ -36,12 +36,18 @@ * linked. */ +#include <rtems.h> + #include "include/ppctypes.h" #include "include/mgt5200/sdma.h" #include "task_api/tasksetup_bdtable.h" #include "task_api/bestcomm_cntrl.h" #include "task_api/bestcomm_api_mem.h" +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + /*! * \brief TaskSetup() debugging * @@ -271,8 +277,10 @@ typedef struct { * TaskId TaskSetup( TaskName_t TaskName, * TaskSetupParamSet_t *TaskSetupParams ); */ -#define TaskSetup(TaskName, TaskSetupParams) \ +#define TaskSetupHelper(TaskName, TaskSetupParams) \ TaskSetup_ ## TaskName (TaskName ## _api, TaskSetupParams) +#define TaskSetup(TaskName, TaskSetupParams) \ + TaskSetupHelper(TaskName, TaskSetupParams) const char *TaskVersion(void); @@ -283,9 +291,6 @@ int TasksInitAPI_VM(uint8 *MBarRef, uint8 *MBarPhys); void TasksLoadImage(sdma_regs *sdma); int TasksAttachImage(sdma_regs *sdma); -uint32 TasksGetSramOffset(void); -void TasksSetSramOffset(uint32 sram_offset); - int TaskStart(TaskId taskId, uint32 autoStartEnable, TaskId autoStartTask, uint32 intrEnable); int TaskStop(TaskId taskId); @@ -327,7 +332,7 @@ static inline int TaskStatus(TaskId taskId) */ static inline TaskBD_t *TaskGetBD(TaskId taskId, BDIdx bd) { - TaskBD_t *bdTab; + void *bdTab; bdTab = TaskBDIdxTable[taskId].BDTablePtr; if (TaskBDIdxTable[taskId].numPtr == 1) { @@ -350,7 +355,7 @@ static inline TaskBD_t *TaskGetBD(TaskId taskId, BDIdx bd) */ static inline TaskBD_t *TaskGetBDRing(TaskId taskId) { - return TaskBDIdxTable[taskId].BDTablePtr; + return (TaskBD_t *) TaskBDIdxTable[taskId].BDTablePtr; } /*! @@ -448,4 +453,8 @@ static inline uint16 TaskBDInUse(TaskId taskId) return TaskBDIdxTable[taskId].currBDInUse; } +#ifdef __cplusplus +} +#endif /* __cplusplus */ + #endif /* __BESTCOMM_API_H */ diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_glue.c b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_glue.c index d1c01336b1..db2223ea87 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_glue.c +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_glue.c @@ -16,8 +16,8 @@ +-----------------------------------------------------------------+ | this file contains glue functions to the Freescale BestComm API | \*===============================================================*/ +#include <assert.h> #include <rtems.h> -#include <rtems/error.h> #include <bsp.h> #include <bsp/irq.h> #include "../include/mpc5200.h" @@ -28,6 +28,10 @@ #include "bestcomm_glue.h" #include "include/mgt5200/sdma.h" +extern const uint32 taskTableBytes; + +static Heap_Control bestcomm_heap; + /*=========================================================================*\ | Function: | \*-------------------------------------------------------------------------*/ @@ -46,15 +50,12 @@ void bestcomm_glue_irq_enable | none | \*=========================================================================*/ { - rtems_interrupt_level level; if (0 != ((1UL<<bestcomm_taskno) & SDMA_INT_BIT_IMPL)) { - rtems_interrupt_disable(level); /* * valid task number * enable interrupt in bestcomm mask */ - SDMA_INT_ENABLE(&mpc5200.IntMask,bestcomm_taskno); - rtems_interrupt_enable(level); + SDMA_INT_ENABLE(&mpc5200.sdma.IntMask,bestcomm_taskno); } } @@ -76,24 +77,21 @@ void bestcomm_glue_irq_disable | none | \*=========================================================================*/ { - rtems_interrupt_level level; if (0 != ((1UL<<bestcomm_taskno) & SDMA_INT_BIT_IMPL)) { - rtems_interrupt_disable(level); /* * valid task number * disable interrupt in bestcomm mask */ - SDMA_INT_DISABLE(&mpc5200.IntMask,bestcomm_taskno); - rtems_interrupt_enable(level); + SDMA_INT_DISABLE(&mpc5200.sdma.IntMask,bestcomm_taskno); } } typedef struct { - void (*the_handler)(rtems_irq_hdl_param); - rtems_irq_hdl_param the_param; + rtems_interrupt_handler handler; + void *arg; } bestcomm_glue_irq_handlers_t; -bestcomm_glue_irq_handlers_t bestcomm_glue_irq_handlers[32]; +static bestcomm_glue_irq_handlers_t bestcomm_glue_irq_handlers[32]; /*=========================================================================*\ | Function: | @@ -107,8 +105,8 @@ void bestcomm_glue_irq_install | Input Parameters: | \*-------------------------------------------------------------------------*/ int bestcomm_taskno, /* task number for handler */ - void (*the_handler)(rtems_irq_hdl_param), /* function to call */ - rtems_irq_hdl_param the_param + rtems_interrupt_handler handler, /* function to call */ + void *arg ) /*-------------------------------------------------------------------------*\ | Return Value: | @@ -120,8 +118,8 @@ void bestcomm_glue_irq_install * valid task number * install handler */ - bestcomm_glue_irq_handlers[bestcomm_taskno].the_handler = the_handler; - bestcomm_glue_irq_handlers[bestcomm_taskno].the_param = the_param; + bestcomm_glue_irq_handlers[bestcomm_taskno].handler = handler; + bestcomm_glue_irq_handlers[bestcomm_taskno].arg = arg; } } @@ -136,8 +134,7 @@ void bestcomm_glue_irq_dispatcher +---------------------------------------------------------------------------+ | Input Parameters: | \*-------------------------------------------------------------------------*/ - rtems_irq_hdl_param handle /* irq specific handle (not used) */ - + void *arg /* irq specific handle (not used) */ ) /*-------------------------------------------------------------------------*\ | Return Value: | @@ -147,23 +144,23 @@ void bestcomm_glue_irq_dispatcher uint32_t pending; int curr_taskno; - pending = mpc5200.IntPend & ~mpc5200.IntMask; + pending = mpc5200.sdma.IntPend & ~mpc5200.sdma.IntMask; curr_taskno = 0; while (pending != 0) { if ((pending & (1UL<<curr_taskno)) != 0) { - if (bestcomm_glue_irq_handlers[curr_taskno].the_handler == NULL) { + if (bestcomm_glue_irq_handlers[curr_taskno].handler != NULL) { /* - * This should never happen. we have a pending IRQ but no handler - * let's clear this pending bit + * call proper handler */ - SDMA_CLEAR_IEVENT(&mpc5200.IntPend,curr_taskno); + bestcomm_glue_irq_handlers[curr_taskno].handler + (bestcomm_glue_irq_handlers[curr_taskno].arg); } else { /* - * call proper handler + * This should never happen. we have a pending IRQ but no handler + * let's clear this pending bit */ - bestcomm_glue_irq_handlers[curr_taskno].the_handler - (bestcomm_glue_irq_handlers[curr_taskno].the_param); + SDMA_CLEAR_IEVENT(&mpc5200.sdma.IntPend,curr_taskno); } /* * clear this bit in our pending copy @@ -175,32 +172,6 @@ void bestcomm_glue_irq_dispatcher } } -void bestcomm_glue_on(const rtems_irq_connect_data* ptr) - { - } - - -void bestcomm_glue_isOn(const rtems_irq_connect_data* ptr) - { - /*return BSP_irq_enabled_at_cpm(ptr->name);*/ - } - - -void bestcomm_glue_off(const rtems_irq_connect_data* ptr) - { - } - -static rtems_irq_connect_data bestcomm_glue_irq_data = - { - - BSP_SIU_IRQ_SMARTCOMM, - (rtems_irq_hdl) bestcomm_glue_irq_dispatcher, - (rtems_irq_hdl_param) NULL, - (rtems_irq_enable) bestcomm_glue_on, - (rtems_irq_disable) bestcomm_glue_off, - (rtems_irq_is_enabled) bestcomm_glue_isOn - }; - static bool bestcomm_glue_is_initialized = false; /*=========================================================================*\ | Function: | @@ -224,12 +195,24 @@ void bestcomm_glue_init | none | \*=========================================================================*/ { + rtems_status_code sc = RTEMS_SUCCESSFUL; + uintptr_t heap_status = 0; + if (!bestcomm_glue_is_initialized) { bestcomm_glue_is_initialized = true; + + heap_status = _Heap_Initialize( + &bestcomm_heap, + (char *) &mpc5200.sram [0] + taskTableBytes, + sizeof(mpc5200.sram) - taskTableBytes, + 4 + ); + assert(heap_status != 0); + /* * Set task bar to begin of sram */ - mpc5200.taskBar = (uint32_t)(&(mpc5200.sram[0])); + mpc5200.sdma.taskBar = (uint32_t)(&(mpc5200.sram[0])); #if 0 /* @@ -244,18 +227,35 @@ void bestcomm_glue_init * the COMM bus. (Yes, _PE -- prefetch enable -- should probably be * named _PD.) */ - mpc5200.PtdCntrl |= SDMA_PTDCNTRL_PE; + mpc5200.sdma.PtdCntrl |= SDMA_PTDCNTRL_PE; TasksInitAPI((uint8*)&mpc5200); - TasksLoadImage( (void *)&(mpc5200.taskBar)); + TasksLoadImage( (void *)&(mpc5200.sdma.taskBar)); /* * initialize interrupt dispatcher */ - if(!BSP_install_rtems_irq_handler (&bestcomm_glue_irq_data)) { - rtems_panic ("Can't attach MPC5x00 BestComm interrupt handler\n"); - } + sc = rtems_interrupt_handler_install( + BSP_SIU_IRQ_SMARTCOMM, + "BESTCOMM", + RTEMS_INTERRUPT_UNIQUE, + bestcomm_glue_irq_dispatcher, + NULL + ); + assert(sc == RTEMS_SUCCESSFUL); + } +} +void *bestcomm_malloc(size_t size) +{ + return _Heap_Allocate(&bestcomm_heap, size); +} + +void bestcomm_free(void *ptr) +{ + if (ptr != NULL) { + bool ok = _Heap_Free(&bestcomm_heap, ptr); + assert(ok); } } diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_glue.h b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_glue.h index 13c3687fc0..aa78ce3209 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_glue.h +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_glue.h @@ -19,7 +19,11 @@ #ifndef _BESTCOMM_GLUE_H #define _BESTCOMM_GLUE_H -#include <rtems.h> +#include <rtems/irq-extension.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ /*=========================================================================*\ | Function: | @@ -69,8 +73,8 @@ void bestcomm_glue_irq_install | Input Parameters: | \*-------------------------------------------------------------------------*/ int bestcomm_taskno, /* task number for handler */ - void (*the_handler)(rtems_irq_hdl_param), /* function to call */ - rtems_irq_hdl_param the_param + rtems_interrupt_handler handler, /* function to call */ + void *arg ); /*-------------------------------------------------------------------------*\ | Return Value: | @@ -99,4 +103,12 @@ void bestcomm_glue_init | none | \*=========================================================================*/ +void *bestcomm_malloc(size_t size); + +void bestcomm_free(void *ptr); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + #endif /* _BESTCOMM_GLUE_H */ diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_priv.h b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_priv.h index 1a3d932b5f..102fc082cb 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_priv.h +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_priv.h @@ -31,7 +31,6 @@ * private data structures that should not be manipulated by API users. */ -extern uint32 SramOffsetGlobal; extern TaskBDIdxTable_t TaskBDIdxTable[MAX_TASKS]; extern int TaskRunning[MAX_TASKS]; extern sint64 MBarPhysOffsetGlobal; diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/load_task.c b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/load_task.c index 2c4c96d84c..c6632955ff 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/load_task.c +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/load_task.c @@ -81,6 +81,4 @@ void TasksLoadImage(sdma_regs *sdma) tt->fdt = (sdma->taskBar & 0xFFFFFF00) + tt->fdt; tt->context += sdma->taskBar; } - - SramOffsetGlobal = taskTableBytes; } diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/bestcomm_cntrl.h b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/bestcomm_cntrl.h index f4273cdb82..3712bae3d0 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/bestcomm_cntrl.h +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/bestcomm_cntrl.h @@ -88,46 +88,54 @@ * Task control macros ******************************************************************************/ #define SDMA_TASK_CFG(RegAddr, TaskNum, AutoStart, AutoStartNum) { \ - *(((uint16 *)RegAddr)+TaskNum) = (uint16)(0x0000 | \ + *(((volatile uint16 *)RegAddr)+TaskNum) = (uint16)(0x0000 | \ ((AutoStart!=0)<<7) | \ (AutoStartNum&0xF) ); \ } #define SDMA_TASK_AUTO_START(RegAddr, TaskNum, AutoStart, AutoStartNum) { \ - *(((uint16 *)RegAddr)+TaskNum) = (uint16)((*(((uint16 *)RegAddr)+TaskNum) & \ + *(((volatile uint16 *)RegAddr)+TaskNum) = (uint16)((*(((volatile uint16 *)RegAddr)+TaskNum) & \ (uint16) 0xff30) | ((uint16)(0x0000 | \ ((AutoStart!=0)<<7) | \ (AutoStartNum&0xF)) )); \ } #define SDMA_TASK_ENABLE(RegAddr, TaskNum) { \ - *(((uint16 *)RegAddr)+TaskNum) |= (uint16)0x8000; \ + *(((volatile uint16 *)RegAddr)+TaskNum) |= (uint16)0x8000; \ } #define SDMA_TASK_DISABLE(RegAddr, TaskNum) { \ - *(((uint16 *)RegAddr)+TaskNum) &= ~(uint16)0x8000; \ + *(((volatile uint16 *)RegAddr)+TaskNum) &= ~(uint16)0x8000; \ } #define SDMA_TASK_STATUS(RegAddr, TaskNum) \ - *(((uint16 *)RegAddr)+TaskNum) + *(((volatile uint16 *)RegAddr)+TaskNum) /******************************************************************************* * Interrupt control macros ******************************************************************************/ -#define SDMA_INT_ENABLE(RegAddr, Bit) { \ - *((uint32 *)RegAddr) &= ~((uint32)(1<<Bit)); \ -} - -#define SDMA_INT_DISABLE(RegAddr, Bit) { \ - *((uint32 *)(RegAddr)) |= ((uint32)(1<<Bit)); \ -} +#define SDMA_INT_ENABLE(RegAddr, Bit) \ + do { \ + rtems_interrupt_level level; \ + rtems_interrupt_disable(level); \ + *((volatile uint32 *) RegAddr) &= ~((uint32) (1 << Bit)); \ + rtems_interrupt_enable(level); \ + } while (0) + +#define SDMA_INT_DISABLE(RegAddr, Bit) \ + do { \ + rtems_interrupt_level level; \ + rtems_interrupt_disable(level); \ + *((volatile uint32 *) (RegAddr)) |= ((uint32)(1 << Bit)); \ + rtems_interrupt_enable(level); \ + } while (0) #define SDMA_INT_SOURCE(RegPend, RegMask) \ - (*((uint32 *)(RegPend)) & (~*((uint32 *)(RegMask))) & (uint32)SDMA_INT_BIT_IMPL) + (*((volatile uint32 *)(RegPend)) & (~*((volatile uint32 *)(RegMask))) & (uint32)SDMA_INT_BIT_IMPL) #define SDMA_INT_PENDING(RegPend, RegMask) \ - (*((uint32 *)(RegPend)) & (~*((uint32 *)(RegMask)))) + (*((volatile uint32 *)(RegPend)) & (~*((volatile uint32 *)(RegMask)))) #define SDMA_INT_TEST(IntSource, Bit) \ (((uint32)IntSource) & ((uint32)(1<<Bit))) @@ -139,7 +147,7 @@ /* Clear the IntPend bit */ #define SDMA_CLEAR_IEVENT(RegAddr, Bit) { \ - *((uint32 *)RegAddr) = ((uint32)(1<<Bit)); \ + *((volatile uint32 *)RegAddr) = ((uint32)(1<<Bit)); \ } #define SDMA_GET_PENDINGBIT(sdma, Bit) \ @@ -175,7 +183,7 @@ /* Determine which task caused a TEA on the XLB */ #define SDMA_TEA_SOURCE(RegPend) \ - (uint32)(((*(uint32 *)RegPend)>>SDMA_INT_BIT_TEA_TASK) & 0xF) + (uint32)(((*(volatile uint32 *)RegPend)>>SDMA_INT_BIT_TEA_TASK) & 0xF) /******************************************************************************* @@ -221,8 +229,8 @@ /* Note that masking the size w/ 0x3 gives the desired value for uint32 */ /* (expressed as 4), namely 0. */ #define SDMA_SET_SIZE(RegAddr, TaskNum, SrcSize, DstSize) \ - *(((uint8 *)RegAddr)+((uint32)(TaskNum/2))) = \ - (uint8)((*(((uint8 *)RegAddr)+((uint32)(TaskNum/2))) & \ + *(((volatile uint8 *)RegAddr)+((uint32)(TaskNum/2))) = \ + (uint8)((*(((volatile uint8 *)RegAddr)+((uint32)(TaskNum/2))) & \ ((TaskNum%2) ? 0xf0 : 0x0f)) | \ ((uint8)(((SrcSize & 0x3)<<2) | \ ( DstSize & 0x3 ) ) <<(4*((int)(1-(TaskNum%2)))))); @@ -231,8 +239,8 @@ /* Set the Initiator in TCR */ #define SDMA_SET_INIT(RegAddr, TaskNum, Initiator) \ { \ - *(((uint16 *)RegAddr)+TaskNum) &= (uint16)0xE0FF; \ - *(((uint16 *)RegAddr)+TaskNum) |= (((0x01F & Initiator)<<8) | \ + *(((volatile uint16 *)RegAddr)+TaskNum) &= (uint16)0xE0FF; \ + *(((volatile uint16 *)RegAddr)+TaskNum) |= (((0x01F & Initiator)<<8) | \ (0<<SDMA_TCR_BIT_HOLD)); \ } @@ -248,16 +256,16 @@ /* Set the Initiator Priority */ #define SDMA_SET_INITIATOR_PRIORITY(sdma, initiator, priority) \ - *(((uint8 *)&sdma->IPR0)+initiator) = priority; + *(((volatile uint8 *)&sdma->IPR0)+initiator) = priority; /* Read DRD initiator number */ #define SDMA_INIT_READ(PtrDRD) \ - (((*(uint32 *)PtrDRD)>>SDMA_DRD_BIT_INIT) & (uint32)0x1F) + (((*(volatile uint32 *)PtrDRD)>>SDMA_DRD_BIT_INIT) & (uint32)0x1F) /* Write DRD initiator number */ #define SDMA_INIT_WRITE(PtrDRD, Initiator) { \ - *(uint32 *)PtrDRD = ((*(uint32 *)PtrDRD) & 0xFC1FFFFF) | \ + *(volatile uint32 *)PtrDRD = ((*(volatile uint32 *)PtrDRD) & 0xFC1FFFFF) | \ (Initiator<<SDMA_DRD_BIT_INIT); \ } diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/tasksetup_bdtable.c b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/tasksetup_bdtable.c index a51c63e625..ee8e0939d9 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/tasksetup_bdtable.c +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/tasksetup_bdtable.c @@ -22,7 +22,10 @@ * ******************************************************************************/ +#include <assert.h> + #include "bestcomm_api.h" +#include "bestcomm_glue.h" #include "task_api/tasksetup_bdtable.h" #include "include/mgt5200/mgt5200.h" @@ -40,8 +43,6 @@ extern const uint32 offsetEntry; TaskBDIdxTable_t TaskBDIdxTable[MAX_TASKS]; -static uint8 *TaskTableFree = 0; - void TaskSetup_BDTable(volatile uint32 *BasePtr, volatile uint32 *LastPtr, volatile uint32 *StartPtr, int TaskNum, uint32 NumBD, uint16 MaxBD, uint8 NumPtr, ApiConfig_t ApiConfig, uint32 Status) @@ -50,16 +51,6 @@ void TaskSetup_BDTable(volatile uint32 *BasePtr, volatile uint32 *LastPtr, volat uint32 *ptr; /* - * If another process has not used SRAM already, then the start value - * will have to be passed in using the TasksSetSramOffset() function. - */ - if (SramOffsetGlobal == 0) { - SramOffsetGlobal = taskTableBytes; - } - - TaskTableFree = MBarGlobal + MBAR_SRAM + SramOffsetGlobal; - - /* * First time through the Buffer Descriptor table configuration * set the buffer descriptor table with parameters that will not * change since they are determined by the task itself. The @@ -70,25 +61,31 @@ void TaskSetup_BDTable(volatile uint32 *BasePtr, volatile uint32 *LastPtr, volat * of the table. */ if (TaskBDIdxTable[TaskNum].BDTablePtr == 0) { - TaskBDIdxTable[TaskNum].BDTablePtr = TaskTableFree; - TaskBDIdxTable[TaskNum].numPtr = NumPtr; - TaskBDIdxTable[TaskNum].apiConfig = ApiConfig; - TaskBDIdxTable[TaskNum].BDStartPtr = StartPtr; - - *StartPtr = *BasePtr = (uint32)((uint32)TaskBDIdxTable[TaskNum].BDTablePtr - + MBarPhysOffsetGlobal); + size_t AllocSize = 0; + void *AllocBegin = NULL; switch (NumPtr) { case 1: - SramOffsetGlobal += MaxBD*sizeof(TaskBD1_t); + AllocSize += MaxBD*sizeof(TaskBD1_t); break; case 2: - SramOffsetGlobal += MaxBD*sizeof(TaskBD2_t); + AllocSize += MaxBD*sizeof(TaskBD2_t); break; default: - /* error */ + assert(0); break; } + + AllocBegin = bestcomm_malloc(AllocSize); + assert(AllocBegin != NULL); + + TaskBDIdxTable[TaskNum].BDTablePtr = AllocBegin; + TaskBDIdxTable[TaskNum].numPtr = NumPtr; + TaskBDIdxTable[TaskNum].apiConfig = ApiConfig; + TaskBDIdxTable[TaskNum].BDStartPtr = StartPtr; + + *StartPtr = *BasePtr = (uint32)((uint32)TaskBDIdxTable[TaskNum].BDTablePtr + + MBarPhysOffsetGlobal); } TaskBDIdxTable[TaskNum].currBDInUse = 0; diff --git a/c/src/lib/libbsp/powerpc/gen5200/configure.ac b/c/src/lib/libbsp/powerpc/gen5200/configure.ac index 6b07dcbeb4..995c9fb716 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/configure.ac +++ b/c/src/lib/libbsp/powerpc/gen5200/configure.ac @@ -25,11 +25,6 @@ RTEMS_BSPOPTS_HELP([INSTRUCTION_CACHE_ENABLE], [If defined, the instruction cache will be enabled after address translation is turned on.]) -RTEMS_BSPOPTS_SET([HAS_UBOOT],[icecube],[1]) -RTEMS_BSPOPTS_SET([HAS_UBOOT],[pm520_*],[1]) -RTEMS_BSPOPTS_HELP([HAS_UBOOT], -[If defined, board boots via U-Boot]) - RTEMS_BSPOPTS_SET([BENCHMARK_IRQ_PROCESSING],[*],[0]) RTEMS_BSPOPTS_HELP([BENCHMARK_IRQ_PROCESSING], [If set to !0, enable code to benchmark IRQ processing.]) @@ -53,17 +48,14 @@ RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[*],[0]) RTEMS_BSPOPTS_HELP([BSP_RESET_BOARD_AT_EXIT], [If set to !0, reset the board when the application exits.]) -RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[pm520_ze30],[0x337F3F77]) -RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[pm520_ze30],[0x01552114]) - -RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[pm520_cr825],[0x330F0F77]) -RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[pm520_cr825],[0x01050444]) +RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[pm520_ze30],[0x037F3F07]) +RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[pm520_ze30],[0x01552104]) RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[brs5l],[0xb30F0F77]) RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[brs5l],[0x91050444]) -RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[icecube],[0x330F0F77]) -RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[icecube],[0x01050444]) +RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[dp2],[0x337F3F77]) +RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[dp2],[0x03550040]) RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[*],[0x330F0F77]) RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[*],[0x01050444]) @@ -83,27 +75,52 @@ RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[pm520_cr825],[0x07]) RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[brs5l],[0x07]) ## on icecube, we only have PSC1 RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[icecube],[0x01]) +## dp2: PSC2 (via USB connector), PSC6 (GPS module) +RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[dp2],[0x22]) +## default RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[*],[0x01]) RTEMS_BSPOPTS_HELP([BSP_UART_AVAIL_MASK], [bit mask to specify the UARTS (PSCs), which should be enabled on this board. Must match the hardware requirements. PSC1 corresponds to the LSB]) +RTEMS_BSPOPTS_SET([MPC5200_PSC_INDEX_FOR_GPS_MODULE],[dp2],[5]) +RTEMS_BSPOPTS_HELP([MPC5200_PSC_INDEX_FOR_GPS_MODULE],[PSC index for GPS module, if defined results in '/dev/gps']) + +RTEMS_BSPOPTS_SET([SINGLE_CHAR_MODE],[dp2],[]) +RTEMS_BSPOPTS_SET([SINGLE_CHAR_MODE],[*],[1]) +RTEMS_BSPOPTS_HELP([SINGLE_CHAR_MODE],[enable single character mode for the PSC console driver]) + +RTEMS_BSPOPTS_SET([UARTS_USE_TERMIOS_INT],[dp2],[1]) +RTEMS_BSPOPTS_HELP([UARTS_USE_TERMIOS_INT],[enable interrupt support for the PSC console driver]) + +RTEMS_BSPOPTS_SET([PRINTK_MINOR],[dp2],[1]) +RTEMS_BSPOPTS_SET([PRINTK_MINOR],[*],[0]) +RTEMS_BSPOPTS_HELP([PRINTK_MINOR],[console minor number used by printk()]) + RTEMS_BSPOPTS_SET([PM520_ZE30],[pm520_ze30],[1]) RTEMS_BSPOPTS_HELP([PM520_ZE30], -[If defined, use custom settings of for the pm520_ze30 BSP]) +[enable settings for PM520 ZE30]) RTEMS_BSPOPTS_SET([PM520_CR825],[pm520_cr825],[1]) RTEMS_BSPOPTS_HELP([PM520_CR825], -[If defined, use custom settings of for the pm520_cr825 BSP]) +[enable settings for PM520 CR825]) RTEMS_BSPOPTS_SET([icecube],[icecube],[1]) RTEMS_BSPOPTS_HELP([icecube], -[If defined, use custom settings of for the icecube BSP]) +[enable settings for IceCube]) RTEMS_BSPOPTS_SET([BRS5L],[brs5l],[1]) RTEMS_BSPOPTS_HELP([BRS5L], -[If defined, use custom settings of for the brs5l BSP]) +[enable settings for BRS5L]) +RTEMS_BSPOPTS_SET([BSP_TYPE_DP2],[dp2],[1]) +RTEMS_BSPOPTS_HELP([BSP_TYPE_DP2], +[enable settings for DP2]) + +RTEMS_BSPOPTS_SET([HAS_UBOOT],[pm520*],[1]) +RTEMS_BSPOPTS_SET([HAS_UBOOT],[icecube],[1]) +RTEMS_BSPOPTS_SET([HAS_UBOOT],[dp2],[1]) +RTEMS_BSPOPTS_HELP([HAS_UBOOT],[enable U-Boot startup]) RTEMS_CHECK_NETWORKING AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes") diff --git a/c/src/lib/libbsp/powerpc/gen5200/console/console.c b/c/src/lib/libbsp/powerpc/gen5200/console/console.c index 11543a907a..2863085047 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/console/console.c +++ b/c/src/lib/libbsp/powerpc/gen5200/console/console.c @@ -95,6 +95,8 @@ /* */ /***********************************************************************/ +#include <assert.h> + #include <rtems.h> #include "../include/mpc5200.h" #include <bsp.h> @@ -233,12 +235,12 @@ int mpc5200_psc_setAttributes( /* * Set upper timer counter */ - psc->ctur = (uint16_t)(baud >> 16); + psc->ctur = (uint8_t) (baud >> 8); /* * Set lower timer counter */ - psc->ctlr = (uint16_t)(baud & 0x0000FFFF); + psc->ctlr = (uint8_t) baud; /* * Reset mode pointer @@ -499,10 +501,7 @@ void mpc5200_uart_psc_initialize( /* * Install rtems irq handler */ - if (!BSP_install_rtems_irq_handler (&consoleIrqData)) { - printk("Unable to connect PSC Irq handler\n"); - rtems_fatal_error_occurred(1); - } + assert(BSP_install_rtems_irq_handler(&consoleIrqData) == 1); #endif /* @@ -675,6 +674,7 @@ rtems_device_driver console_initialize( rtems_device_minor_number console_minor; char dev_name[] = "/dev/ttyx"; uint32_t tty_num = 0; + bool first = true; /* * Always use and set up TERMIOS @@ -695,20 +695,27 @@ rtems_device_driver console_initialize( mpc5200_uart_psc_initialize(console_minor); /* /dev/tty0 */ dev_name[8] = '0' + tty_num; status = rtems_io_register_name (dev_name, major, console_minor); + assert(status == RTEMS_SUCCESSFUL); + + #ifdef MPC5200_PSC_INDEX_FOR_GPS_MODULE + if (console_minor == MPC5200_PSC_INDEX_FOR_GPS_MODULE) { + status = rtems_io_register_name("/dev/gps", major, console_minor); + assert(status == RTEMS_SUCCESSFUL); + } + #endif - if (status != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred(status); + if (first) { + first = false; + + /* Now register the RTEMS console */ + status = rtems_io_register_name ("/dev/console", major, console_minor); + assert(status == RTEMS_SUCCESSFUL); + } tty_num++; } } - /* Now register the RTEMS console */ - status = rtems_io_register_name ("/dev/console", major, PSC1_MINOR); - - if(status != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred (status); - console_initialized = true; return RTEMS_SUCCESSFUL; } diff --git a/c/src/lib/libbsp/powerpc/gen5200/ide/pcmcia_ide.c b/c/src/lib/libbsp/powerpc/gen5200/ide/pcmcia_ide.c index bf4d71f81d..63c6a0b72a 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/ide/pcmcia_ide.c +++ b/c/src/lib/libbsp/powerpc/gen5200/ide/pcmcia_ide.c @@ -122,8 +122,8 @@ #include "../bestcomm/task_api/bestcomm_cntrl.h" #include "../bestcomm/task_api/tasksetup_bdtable.h" -#define IDE_RECV_TASK_NO TASK_GEN_DP_BD_0 -#define TASK_GEN_DP_BD_1 TASK_GEN_DP_BD_1 +#define IDE_RX_TASK_NO TASK_GEN_DP_BD_0 +#define IDE_TX_TASK_NO TASK_GEN_DP_BD_1 static TaskId pcmcia_ide_rxTaskId; /* SDMA RX task ID */ static TaskId pcmcia_ide_txTaskId; /* SDMA TX task ID */ #define PCMCIA_IDE_RD_SECTOR_SIZE 512 /* FIXME: make this better... */ @@ -152,6 +152,20 @@ bool mpc5200_pcmciaide_probe(int minor) bool ide_card_plugged = false; /* assume: we don't have a card plugged in */ struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)(&mpc5200.gpt[GPT2]); + #ifdef BSP_TYPE_DP2 + /* Deactivate RESET signal */ + rtems_interrupt_level level; + rtems_interrupt_disable(level); + mpc5200.gpiowe |= GPIO_W_PIN_PSC1_4; + mpc5200.gpiowod &= ~GPIO_W_PIN_PSC1_4; + mpc5200.gpiowdd |= GPIO_W_PIN_PSC1_4; + mpc5200.gpiowdo |= GPIO_W_PIN_PSC1_4; + rtems_interrupt_enable(level); + /* FIXME */ + volatile int i = 0; + while (++i < 20000000); + #endif + /* enable card detection on GPT2 */ gpt->emsel = (GPT_EMSEL_GPIO_IN | GPT_EMSEL_TIMER_MS_GPIO); @@ -167,6 +181,14 @@ bool mpc5200_pcmciaide_probe(int minor) } +#define DMA1_T0(val) BSP_BFLD32(COUNT_VAL(val), 0, 7) +#define DMA1_TD(val) BSP_BFLD32(COUNT_VAL(val), 8, 15) +#define DMA1_TK(val) BSP_BFLD32(COUNT_VAL(val), 16, 23) +#define DMA1_TM(val) BSP_BFLD32(COUNT_VAL(val), 24, 31) + +#define DMA2_TH(val) BSP_BFLD32(COUNT_VAL(val), 0, 7) +#define DMA2_TJ(val) BSP_BFLD32(COUNT_VAL(val), 8, 15) +#define DMA2_TN(val) BSP_BFLD32(COUNT_VAL(val), 16, 23) rtems_status_code mpc5200_pcmciaide_config_io_speed(int minor, uint16_t modes_avail) { @@ -199,6 +221,9 @@ rtems_status_code mpc5200_pcmciaide_config_io_speed(int minor, uint16_t modes_av mpc5200.ata_pio1 = ATA_PIO_TIMING_1(pio_t0, pio_t2_8, pio_t2_16); mpc5200.ata_pio2 = ATA_PIO_TIMING_2(pio_t4, pio_t1, pio_ta); + mpc5200.ata_dma1 = DMA1_T0(120) | DMA1_TD(70) | DMA1_TK(25) | DMA1_TM(25); + mpc5200.ata_dma2 = DMA2_TH(10) | DMA2_TJ(5) | DMA2_TN(10); + return RTEMS_SUCCESSFUL; } @@ -237,10 +262,10 @@ volatile rtems_id pcmcia_ide_hdl_task = 0; */ static void pcmcia_ide_recv_dmairq_hdl(rtems_irq_hdl_param unused) { - SDMA_CLEAR_IEVENT(&mpc5200.IntPend,TASK_GEN_DP_BD_0); + SDMA_CLEAR_IEVENT(&mpc5200.sdma.IntPend,IDE_RX_TASK_NO); /*Disable receive ints*/ - bestcomm_glue_irq_disable(TASK_GEN_DP_BD_0); + bestcomm_glue_irq_disable(IDE_RX_TASK_NO); pcmcia_ide_rxInterrupts++; /* Rx int has occurred */ @@ -252,10 +277,10 @@ static void pcmcia_ide_recv_dmairq_hdl(rtems_irq_hdl_param unused) static void pcmcia_ide_xmit_dmairq_hdl(rtems_irq_hdl_param unused) { - SDMA_CLEAR_IEVENT(&mpc5200.IntPend,TASK_GEN_DP_BD_1); + SDMA_CLEAR_IEVENT(&mpc5200.sdma.IntPend,IDE_TX_TASK_NO); /*Disable transmit ints*/ - bestcomm_glue_irq_disable(TASK_GEN_DP_BD_1); + bestcomm_glue_irq_disable(IDE_TX_TASK_NO); pcmcia_ide_txInterrupts++; /* Tx int has occurred */ @@ -287,7 +312,7 @@ void mpc5200_pcmciaide_dma_init(int minor) rxParam.IncrDst = sizeof(uint16_t); rxParam.SzDst = sizeof(uint16_t); /* XXX: set this to 32 bit? */ - pcmcia_ide_rxTaskId = TaskSetup(TASK_GEN_DP_BD_0,&rxParam ); + pcmcia_ide_rxTaskId = TaskSetup(IDE_RX_TASK_NO,&rxParam ); /* * Setup the TX task. @@ -303,7 +328,7 @@ void mpc5200_pcmciaide_dma_init(int minor) txParam.IncrDst = 0; txParam.SzDst = sizeof(uint16_t); - pcmcia_ide_txTaskId = TaskSetup( TASK_GEN_DP_BD_1, &txParam ); + pcmcia_ide_txTaskId = TaskSetup( IDE_TX_TASK_NO, &txParam ); /* * FIXME: Init BD rings */ @@ -314,9 +339,10 @@ void mpc5200_pcmciaide_dma_init(int minor) /* * connect interrupt handlers */ - bestcomm_glue_irq_install(TASK_GEN_DP_BD_1,pcmcia_ide_xmit_dmairq_hdl,NULL); - bestcomm_glue_irq_install(TASK_GEN_DP_BD_0,pcmcia_ide_recv_dmairq_hdl,NULL); + bestcomm_glue_irq_install(IDE_TX_TASK_NO,pcmcia_ide_xmit_dmairq_hdl,NULL); + bestcomm_glue_irq_install(IDE_RX_TASK_NO,pcmcia_ide_recv_dmairq_hdl,NULL); } +#endif /* IDE_USE_DMA */ void mpc5200_pcmciaide_dma_blockop(bool is_write, int minor, @@ -326,6 +352,7 @@ void mpc5200_pcmciaide_dma_blockop(bool is_write, uint32_t *pos) { +#if IDE_USE_DMA /* * Nameing: * - a block is one unit of data on disk (multiple sectors) @@ -367,9 +394,9 @@ void mpc5200_pcmciaide_dma_blockop(bool is_write, /* * fill in BD, set interrupt if needed */ - SDMA_CLEAR_IEVENT(&mpc5200.IntPend,(is_write - ? TASK_GEN_DP_BD_1 - : TASK_GEN_DP_BD_0)); + SDMA_CLEAR_IEVENT(&mpc5200.sdma.IntPend,(is_write + ? IDE_TX_TASK_NO + : IDE_RX_TASK_NO)); if (is_write) { TaskBDAssign(pcmcia_ide_txTaskId , (void *)bufs[bufs_to_dma].buffer, @@ -406,10 +433,10 @@ void mpc5200_pcmciaide_dma_blockop(bool is_write, /* * enable interrupts, wait for interrupt event */ - rtems_task_ident(RTEMS_SELF,0,(rtems_id *)&pcmcia_ide_hdl_task); + pcmcia_ide_hdl_task = rtems_task_self(); bestcomm_glue_irq_enable((is_write - ? TASK_GEN_DP_BD_1 - : TASK_GEN_DP_BD_0)); + ? IDE_TX_TASK_NO + : IDE_RX_TASK_NO)); rtems_event_receive(PCMCIA_IDE_INTERRUPT_EVENT, RTEMS_WAIT | RTEMS_EVENT_ANY, @@ -442,8 +469,8 @@ void mpc5200_pcmciaide_dma_blockop(bool is_write, (nxt_bd_idx != TASK_ERR_BD_BUSY) && (bufs_from_dma < bufs_to_dma)); } -} #endif /* IDE_USE_DMA */ +} void mpc5200_pcmciaide_read_block(int minor, uint32_t block_size, rtems_blkdev_sg_buffer *bufs, @@ -521,18 +548,6 @@ void mpc5200_pcmciaide_read_block(int minor, uint32_t block_size, rtems_blkdev_s } } #endif - while (cnt < block_size) { - *lbuf++ = 0; /* fill buffer with dummy data */ - cnt += 2; - (*pos) += 2; - - if((*pos) == llength) { - (*pos) = 0; - (*cbuf)++; - lbuf = bufs[(*cbuf)].buffer; - llength = bufs[(*cbuf)].length; - } - } } } diff --git a/c/src/lib/libbsp/powerpc/gen5200/ide/pcmcia_ide.h b/c/src/lib/libbsp/powerpc/gen5200/ide/pcmcia_ide.h index 907689f0fc..9096319f50 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/ide/pcmcia_ide.h +++ b/c/src/lib/libbsp/powerpc/gen5200/ide/pcmcia_ide.h @@ -80,11 +80,7 @@ #define ATA_HCFG_IORDY (1 << 24) #define ATA_HCFG_IE (1 << 25) -#if 0 -#define COUNT_VAL(nsec) (((nsec)%(IPB_CLOCK/1000000)) ? (((nsec)/(IPB_CLOCK/1000000)) + 1) : ((nsec)/(IPB_CLOCK/1000000))) -#else -#define COUNT_VAL(nsec) (((nsec)*(IPB_CLOCK/1000000)/1000) + 1) -#endif +#define COUNT_VAL(nsec) (((nsec) * (IPB_CLOCK / 1000000) + 999) / 1000) #define PIO_3 0 #define PIO_4 1 diff --git a/c/src/lib/libbsp/powerpc/gen5200/include/bsp.h b/c/src/lib/libbsp/powerpc/gen5200/include/bsp.h index 5bcae681cb..03c96b7960 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/gen5200/include/bsp.h @@ -96,6 +96,8 @@ LINKER_SYMBOL(MBAR); * Embedded Planet EP5200 */ +#elif defined (BSP_TYPE_DP2) + #else #error "board type not defined" #endif @@ -165,14 +167,6 @@ extern int rtems_mpc5200_fec_driver_attach_detach (struct rtems_bsdnet_ifconfig /* functions */ -/* console modes (only termios) */ -#ifdef PRINTK_MINOR -#undef PRINTK_MINOR -#endif -#define PRINTK_MINOR PSC1_MINOR - -#define SINGLE_CHAR_MODE -/* #define UARTS_USE_TERMIOS_INT 1 */ /* #define SHOW_MORE_INIT_SETTINGS 1 */ /* ata modes */ diff --git a/c/src/lib/libbsp/powerpc/gen5200/include/mpc5200.h b/c/src/lib/libbsp/powerpc/gen5200/include/mpc5200.h index ac21c3baaa..89e396804c 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/include/mpc5200.h +++ b/c/src/lib/libbsp/powerpc/gen5200/include/mpc5200.h @@ -26,32 +26,9 @@ /* Additional Harpo Core SPR definitions (603le only) */ #define CSRR0 58 /* Critical Interrupt SRR0 */ #define CSRR1 59 /* Critical Interrupt SRR1 */ -#define SPRG4 276 /* Special Purpose Register 4 */ -#define SPRG5 277 /* Special Purpose Register 5 */ -#define SPRG6 278 /* Special Purpose Register 6 */ -#define SPRG7 279 /* Special Purpose Register 7 */ -#define IBAT4U 560 /* Instruction BAT #0 Upper/Lower */ -#define IBAT4L 561 -#define IBAT5U 562 /* Instruction BAT #1 Upper/Lower */ -#define IBAT5L 563 -#define IBAT6U 564 /* Instruction BAT #2 Upper/Lower */ -#define IBAT6L 565 -#define IBAT7U 566 /* Instruction BAT #3 Upper/Lower */ -#define IBAT7L 567 -#define DBAT4U 568 /* Data BAT #0 Upper/Lower */ -#define DBAT4L 569 -#define DBAT5U 570 /* Data BAT #1 Upper/Lower */ -#define DBAT5L 571 -#define DBAT6U 572 /* Data BAT #2 Upper/Lower */ -#define DBAT6L 573 -#define DBAT7U 574 /* Data BAT #3 Upper/Lower */ -#define DBAT7L 575 #define DABR2 1000 /* Data Address Breakpoint #2 */ #define DBCR 1001 /* Data Address Breakpoint Control */ #define IBCR 1002 /* Instruction Breakpoint Control */ -#define HID1 1009 /* Hardware Implementation 1 */ -#define HID2 1011 /* Hardware Implementation 2 */ -#define DABR 1013 /* Data Address Breakpoint */ #define IABR2 1018 /* Instruction Breakpoint #2 */ /* @@ -68,8 +45,7 @@ #ifndef ASM #include <rtems.h> -/* You can directly use the bit value from the MPC5200B User's Manual */ -#define MPC5200_BIT32(bit) (((uint32_t) 1) << (31 - (bit))) +#include <bsp/utility.h> #ifdef __cplusplus extern "C" { @@ -232,6 +208,177 @@ extern "C" { #define FEC_FIFO_CNTRL_OF_MASK 0x00080000 /* overflow mask */ /* 0x0007ffff reserved */ +#define SDMA_TCR_EN BSP_BBIT16(0) +#define SDMA_TCR_VAL BSP_BBIT16(1) +#define SDMA_TCR_ALW_INIT BSP_BBIT16(2) +#define SDMA_TCR_IN(val) BSP_BFLD16(val, 3, 7) +#define SDMA_TCR_AUTO_START BSP_BBIT16(8) +#define SDMA_TCR_HIGH_EN BSP_BBIT16(9) +#define SDMA_TCR_HOLD BSP_BBIT16(10) +#define SDMA_TCR_AS(val) BSP_BFLD16(val, 12, 15) + +#define SDMA_IPR_HOLD BSP_BBIT8(0) +#define SDMA_IPR_PRIOR(val) BSP_BFLD8(val, 5, 7) + +#define SDMA_REQMUX_SET_31(reg, val) BSP_BFLD32SET(reg, val, 0, 1) +#define SDMA_REQMUX_SET_30(reg, val) BSP_BFLD32SET(reg, val, 2, 3) +#define SDMA_REQMUX_SET_29(reg, val) BSP_BFLD32SET(reg, val, 4, 5) +#define SDMA_REQMUX_SET_28(reg, val) BSP_BFLD32SET(reg, val, 6, 7) +#define SDMA_REQMUX_SET_27(reg, val) BSP_BFLD32SET(reg, val, 8, 9) +#define SDMA_REQMUX_SET_26(reg, val) BSP_BFLD32SET(reg, val, 10, 11) +#define SDMA_REQMUX_SET_25(reg, val) BSP_BFLD32SET(reg, val, 12, 13) +#define SDMA_REQMUX_SET_24(reg, val) BSP_BFLD32SET(reg, val, 14, 15) +#define SDMA_REQMUX_SET_23(reg, val) BSP_BFLD32SET(reg, val, 16, 17) +#define SDMA_REQMUX_SET_22(reg, val) BSP_BFLD32SET(reg, val, 18, 19) +#define SDMA_REQMUX_SET_21(reg, val) BSP_BFLD32SET(reg, val, 20, 21) +#define SDMA_REQMUX_SET_20(reg, val) BSP_BFLD32SET(reg, val, 22, 23) +#define SDMA_REQMUX_SET_19(reg, val) BSP_BFLD32SET(reg, val, 24, 25) +#define SDMA_REQMUX_SET_18(reg, val) BSP_BFLD32SET(reg, val, 26, 27) +#define SDMA_REQMUX_SET_17(reg, val) BSP_BFLD32SET(reg, val, 28, 29) +#define SDMA_REQMUX_SET_16(reg, val) BSP_BFLD32SET(reg, val, 30, 31) + +/* SDMA / BestComm */ +typedef struct { + uint32_t taskBar; + uint32_t currentPointer; + uint32_t endPointer; + uint32_t variablePointer; + uint8_t IntVect1; + uint8_t IntVect2; + uint16_t PtdCntrl; + uint32_t IntPend; + uint32_t IntMask; + uint16_t tcr [16]; + uint8_t ipr [32]; + uint32_t cReqSelect; + uint32_t task_size0; + uint32_t task_size1; + uint32_t reserved_0; + uint32_t reserved_1; + uint32_t Value1; + uint32_t Value2; + uint32_t Control; + uint32_t Status; +} mpc5200_sdma; + +typedef struct { +#define CSC_CFG_WAITP(val) BSP_BFLD32(val, 0, 7) +#define CSC_CFG_WAITX(val) BSP_BFLD32(val, 8, 15) +#define CSC_CFG_MX BSP_BBIT32(16) +#define CSC_CFG_AA BSP_BBIT32(18) +#define CSC_CFG_CE BSP_BBIT32(19) +#define CSC_CFG_AS(val) BSP_BFLD32(val, 20, 21) +#define CSC_CFG_DS(val) BSP_BFLD32(val, 22, 23) +#define CSC_CFG_BANK(val) BSP_BFLD32(val, 24, 25) +#define CSC_CFG_WTYP(val) BSP_BFLD32(val, 26, 27) +#define CSC_CFG_WS BSP_BBIT32(28) +#define CSC_CFG_RS BSP_BBIT32(29) +#define CSC_CFG_WO BSP_BBIT32(30) +#define CSC_CFG_RO BSP_BBIT32(31) + uint32_t config_0; + uint32_t config_1; + uint32_t config_2; + uint32_t config_3; + uint32_t config_4; + uint32_t config_5; + +#define CSC_CTRL_ME BSP_BBIT32(7) + uint32_t control; + +#define CSC_STAT_WOERR BSP_BBIT32(2) +#define CSC_STAT_ROERR BSP_BBIT32(3) +#define CSC_STAT_GET_CSXERR(reg) BSP_BFLD32GET(reg, 5, 7) + uint32_t status; + + uint32_t config_6; + uint32_t config_7; + +#define CSC_BST_CTRL_CW7 BSP_BBIT32(0) +#define CSC_BST_CTRL_SLB7 BSP_BBIT32(1) +#define CSC_BST_CTRL_BRE7 BSP_BBIT32(3) +#define CSC_BST_CTRL_CW6 BSP_BBIT32(4) +#define CSC_BST_CTRL_SLB6 BSP_BBIT32(5) +#define CSC_BST_CTRL_BRE6 BSP_BBIT32(7) +#define CSC_BST_CTRL_CW5 BSP_BBIT32(8) +#define CSC_BST_CTRL_SLB5 BSP_BBIT32(9) +#define CSC_BST_CTRL_BRE5 BSP_BBIT32(11) +#define CSC_BST_CTRL_CW4 BSP_BBIT32(12) +#define CSC_BST_CTRL_SLB4 BSP_BBIT32(13) +#define CSC_BST_CTRL_BRE4 BSP_BBIT32(15) +#define CSC_BST_CTRL_CW3 BSP_BBIT32(16) +#define CSC_BST_CTRL_SLB3 BSP_BBIT32(17) +#define CSC_BST_CTRL_BRE3 BSP_BBIT32(19) +#define CSC_BST_CTRL_CW2 BSP_BBIT32(20) +#define CSC_BST_CTRL_SLB2 BSP_BBIT32(21) +#define CSC_BST_CTRL_BRE2 BSP_BBIT32(23) +#define CSC_BST_CTRL_CW1 BSP_BBIT32(24) +#define CSC_BST_CTRL_SLB1 BSP_BBIT32(25) +#define CSC_BST_CTRL_BRE1 BSP_BBIT32(27) +#define CSC_BST_CTRL_CW0 BSP_BBIT32(28) +#define CSC_BST_CTRL_SLB0 BSP_BBIT32(29) +#define CSC_BST_CTRL_BRE0 BSP_BBIT32(31) + uint32_t burst_control; + +#define CSC_DCYC_CTRL_DC7(val) BSP_BFLD32(val, 2, 3) +#define CSC_DCYC_CTRL_SET_DC7(reg, val) BSP_BFLD32SET(reg, val, 2, 3) +#define CSC_DCYC_CTRL_DC6(val) BSP_BFLD32(val, 6, 7) +#define CSC_DCYC_CTRL_SET_DC6(reg, val) BSP_BFLD32SET(reg, val, 6, 7) +#define CSC_DCYC_CTRL_DC5(val) BSP_BFLD32(val, 10, 11) +#define CSC_DCYC_CTRL_SET_DC5(reg, val) BSP_BFLD32SET(reg, val, 10, 11) +#define CSC_DCYC_CTRL_DC4(val) BSP_BFLD32(val, 14, 15) +#define CSC_DCYC_CTRL_SET_DC4(reg, val) BSP_BFLD32SET(reg, val, 14, 15) +#define CSC_DCYC_CTRL_DC3(val) BSP_BFLD32(val, 18, 19) +#define CSC_DCYC_CTRL_SET_DC3(reg, val) BSP_BFLD32SET(reg, val, 18, 19) +#define CSC_DCYC_CTRL_DC2(val) BSP_BFLD32(val, 22, 23) +#define CSC_DCYC_CTRL_SET_DC2(reg, val) BSP_BFLD32SET(reg, val, 22, 23) +#define CSC_DCYC_CTRL_DC1(val) BSP_BFLD32(val, 26, 27) +#define CSC_DCYC_CTRL_SET_DC1(reg, val) BSP_BFLD32SET(reg, val, 26, 27) +#define CSC_DCYC_CTRL_DC0(val) BSP_BFLD32(val, 30, 31) +#define CSC_DCYC_CTRL_SET_DC0(reg, val) BSP_BFLD32SET(reg, val, 30, 31) + uint32_t deadcycle_control; + + uint8_t reserved [208]; +} mpc5200_csc; + +typedef struct { + uint32_t memory_address_base; + uint32_t cs0_start_address; + uint32_t cs0_stop_address; + uint32_t cs1_start_address; + uint32_t cs1_stop_address; + uint32_t cs2_start_address; + uint32_t cs2_stop_address; + uint32_t cs3_start_address; + uint32_t cs3_stop_address; + uint32_t cs4_start_address; + uint32_t cs4_stop_address; + uint32_t cs5_start_address; + uint32_t cs5_stop_address; + uint32_t sdram_chip_select_0; + uint32_t sdram_chip_select_1; + uint8_t reserved_0 [16]; + uint32_t boot_start_address; + uint32_t boot_stop_address; + +#define MM_IPBI_CTRL_CS7ENA BSP_BBIT16(4) +#define MM_IPBI_CTRL_CS6ENA BSP_BBIT16(5) +#define MM_IPBI_CTRL_BOOTENA BSP_BBIT16(6) +#define MM_IPBI_CTRL_CS5ENA BSP_BBIT16(10) +#define MM_IPBI_CTRL_CS4ENA BSP_BBIT16(11) +#define MM_IPBI_CTRL_CS3ENA BSP_BBIT16(12) +#define MM_IPBI_CTRL_CS2ENA BSP_BBIT16(13) +#define MM_IPBI_CTRL_CS1ENA BSP_BBIT16(14) +#define MM_IPBI_CTRL_CS0ENA BSP_BBIT16(15) + uint16_t ipbi_control; + + uint16_t wait_state_enable; + uint32_t cs6_start_address; + uint32_t cs6_stop_address; + uint32_t cs7_start_address; + uint32_t cs7_stop_address; + uint8_t reserved_1 [152]; +} mpc5200_mm; + /* ************************************************************************* * MPC5x00 internal register memory map * @@ -241,12 +388,7 @@ typedef struct mpc5200_ { /* * memory map registers (MBAR + 0) */ - volatile uint8_t mm[0x80]; - - /* - * arbiter registers (processor bus) (MBAR + 0x80) - */ - volatile uint8_t arb[0x80]; + volatile mpc5200_mm mm; /* * SDRAM memory controller registers (MBAR + 0x100) @@ -261,7 +403,7 @@ typedef struct mpc5200_ { /* * chip selct controller registers(MBAR + 0x300) */ - volatile uint8_t csc[0x100]; + volatile mpc5200_csc csc; /* * SmartComm timer registers (MBAR + 0x400) @@ -275,6 +417,26 @@ typedef struct mpc5200_ { volatile uint32_t per_pri_1; /* + 0x04 */ volatile uint32_t per_pri_2; /* + 0x08 */ volatile uint32_t per_pri_3; /* + 0x0C */ + +#define ICTL_EET_ECLR0 BSP_BBIT32(4) +#define ICTL_EET_ECLR1 BSP_BBIT32(5) +#define ICTL_EET_ECLR2 BSP_BBIT32(6) +#define ICTL_EET_ECLR3 BSP_BBIT32(7) +#define ICTL_EET_ETYPE0(val) BSP_BFLD32(val, 8, 9) +#define ICTL_EET_ETYPE1(val) BSP_BFLD32(val, 10, 11) +#define ICTL_EET_ETYPE2(val) BSP_BFLD32(val, 12, 13) +#define ICTL_EET_ETYPE3(val) BSP_BFLD32(val, 14, 15) +#define ICTL_EET_SET_ETYPE0(reg, val) BSP_BFLD32SET(reg, val, 8, 9) +#define ICTL_EET_SET_ETYPE1(reg, val) BSP_BFLD32SET(reg, val, 10, 11) +#define ICTL_EET_SET_ETYPE2(reg, val) BSP_BFLD32SET(reg, val, 12, 13) +#define ICTL_EET_SET_ETYPE3(reg, val) BSP_BFLD32SET(reg, val, 14, 15) +#define ICTL_EET_MEE BSP_BBIT32(19) +#define ICTL_EET_EENA0 BSP_BBIT32(20) +#define ICTL_EET_EENA1 BSP_BBIT32(21) +#define ICTL_EET_EENA2 BSP_BBIT32(22) +#define ICTL_EET_EENA3 BSP_BBIT32(23) +#define ICTL_EET_CEB BSP_BBIT32(31) + volatile uint32_t ext_en_type; /* + 0x10 */ volatile uint32_t crit_pri_main_mask;/* + 0x14 */ volatile uint32_t main_pri_1; /* + 0x18 */ @@ -499,30 +661,30 @@ typedef struct mpc5200_ { #define GPIO_PCR_PSC2 0x00000070 #define GPIO_PCR_PSC1 0x00000007 - #define GPIO_S_PIN_IR_USB_CLK MPC5200_BIT32(2) - #define GPIO_S_PIN_IRDA_TX MPC5200_BIT32(3) - #define GPIO_S_PIN_ETH_11 MPC5200_BIT32(4) - #define GPIO_S_PIN_ETH_10 MPC5200_BIT32(5) - #define GPIO_S_PIN_ETH_9 MPC5200_BIT32(6) - #define GPIO_S_PIN_ETH_8 MPC5200_BIT32(7) - #define GPIO_S_PIN_USB1_8 MPC5200_BIT32(12) - #define GPIO_S_PIN_USB1_7 MPC5200_BIT32(13) - #define GPIO_S_PIN_USB1_6 MPC5200_BIT32(14) - #define GPIO_S_PIN_USB1_0 MPC5200_BIT32(15) - #define GPIO_S_PIN_PSC3_7 MPC5200_BIT32(18) - #define GPIO_S_PIN_PSC3_6 MPC5200_BIT32(19) - #define GPIO_S_PIN_PSC3_3 MPC5200_BIT32(20) - #define GPIO_S_PIN_PSC3_2 MPC5200_BIT32(21) - #define GPIO_S_PIN_PSC3_1 MPC5200_BIT32(22) - #define GPIO_S_PIN_PSC3_0 MPC5200_BIT32(23) - #define GPIO_S_PIN_PSC2_3 MPC5200_BIT32(24) - #define GPIO_S_PIN_PSC2_2 MPC5200_BIT32(25) - #define GPIO_S_PIN_PSC2_1 MPC5200_BIT32(26) - #define GPIO_S_PIN_PSC2_0 MPC5200_BIT32(27) - #define GPIO_S_PIN_PSC1_3 MPC5200_BIT32(28) - #define GPIO_S_PIN_PSC1_2 MPC5200_BIT32(29) - #define GPIO_S_PIN_PSC1_1 MPC5200_BIT32(30) - #define GPIO_S_PIN_PSC1_0 MPC5200_BIT32(31) + #define GPIO_S_PIN_IR_USB_CLK BSP_BBIT32(2) + #define GPIO_S_PIN_IRDA_TX BSP_BBIT32(3) + #define GPIO_S_PIN_ETH_11 BSP_BBIT32(4) + #define GPIO_S_PIN_ETH_10 BSP_BBIT32(5) + #define GPIO_S_PIN_ETH_9 BSP_BBIT32(6) + #define GPIO_S_PIN_ETH_8 BSP_BBIT32(7) + #define GPIO_S_PIN_USB1_8 BSP_BBIT32(12) + #define GPIO_S_PIN_USB1_7 BSP_BBIT32(13) + #define GPIO_S_PIN_USB1_6 BSP_BBIT32(14) + #define GPIO_S_PIN_USB1_0 BSP_BBIT32(15) + #define GPIO_S_PIN_PSC3_7 BSP_BBIT32(18) + #define GPIO_S_PIN_PSC3_6 BSP_BBIT32(19) + #define GPIO_S_PIN_PSC3_3 BSP_BBIT32(20) + #define GPIO_S_PIN_PSC3_2 BSP_BBIT32(21) + #define GPIO_S_PIN_PSC3_1 BSP_BBIT32(22) + #define GPIO_S_PIN_PSC3_0 BSP_BBIT32(23) + #define GPIO_S_PIN_PSC2_3 BSP_BBIT32(24) + #define GPIO_S_PIN_PSC2_2 BSP_BBIT32(25) + #define GPIO_S_PIN_PSC2_1 BSP_BBIT32(26) + #define GPIO_S_PIN_PSC2_0 BSP_BBIT32(27) + #define GPIO_S_PIN_PSC1_3 BSP_BBIT32(28) + #define GPIO_S_PIN_PSC1_2 BSP_BBIT32(29) + #define GPIO_S_PIN_PSC1_1 BSP_BBIT32(30) + #define GPIO_S_PIN_PSC1_0 BSP_BBIT32(31) volatile uint32_t gpiosen; /* + 0x04 */ volatile uint32_t gpiosod; /* + 0x08 */ @@ -530,29 +692,29 @@ typedef struct mpc5200_ { volatile uint32_t gpiosdo; /* + 0x10 */ volatile uint32_t gpiosdi; /* + 0x14 */ - #define GPIO_O_PIN_ETH_7 MPC5200_BIT32(0) - #define GPIO_O_PIN_ETH_6 MPC5200_BIT32(1) - #define GPIO_O_PIN_ETH_5 MPC5200_BIT32(2) - #define GPIO_O_PIN_ETH_4 MPC5200_BIT32(3) - #define GPIO_O_PIN_ETH_3 MPC5200_BIT32(4) - #define GPIO_O_PIN_ETH_2 MPC5200_BIT32(5) - #define GPIO_O_PIN_ETH_1 MPC5200_BIT32(6) - #define GPIO_O_PIN_ETH_0 MPC5200_BIT32(7) - #define GPIO_O_PIN_I2C_3 MPC5200_BIT32(13) - #define GPIO_O_PIN_I2C_0 MPC5200_BIT32(14) - #define GPIO_O_PIN_I2C_1 MPC5200_BIT32(15) + #define GPIO_O_PIN_ETH_7 BSP_BBIT32(0) + #define GPIO_O_PIN_ETH_6 BSP_BBIT32(1) + #define GPIO_O_PIN_ETH_5 BSP_BBIT32(2) + #define GPIO_O_PIN_ETH_4 BSP_BBIT32(3) + #define GPIO_O_PIN_ETH_3 BSP_BBIT32(4) + #define GPIO_O_PIN_ETH_2 BSP_BBIT32(5) + #define GPIO_O_PIN_ETH_1 BSP_BBIT32(6) + #define GPIO_O_PIN_ETH_0 BSP_BBIT32(7) + #define GPIO_O_PIN_I2C_3 BSP_BBIT32(13) + #define GPIO_O_PIN_I2C_0 BSP_BBIT32(14) + #define GPIO_O_PIN_I2C_1 BSP_BBIT32(15) volatile uint32_t gpiooe; /* + 0x18 */ volatile uint32_t gpioodo; /* + 0x1C */ - #define GPIO_I_PIN_ETH_16 MPC5200_BIT32(0) - #define GPIO_I_PIN_ETH_15 MPC5200_BIT32(1) - #define GPIO_I_PIN_ETH_14 MPC5200_BIT32(2) - #define GPIO_I_PIN_ETH_13 MPC5200_BIT32(3) - #define GPIO_I_PIN_USB1_9 MPC5200_BIT32(4) - #define GPIO_I_PIN_PSC3_8 MPC5200_BIT32(5) - #define GPIO_I_PIN_PSC3_5 MPC5200_BIT32(6) - #define GPIO_I_PIN_PSC3_4 MPC5200_BIT32(7) + #define GPIO_I_PIN_ETH_16 BSP_BBIT32(0) + #define GPIO_I_PIN_ETH_15 BSP_BBIT32(1) + #define GPIO_I_PIN_ETH_14 BSP_BBIT32(2) + #define GPIO_I_PIN_ETH_13 BSP_BBIT32(3) + #define GPIO_I_PIN_USB1_9 BSP_BBIT32(4) + #define GPIO_I_PIN_PSC3_8 BSP_BBIT32(5) + #define GPIO_I_PIN_PSC3_5 BSP_BBIT32(6) + #define GPIO_I_PIN_PSC3_4 BSP_BBIT32(7) volatile uint32_t gpiosie; /* + 0x20 */ #define GPIO_SIE_SINT_7_ETH_16_PIN 0x80000000 @@ -589,6 +751,15 @@ typedef struct mpc5200_ { #define GPIO_SIIE_SINT_0_PSC3_4_PIN 0x01000000 volatile uint32_t gpiosiit; /* + 0x34 */ + #define GPIO_SIIT_SET_ETH_16_PIN(reg, val) BSP_BFLD32SET(reg, val, 0, 1) + #define GPIO_SIIT_SET_ETH_15_PIN(reg, val) BSP_BFLD32SET(reg, val, 2, 3) + #define GPIO_SIIT_SET_ETH_14_PIN(reg, val) BSP_BFLD32SET(reg, val, 4, 5) + #define GPIO_SIIT_SET_ETH_13_PIN(reg, val) BSP_BFLD32SET(reg, val, 6, 7) + #define GPIO_SIIT_SET_USB1_9_PIN(reg, val) BSP_BFLD32SET(reg, val, 8, 9) + #define GPIO_SIIT_SET_PSC3_8_PIN(reg, val) BSP_BFLD32SET(reg, val, 10, 11) + #define GPIO_SIIT_SET_PSC3_5_PIN(reg, val) BSP_BFLD32SET(reg, val, 12, 13) + #define GPIO_SIIT_SET_PSC3_4_PIN(reg, val) BSP_BFLD32SET(reg, val, 14, 15) + #define GPIO_SIIT_SINT_7_ETH_16_PIN_MASK 0xc0000000 #define GPIO_SIIT_SINT_6_ETH_15_PIN_MASK 0x30000000 #define GPIO_SIIT_SINT_5_ETH_14_PIN_MASK 0x0c000000 @@ -641,14 +812,14 @@ typedef struct mpc5200_ { * GPIO wakeup registers (MBAR + 0xC00) */ - #define GPIO_W_PIN_GPIO_WKUP_7 MPC5200_BIT32(0) - #define GPIO_W_PIN_GPIO_WKUP_6 MPC5200_BIT32(1) - #define GPIO_W_PIN_PSC6_1 MPC5200_BIT32(2) - #define GPIO_W_PIN_PSC6_0 MPC5200_BIT32(3) - #define GPIO_W_PIN_ETH_17 MPC5200_BIT32(4) - #define GPIO_W_PIN_PSC3_9 MPC5200_BIT32(5) - #define GPIO_W_PIN_PSC2_4 MPC5200_BIT32(6) - #define GPIO_W_PIN_PSC1_4 MPC5200_BIT32(7) + #define GPIO_W_PIN_GPIO_WKUP_7 BSP_BBIT32(0) + #define GPIO_W_PIN_GPIO_WKUP_6 BSP_BBIT32(1) + #define GPIO_W_PIN_PSC6_1 BSP_BBIT32(2) + #define GPIO_W_PIN_PSC6_0 BSP_BBIT32(3) + #define GPIO_W_PIN_ETH_17 BSP_BBIT32(4) + #define GPIO_W_PIN_PSC3_9 BSP_BBIT32(5) + #define GPIO_W_PIN_PSC2_4 BSP_BBIT32(6) + #define GPIO_W_PIN_PSC1_4 BSP_BBIT32(7) volatile uint32_t gpiowe; /* + 0x00 */ volatile uint32_t gpiowod; /* + 0x04 */ @@ -685,83 +856,8 @@ typedef struct mpc5200_ { /* * SmartComm DMA registers (MBAR + 0x1200) */ - volatile uint32_t taskBar; /* + 0x00 sdTpb */ - volatile uint32_t currentPointer; /* + 0x04 sdMdeComplex */ - volatile uint32_t endPointer; /* + 0x08 sdMdeComplex */ - volatile uint32_t variablePointer; /* + 0x0c sdMdeComplex */ - - /* - * The following are Priority Task Decoder (ptd) regs in sdma/rtl_v/sdPtd.v. - * The ptd register map below is from the smartcomm spec, table 3-2, page 3-54. - * The spec shows the ptd map as 20 words, but sdPtd.v has only implemented 19. - * The word commented out below is the one which is not implemented. - */ + volatile mpc5200_sdma sdma; - /* volatile uint8_t IntVect; */ /* - * + 0xXX sdPtd read only - */ - - /* volatile uint8_t res0[3]; */ /* - * + 0xXX sdPtd read only - */ - volatile uint8_t IntVect1; /* + 0x10 sdPtd */ - volatile uint8_t IntVect2; /* + 0x11 sdPtd */ - volatile uint16_t PtdCntrl; /* + 0x12 sdPtd */ - - volatile uint32_t IntPend; /* + 0x14 sdPtd */ - volatile uint32_t IntMask; /* + 0x18 sdPtd */ - - volatile uint32_t TCR01; /* + 0x1c sdPtd */ - volatile uint32_t TCR23; /* + 0x20 sdPtd */ - volatile uint32_t TCR45; /* + 0x24 sdPtd */ - volatile uint32_t TCR67; /* + 0x28 sdPtd */ - volatile uint32_t TCR89; /* + 0x2c sdPtd */ - volatile uint32_t TCRAB; /* + 0x30 sdPtd */ - volatile uint32_t TCRCD; /* + 0x34 sdPtd */ - volatile uint32_t TCREF; /* + 0x38 sdPtd */ - - volatile uint8_t IPR0; /* + 0x3c sdPtd */ - volatile uint8_t IPR1; /* + 0x3d sdPtd */ - volatile uint8_t IPR2; /* + 0x3e sdPtd */ - volatile uint8_t IPR3; /* + 0x3f sdPtd */ - volatile uint8_t IPR4; /* + 0x40 sdPtd */ - volatile uint8_t IPR5; /* + 0x41 sdPtd */ - volatile uint8_t IPR6; /* + 0x42 sdPtd */ - volatile uint8_t IPR7; /* + 0x43 sdPtd */ - volatile uint8_t IPR8; /* + 0x44 sdPtd */ - volatile uint8_t IPR9; /* + 0x45 sdPtd */ - volatile uint8_t IPR10; /* + 0x46 sdPtd */ - volatile uint8_t IPR11; /* + 0x47 sdPtd */ - volatile uint8_t IPR12; /* + 0x48 sdPtd */ - volatile uint8_t IPR13; /* + 0x49 sdPtd */ - volatile uint8_t IPR14; /* + 0x4a sdPtd */ - volatile uint8_t IPR15; /* + 0x4b sdPtd */ - volatile uint8_t IPR16; /* + 0x4c sdPtd */ - volatile uint8_t IPR17; /* + 0x4d sdPtd */ - volatile uint8_t IPR18; /* + 0x4e sdPtd */ - volatile uint8_t IPR19; /* + 0x4f sdPtd */ - volatile uint8_t IPR20; /* + 0x50 sdPtd */ - volatile uint8_t IPR21; /* + 0x51 sdPtd */ - volatile uint8_t IPR22; /* + 0x52 sdPtd */ - volatile uint8_t IPR23; /* + 0x53 sdPtd */ - volatile uint8_t IPR24; /* + 0x54 sdPtd */ - volatile uint8_t IPR25; /* + 0x55 sdPtd */ - volatile uint8_t IPR26; /* + 0x56 sdPtd */ - volatile uint8_t IPR27; /* + 0x57 sdPtd */ - volatile uint8_t IPR28; /* + 0x58 sdPtd */ - volatile uint8_t IPR29; /* + 0x59 sdPtd */ - volatile uint8_t IPR30; /* + 0x5a sdPtd */ - volatile uint8_t IPR31; /* + 0x5b sdPtd */ - - volatile uint32_t res5; /* reserved */ - volatile uint32_t res6; /* reserved */ - volatile uint32_t res7; /* reserved */ - volatile uint32_t MDEDebug; /* + 0x68 sdMdeComplex */ - volatile uint32_t ADSDebug; /* + 0x6c sdAdsTop */ - volatile uint32_t Value1; /* + 0x70 sdDbg */ - volatile uint32_t Value2; /* + 0x74 sdDbg */ - volatile uint32_t Control; /* + 0x78 sdDbg */ - volatile uint32_t Status; /* + 0x7c sdDbg */ volatile uint32_t EU00; /* + 0x80 sdMac macer reg */ volatile uint32_t EU01; /* + 0x84 sdMac macemr reg */ volatile uint32_t EU02; /* + 0x88 unused */ @@ -816,8 +912,32 @@ typedef struct mpc5200_ { volatile uint32_t reserved14; /* MBAR_XLB_ARB + 0x0038 reserved */ volatile uint32_t reserved15; /* MBAR_XLB_ARB + 0x003c reserved */ +#define XLB_CFG_PLDIS BSP_BBIT32(0) +#define XLB_CFG_BSDIS BSP_BBIT32(15) +#define XLB_CFG_SE BSP_BBIT32(16) +#define XLB_CFG_USE_WWF BSP_BBIT32(17) +#define XLB_CFG_TBEN BSP_BBIT32(18) +#define XLB_CFG_WS BSP_BBIT32(20) +#define XLB_CFG_SP(val) BSP_BFLD32(val, 21, 23) +#define XLB_CFG_SET_SP(reg, val) BSP_BFLD32SET(reg, val, 21, 23) +#define XLB_CFG_PM(val) BSP_BFLD32(val, 25, 26) +#define XLB_CFG_SET_PM(reg, val) BSP_BFLD32SET(reg, val, 25, 26) +#define XLB_CFG_BA BSP_BBIT32(28) +#define XLB_CFG_DT BSP_BBIT32(29) +#define XLB_CFG_AT BSP_BBIT32(30) + volatile uint32_t config; /* MBAR_XLB_ARB + 0x0040 */ volatile uint32_t version; /* MBAR_XLB_ARB + 0x0044 */ + +#define XLB_ST_SEA BSP_BBIT32(23) +#define XLB_ST_MM BSP_BBIT32(24) +#define XLB_ST_TTA BSP_BBIT32(25) +#define XLB_ST_TTR BSP_BBIT32(26) +#define XLB_ST_ECW BSP_BBIT32(27) +#define XLB_ST_TTM BSP_BBIT32(28) +#define XLB_ST_BA BSP_BBIT32(29) +#define XLB_ST_DT BSP_BBIT32(30) +#define XLB_ST_AT BSP_BBIT32(31) /* read only = 0x0001 */ volatile uint32_t xlb_status; /* MBAR_XLB_ARB + 0x0048 */ volatile uint32_t int_enable; /* MBAR_XLB_ARB + 0x004c */ @@ -1150,7 +1270,20 @@ typedef struct mpc5200_ { /* ATA FIFO registers (offset 0x3C-0x50) */ volatile uint32_t ata_rtfdwr; /* + 0x3C */ + +#define ATA_RTFSR_ERR BSP_BBIT32(9) +#define ATA_RTFSR_UF BSP_BBIT32(10) +#define ATA_RTFSR_OF BSP_BBIT32(11) +#define ATA_RTFSR_FULL BSP_BBIT32(12) +#define ATA_RTFSR_HI BSP_BBIT32(13) +#define ATA_RTFSR_LO BSP_BBIT32(14) +#define ATA_RTFSR_EMPTY BSP_BBIT32(15) + volatile uint32_t ata_rtfsr; /* + 0x40 */ + +#define ATA_RTFCR_WFR BSP_BBIT32(2) +#define ATA_RTFCR_GR(val) BSP_BFLD32(val, 5, 7) + volatile uint32_t ata_rtfcr; /* + 0x44 */ volatile uint32_t ata_rtfar; /* + 0x48 */ volatile uint32_t ata_rtfrpr; /* + 0x4C */ diff --git a/c/src/lib/libbsp/powerpc/gen5200/include/mscan-base.h b/c/src/lib/libbsp/powerpc/gen5200/include/mscan-base.h index 9fd87a507c..e28663f3c1 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/include/mscan-base.h +++ b/c/src/lib/libbsp/powerpc/gen5200/include/mscan-base.h @@ -248,35 +248,35 @@ typedef struct { uint8_t tier; } mscan_context; -bool mscan_enable( mscan *m, unsigned bit_rate); +bool mscan_enable( volatile mscan *m, unsigned bit_rate); -void mscan_disable( mscan *m); +void mscan_disable( volatile mscan *m); -void mscan_interrupts_disable( mscan *m); +void mscan_interrupts_disable( volatile mscan *m); -bool mscan_set_bit_rate( mscan *m, unsigned bit_rate); +bool mscan_set_bit_rate( volatile mscan *m, unsigned bit_rate); -void mscan_initialization_mode_enter( mscan *m, mscan_context *context); +void mscan_initialization_mode_enter( volatile mscan *m, mscan_context *context); -void mscan_initialization_mode_leave( mscan *m, const mscan_context *context); +void mscan_initialization_mode_leave( volatile mscan *m, const mscan_context *context); -void mscan_sleep_mode_enter( mscan *m); +void mscan_sleep_mode_enter( volatile mscan *m); -void mscan_sleep_mode_leave( mscan *m); +void mscan_sleep_mode_leave( volatile mscan *m); -volatile uint8_t *mscan_id_acceptance_register( mscan *m, unsigned i); +volatile uint8_t *mscan_id_acceptance_register( volatile mscan *m, unsigned i); -volatile uint8_t *mscan_id_mask_register( mscan *m, unsigned i); +volatile uint8_t *mscan_id_mask_register( volatile mscan *m, unsigned i); -unsigned mscan_filter_number( mscan *m); +unsigned mscan_filter_number( volatile mscan *m); -bool mscan_set_filter_number( mscan *m, unsigned number); +bool mscan_set_filter_number( volatile mscan *m, unsigned number); -bool mscan_filter_operation( mscan *m, bool set, unsigned index, uint32_t *id, uint32_t *mask); +bool mscan_filter_operation( volatile mscan *m, bool set, unsigned index, uint32_t *id, uint32_t *mask); -void mscan_filter_clear( mscan *m); +void mscan_filter_clear( volatile mscan *m); -void mscan_get_error_counters( mscan *m, unsigned *rec, unsigned *tec); +void mscan_get_error_counters( volatile mscan *m, unsigned *rec, unsigned *tec); /** @} */ diff --git a/c/src/lib/libbsp/powerpc/gen5200/irq/irq.c b/c/src/lib/libbsp/powerpc/gen5200/irq/irq.c index f0a15d0ae8..0dc80bf523 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/irq/irq.c +++ b/c/src/lib/libbsp/powerpc/gen5200/irq/irq.c @@ -480,19 +480,38 @@ void BSP_IRQ_Benchmarking_Report( void) } #endif +static void dispatch(uint32_t irq, uint32_t offset, volatile uint32_t *maskreg) +{ + #if (ALLOW_IRQ_NESTING == 1) + uint32_t msr; + #endif + + uint32_t mask = *maskreg; + + irq += offset; + + *maskreg = mask | irqMaskTable [irq]; + + #if (ALLOW_IRQ_NESTING == 1) + msr = ppc_external_exceptions_enable(); + #endif + + bsp_interrupt_handler_dispatch(irq); + + #if (ALLOW_IRQ_NESTING == 1) + ppc_external_exceptions_disable(msr); + #endif + + *maskreg = mask; +} + /* * High level IRQ handler called from shared_raw_irq_code_entry */ int C_dispatch_irq_handler(BSP_Exception_frame *frame, unsigned excNum) { - register unsigned int irq; - register unsigned int pmce; - register unsigned int crit_pri_main_mask, - per_mask; - -#if (ALLOW_IRQ_NESTING == 1) - uint32_t msr; -#endif + uint32_t irq; + uint32_t pmce; #if (BENCHMARK_IRQ_PROCESSING == 1) uint64_t start, @@ -518,133 +537,8 @@ int C_dispatch_irq_handler(BSP_Exception_frame *frame, unsigned excNum) break; - case ASM_60X_SYSMGMT_VECTOR: - - /* get the content of main interrupt status register */ - pmce = mpc5200.pmce; - - /* main interrupts may be routed to SMI, see bit SMI/INT select - * bit in main int. priorities - */ - while (CHK_MSE_STICKY( pmce)) { - - /* check for main interrupt sources (hirarchical order) - * -> LO_int indicates peripheral sources - */ - if (CHK_MSE_STICKY( pmce)) { - /* get source of main interrupt */ - irq = MSE_SOURCE( pmce); - switch (irq) { - - /* irq1-3, RTC, GPIO, TMR0-7 detected (attention: - * slice timer 2 is always routed to SMI) - */ - case 0: /* slice timer 2 */ - case 1: - case 2: - case 3: - case 5: - case 6: - case 7: - case 8: - case 9: - case 10: - case 11: - case 12: - case 13: - case 14: - case 15: - case 16: - - /* add proper offset for main interrupts in - * the siu handler array - */ - irq += BSP_MAIN_IRQ_LOWEST_OFFSET; - - /* save original mask and disable all lower - * priorized main interrupts - */ - crit_pri_main_mask = mpc5200.crit_pri_main_mask; - mpc5200.crit_pri_main_mask |= irqMaskTable [irq]; - -#if (ALLOW_IRQ_NESTING == 1) - /* enable interrupt nesting */ - msr = ppc_external_exceptions_enable(); -#endif - - /* Dispatch interrupt handlers */ - bsp_interrupt_handler_dispatch( irq); - -#if (ALLOW_IRQ_NESTING == 1) - /* disable interrupt nesting */ - ppc_external_exceptions_disable( msr); -#endif - - /* restore original interrupt mask */ - mpc5200.crit_pri_main_mask = crit_pri_main_mask; - - break; - - /* peripheral LO_int interrupt source detected */ - case 4: - - /* check for valid peripheral interrupt source */ - if (CHK_PSE_STICKY( pmce)) { - /* get source of peripheral interrupt */ - irq = PSE_SOURCE( pmce); - - /* add proper offset for peripheral interrupts - * in the siu handler array - */ - irq += BSP_PER_IRQ_LOWEST_OFFSET; - - /* save original mask and disable all lower - * priorized main interrupts - */ - per_mask = mpc5200.per_mask; - mpc5200.per_mask |= irqMaskTable [irq]; - -#if (ALLOW_IRQ_NESTING == 1) - /* enable interrupt nesting */ - msr = ppc_external_exceptions_enable(); -#endif - - /* Dispatch interrupt handlers */ - bsp_interrupt_handler_dispatch( irq); - -#if (ALLOW_IRQ_NESTING == 1) - /* disable interrupt nesting */ - ppc_external_exceptions_disable( msr); -#endif - - /* restore original interrupt mask */ - mpc5200.per_mask = per_mask; - - /* force re-evaluation of peripheral interrupts */ - CLR_PSE_STICKY( mpc5200.pmce); - } else { - /* this case may not occur: no valid peripheral - * interrupt source - */ - printk( "No valid peripheral LO_int interrupt source\n"); - } - break; - /* error: unknown interrupt source */ - default: - printk( "Unknown peripheral LO_int interrupt source\n"); - break; - } - - /* force re-evaluation of main interrupts */ - CLR_MSE_STICKY( mpc5200.pmce); - } - - /* get the content of main interrupt status register */ - pmce = mpc5200.pmce; - } - break; - case ASM_EXT_VECTOR: + case ASM_60X_SYSMGMT_VECTOR: /* get the content of main interrupt status register */ pmce = mpc5200.pmce; @@ -682,30 +576,7 @@ int C_dispatch_irq_handler(BSP_Exception_frame *frame, unsigned excNum) /* get source of peripheral interrupt */ irq = PSE_SOURCE( pmce); - /* add proper offset for peripheral interrupts in the - * siu handler array */ - irq += BSP_PER_IRQ_LOWEST_OFFSET; - - /* save original mask and disable all lower - * priorized main interrupts */ - per_mask = mpc5200.per_mask; - mpc5200.per_mask |= irqMaskTable [irq]; - -#if (ALLOW_IRQ_NESTING == 1) - /* enable interrupt nesting */ - msr = ppc_external_exceptions_enable(); -#endif - - /* Dispatch interrupt handlers */ - bsp_interrupt_handler_dispatch( irq); - -#if (ALLOW_IRQ_NESTING == 1) - /* disable interrupt nesting */ - ppc_external_exceptions_disable( msr); -#endif - - /* restore original interrupt mask */ - mpc5200.per_mask = per_mask; + dispatch(irq, BSP_PER_IRQ_LOWEST_OFFSET, &mpc5200.per_mask); /* force re-evaluation of peripheral interrupts */ CLR_PSE_STICKY( mpc5200.pmce); @@ -734,6 +605,7 @@ int C_dispatch_irq_handler(BSP_Exception_frame *frame, unsigned excNum) /* irq1-3, RTC, GPIO, TMR0-7 detected (attention: slice timer * 2 is always routed to SMI) */ + case 0: case 1: case 2: case 3: @@ -749,30 +621,7 @@ int C_dispatch_irq_handler(BSP_Exception_frame *frame, unsigned excNum) case 14: case 15: case 16: - /* add proper offset for main interrupts in the siu - * handler array */ - irq += BSP_MAIN_IRQ_LOWEST_OFFSET; - - /* save original mask and disable all lower priorized - * main interrupts*/ - crit_pri_main_mask = mpc5200.crit_pri_main_mask; - mpc5200.crit_pri_main_mask |= irqMaskTable [irq]; - -#if (ALLOW_IRQ_NESTING == 1) - /* enable interrupt nesting */ - msr = ppc_external_exceptions_enable(); -#endif - - /* Dispatch interrupt handlers */ - bsp_interrupt_handler_dispatch( irq); - -#if (ALLOW_IRQ_NESTING == 1) - /* disable interrupt nesting */ - ppc_external_exceptions_disable( msr); -#endif - - /* restore original interrupt mask */ - mpc5200.crit_pri_main_mask = crit_pri_main_mask; + dispatch(irq, BSP_MAIN_IRQ_LOWEST_OFFSET, &mpc5200.crit_pri_main_mask); break; /* peripheral LO_int interrupt source detected */ @@ -782,30 +631,7 @@ int C_dispatch_irq_handler(BSP_Exception_frame *frame, unsigned excNum) /* get source of peripheral interrupt */ irq = PSE_SOURCE( pmce); - /* add proper offset for peripheral interrupts in the siu - * handler array */ - irq += BSP_PER_IRQ_LOWEST_OFFSET; - - /* save original mask and disable all lower priorized main - * interrupts */ - per_mask = mpc5200.per_mask; - mpc5200.per_mask |= irqMaskTable [irq]; - -#if (ALLOW_IRQ_NESTING == 1) - /* enable interrupt nesting */ - msr = ppc_external_exceptions_enable(); -#endif - - /* Dispatch interrupt handlers */ - bsp_interrupt_handler_dispatch( irq); - -#if (ALLOW_IRQ_NESTING == 1) - /* disable interrupt nesting */ - ppc_external_exceptions_disable( msr); -#endif - - /* restore original interrupt mask */ - mpc5200.per_mask = per_mask; + dispatch(irq, BSP_PER_IRQ_LOWEST_OFFSET, &mpc5200.per_mask); /* force re-evaluation of peripheral interrupts */ CLR_PSE_STICKY( mpc5200.pmce); @@ -824,6 +650,17 @@ int C_dispatch_irq_handler(BSP_Exception_frame *frame, unsigned excNum) /* force re-evaluation of main interrupts */ CLR_MSE_STICKY( mpc5200.pmce); } + + if (CHK_PSE_STICKY( pmce)) { + /* get source of peripheral interrupt */ + irq = PSE_SOURCE( pmce); + + dispatch(irq, BSP_PER_IRQ_LOWEST_OFFSET, &mpc5200.per_mask); + + /* force re-evaluation of peripheral interrupts */ + CLR_PSE_STICKY( mpc5200.pmce); + } + /* get the content of main interrupt status register */ pmce = mpc5200.pmce; } diff --git a/c/src/lib/libbsp/powerpc/gen5200/make/custom/dp2.cfg b/c/src/lib/libbsp/powerpc/gen5200/make/custom/dp2.cfg new file mode 100644 index 0000000000..0dc3eef4f8 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/gen5200/make/custom/dp2.cfg @@ -0,0 +1,7 @@ +# +# Config file for Direct Prototyping Data Processing (DP2) board. +# +# $Id$ +# + +include $(RTEMS_ROOT)/make/custom/gen5200.inc diff --git a/c/src/lib/libbsp/powerpc/gen5200/mscan/mscan-base.c b/c/src/lib/libbsp/powerpc/gen5200/mscan/mscan-base.c index e768529004..4b023577be 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/mscan/mscan-base.c +++ b/c/src/lib/libbsp/powerpc/gen5200/mscan/mscan-base.c @@ -139,7 +139,7 @@ static uint8_t prescaler_calculation( * @brief Sets the bit rate for the MSCAN module @a m to @a can_bit_rate * in [bits/s]. */ -bool mscan_set_bit_rate( mscan *m, unsigned can_bit_rate) +bool mscan_set_bit_rate( volatile mscan *m, unsigned can_bit_rate) { mscan_context context; unsigned prescale_val = 0; @@ -204,7 +204,7 @@ bool mscan_set_bit_rate( mscan *m, unsigned can_bit_rate) /** * @brief Disables all interrupts for the MSCAN module @a m. */ -void mscan_interrupts_disable( mscan *m) +void mscan_interrupts_disable( volatile mscan *m) { m->rier = 0; m->tier = 0; @@ -215,7 +215,7 @@ void mscan_interrupts_disable( mscan *m) * * Saves the current MSCAN context in @a context. */ -void mscan_initialization_mode_enter( mscan *m, mscan_context *context) +void mscan_initialization_mode_enter( volatile mscan *m, mscan_context *context) { /* Save context */ context->ctl0 = m->ctl0 & CTL0_TIME; @@ -242,7 +242,7 @@ void mscan_initialization_mode_enter( mscan *m, mscan_context *context) * * Saves the previous MSCAN context saved in @a context. */ -void mscan_initialization_mode_leave( mscan *m, const mscan_context *context) +void mscan_initialization_mode_leave( volatile mscan *m, const mscan_context *context) { /* Clear initialization mode request */ m->ctl0 &= ~CTL0_INITRQ; @@ -264,7 +264,7 @@ void mscan_initialization_mode_leave( mscan *m, const mscan_context *context) /** * @brief Enter sleep mode for the MSCAN module @a m. */ -void mscan_sleep_mode_enter( mscan *m) +void mscan_sleep_mode_enter( volatile mscan *m) { /* Request sleep mode */ m->ctl0 |= CTL0_SLPRQ; @@ -278,7 +278,7 @@ void mscan_sleep_mode_enter( mscan *m) /** * @brief Leave sleep mode for the MSCAN module @a m. */ -void mscan_sleep_mode_leave( mscan *m) +void mscan_sleep_mode_leave( volatile mscan *m) { /* Clear sleep mode request */ m->ctl0 &= ~CTL0_SLPRQ; @@ -294,7 +294,7 @@ void mscan_sleep_mode_leave( mscan *m) * * The module is set to listen only mode. */ -bool mscan_enable( mscan *m, unsigned bit_rate) +bool mscan_enable( volatile mscan *m, unsigned bit_rate) { bool s = true; @@ -327,7 +327,7 @@ bool mscan_enable( mscan *m, unsigned bit_rate) * * The module is set to sleep mode and disabled afterwards. */ -void mscan_disable( mscan *m) +void mscan_disable( volatile mscan *m) { mscan_context context; @@ -345,7 +345,7 @@ void mscan_disable( mscan *m) * @brief Sets the filter ID and mask registers of the MSCAN module @a m to * default values. */ -void mscan_filter_clear( mscan *m) +void mscan_filter_clear( volatile mscan *m) { mscan_context context; @@ -380,7 +380,7 @@ void mscan_filter_clear( mscan *m) * @see MSCAN_FILTER_NUMBER_MIN, MSCAN_FILTER_NUMBER_2, MSCAN_FILTER_NUMBER_4 * and MSCAN_FILTER_NUMBER_MAX. */ -unsigned mscan_filter_number( mscan *m) +unsigned mscan_filter_number( volatile mscan *m) { uint8_t idam = m->idac & IDAC_IDAM; @@ -403,7 +403,7 @@ unsigned mscan_filter_number( mscan *m) * @see MSCAN_FILTER_NUMBER_MIN, MSCAN_FILTER_NUMBER_2, MSCAN_FILTER_NUMBER_4 * and MSCAN_FILTER_NUMBER_MAX. */ -bool mscan_set_filter_number( mscan *m, unsigned number) +bool mscan_set_filter_number( volatile mscan *m, unsigned number) { mscan_context context; uint8_t idac = IDAC_IDAM1 | IDAC_IDAM0; @@ -442,7 +442,7 @@ bool mscan_set_filter_number( mscan *m, unsigned number) * * @warning The index @a i is not checked if it is in range. */ -volatile uint8_t *mscan_id_acceptance_register( mscan *m, unsigned i) +volatile uint8_t *mscan_id_acceptance_register( volatile mscan *m, unsigned i) { volatile uint8_t *const idar [8] = { &m->idar0, @@ -464,7 +464,7 @@ volatile uint8_t *mscan_id_acceptance_register( mscan *m, unsigned i) * * @warning The index @a i is not checked if it is in range. */ -volatile uint8_t *mscan_id_mask_register( mscan *m, unsigned i) +volatile uint8_t *mscan_id_mask_register( volatile mscan *m, unsigned i) { volatile uint8_t *const idmr [8] = { &m->idmr0, @@ -488,7 +488,7 @@ volatile uint8_t *mscan_id_mask_register( mscan *m, unsigned i) * Returns true if the operation was successful. */ bool mscan_filter_operation( - mscan *m, + volatile mscan *m, bool set, unsigned index, uint32_t *id, @@ -543,7 +543,7 @@ bool mscan_filter_operation( * @brief Returns the receiver and transmitter error counter values in @a rec * and @a tec of MSCAN module @a m. */ -void mscan_get_error_counters( mscan *m, unsigned *rec, unsigned *tec) +void mscan_get_error_counters( volatile mscan *m, unsigned *rec, unsigned *tec) { mscan_context context; diff --git a/c/src/lib/libbsp/powerpc/gen5200/network_5200/network.c b/c/src/lib/libbsp/powerpc/gen5200/network_5200/network.c index 397667f56e..61dcea40a2 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/network_5200/network.c +++ b/c/src/lib/libbsp/powerpc/gen5200/network_5200/network.c @@ -92,14 +92,12 @@ #define GET_BD_STATUS(bd) ((bd)->Status & 0xffff0000) #define GET_BD_LENGTH(bd) ((bd)->Status & 0x0000ffff) #define GET_SDMA_PENDINGBIT(Bit) \ - (mpc5200.IntPend & (uint32)(1<<Bit)) + (mpc5200.sdma.IntPend & (uint32)(1<<Bit)) #include "../bestcomm/bestcomm_api.h" #include "../bestcomm/task_api/bestcomm_cntrl.h" #include "../bestcomm/task_api/tasksetup_bdtable.h" -extern TaskBDIdxTable_t TaskBDIdxTable[MAX_TASKS]; - static TaskId rxTaskId; /* SDMA RX task ID */ static TaskId txTaskId; /* SDMA TX task ID */ @@ -673,7 +671,7 @@ void mpc5200_smartcomm_rx_irq_handler(rtems_irq_hdl_param unused) if(GET_SDMA_PENDINGBIT(FEC_RECV_TASK_NO)) { - SDMA_CLEAR_IEVENT(&mpc5200.IntPend,FEC_RECV_TASK_NO); + SDMA_CLEAR_IEVENT(&mpc5200.sdma.IntPend,FEC_RECV_TASK_NO); bestcomm_glue_irq_disable(FEC_RECV_TASK_NO);/*Disable receive ints*/ @@ -693,7 +691,7 @@ void mpc5200_smartcomm_tx_irq_handler(rtems_irq_hdl_param unused) if(GET_SDMA_PENDINGBIT(FEC_XMIT_TASK_NO)) { - SDMA_CLEAR_IEVENT(&mpc5200.IntPend,FEC_XMIT_TASK_NO); + SDMA_CLEAR_IEVENT(&mpc5200.sdma.IntPend,FEC_XMIT_TASK_NO); bestcomm_glue_irq_disable(FEC_XMIT_TASK_NO);/*Disable tx ints*/ @@ -815,7 +813,7 @@ static void mpc5200_fec_sendpacket(struct ifnet *ifp,struct mbuf *m) { /* * Clear old events */ - SDMA_CLEAR_IEVENT(&mpc5200.IntPend,FEC_XMIT_TASK_NO); + SDMA_CLEAR_IEVENT(&mpc5200.sdma.IntPend,FEC_XMIT_TASK_NO); /* * Wait for buffer descriptor to become available. @@ -983,7 +981,7 @@ static void mpc5200_fec_rxDaemon(void *arg){ /* * Clear old events */ - SDMA_CLEAR_IEVENT(&mpc5200.IntPend,FEC_RECV_TASK_NO); + SDMA_CLEAR_IEVENT(&mpc5200.sdma.IntPend,FEC_RECV_TASK_NO); /* * Get the first BD pointer and its length. */ @@ -1400,9 +1398,9 @@ static void mpc5200_fec_init(void *arg) /* * Set priority of different initiators */ - mpc5200.IPR0 = 7; /* always initiator */ - mpc5200.IPR3 = 6; /* eth rx initiator */ - mpc5200.IPR4 = 5; /* eth tx initiator */ + mpc5200.sdma.ipr [0] = 7; /* always initiator */ + mpc5200.sdma.ipr [3] = 6; /* eth rx initiator */ + mpc5200.sdma.ipr [4] = 5; /* eth tx initiator */ /* * Start driver tasks diff --git a/c/src/lib/libbsp/powerpc/gen5200/preinstall.am b/c/src/lib/libbsp/powerpc/gen5200/preinstall.am index e45d46d96e..7ecea32443 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/preinstall.am +++ b/c/src/lib/libbsp/powerpc/gen5200/preinstall.am @@ -33,6 +33,26 @@ $(PROJECT_INCLUDE)/bsp/$(dirstamp): @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp) PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp) +$(PROJECT_INCLUDE)/bsp/bestcomm/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp/bestcomm + @: > $(PROJECT_INCLUDE)/bsp/bestcomm/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/bestcomm/$(dirstamp) + +$(PROJECT_INCLUDE)/bsp/bestcomm/include/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp/bestcomm/include + @: > $(PROJECT_INCLUDE)/bsp/bestcomm/include/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/bestcomm/include/$(dirstamp) + +$(PROJECT_INCLUDE)/bsp/bestcomm/include/mgt5200/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp/bestcomm/include/mgt5200 + @: > $(PROJECT_INCLUDE)/bsp/bestcomm/include/mgt5200/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/bestcomm/include/mgt5200/$(dirstamp) + +$(PROJECT_INCLUDE)/bsp/bestcomm/task_api/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp/bestcomm/task_api + @: > $(PROJECT_INCLUDE)/bsp/bestcomm/task_api/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/bestcomm/task_api/$(dirstamp) + $(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs @@ -89,6 +109,62 @@ $(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds +$(PROJECT_INCLUDE)/bsp/bestcomm/bestcomm_priv.h: bestcomm/bestcomm_priv.h $(PROJECT_INCLUDE)/bsp/bestcomm/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bestcomm/bestcomm_priv.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bestcomm/bestcomm_priv.h + +$(PROJECT_INCLUDE)/bsp/bestcomm/dma_image.h: bestcomm/dma_image.h $(PROJECT_INCLUDE)/bsp/bestcomm/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bestcomm/dma_image.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bestcomm/dma_image.h + +$(PROJECT_INCLUDE)/bsp/bestcomm/dma_image.capi.h: bestcomm/dma_image.capi.h $(PROJECT_INCLUDE)/bsp/bestcomm/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bestcomm/dma_image.capi.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bestcomm/dma_image.capi.h + +$(PROJECT_INCLUDE)/bsp/bestcomm/bestcomm_api.h: bestcomm/bestcomm_api.h $(PROJECT_INCLUDE)/bsp/bestcomm/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bestcomm/bestcomm_api.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bestcomm/bestcomm_api.h + +$(PROJECT_INCLUDE)/bsp/bestcomm/bestcomm_glue.h: bestcomm/bestcomm_glue.h $(PROJECT_INCLUDE)/bsp/bestcomm/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bestcomm/bestcomm_glue.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bestcomm/bestcomm_glue.h + +$(PROJECT_INCLUDE)/bsp/bestcomm/include/ppctypes.h: bestcomm/include/ppctypes.h $(PROJECT_INCLUDE)/bsp/bestcomm/include/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bestcomm/include/ppctypes.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bestcomm/include/ppctypes.h + +$(PROJECT_INCLUDE)/bsp/bestcomm/include/sdma.h: bestcomm/include/mgt5200/sdma.h $(PROJECT_INCLUDE)/bsp/bestcomm/include/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bestcomm/include/sdma.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bestcomm/include/sdma.h + +$(PROJECT_INCLUDE)/bsp/bestcomm/include/mgt5200.h: bestcomm/include/mgt5200/mgt5200.h $(PROJECT_INCLUDE)/bsp/bestcomm/include/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bestcomm/include/mgt5200.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bestcomm/include/mgt5200.h + +$(PROJECT_INCLUDE)/bsp/bestcomm/include/mgt5200/mgt5200.h: bestcomm/include/mgt5200/mgt5200.h $(PROJECT_INCLUDE)/bsp/bestcomm/include/mgt5200/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bestcomm/include/mgt5200/mgt5200.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bestcomm/include/mgt5200/mgt5200.h + +$(PROJECT_INCLUDE)/bsp/bestcomm/include/mgt5200/sdma.h: bestcomm/include/mgt5200/sdma.h $(PROJECT_INCLUDE)/bsp/bestcomm/include/mgt5200/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bestcomm/include/mgt5200/sdma.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bestcomm/include/mgt5200/sdma.h + +$(PROJECT_INCLUDE)/bsp/bestcomm/task_api/tasksetup_general.h: bestcomm/task_api/tasksetup_general.h $(PROJECT_INCLUDE)/bsp/bestcomm/task_api/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bestcomm/task_api/tasksetup_general.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bestcomm/task_api/tasksetup_general.h + +$(PROJECT_INCLUDE)/bsp/bestcomm/task_api/tasksetup_bdtable.h: bestcomm/task_api/tasksetup_bdtable.h $(PROJECT_INCLUDE)/bsp/bestcomm/task_api/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bestcomm/task_api/tasksetup_bdtable.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bestcomm/task_api/tasksetup_bdtable.h + +$(PROJECT_INCLUDE)/bsp/bestcomm/task_api/bestcomm_cntrl.h: bestcomm/task_api/bestcomm_cntrl.h $(PROJECT_INCLUDE)/bsp/bestcomm/task_api/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bestcomm/task_api/bestcomm_cntrl.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bestcomm/task_api/bestcomm_cntrl.h + +$(PROJECT_INCLUDE)/bsp/bestcomm/task_api/bestcomm_api_mem.h: bestcomm/task_api/bestcomm_api_mem.h $(PROJECT_INCLUDE)/bsp/bestcomm/task_api/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bestcomm/task_api/bestcomm_api_mem.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bestcomm/task_api/bestcomm_api_mem.h + $(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h @@ -97,6 +173,10 @@ $(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INC $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h +$(PROJECT_INCLUDE)/bsp/utility.h: ../../shared/include/utility.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/utility.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/utility.h + $(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h diff --git a/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c b/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c index 289dc6d7e8..549972a4d9 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c +++ b/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c @@ -112,16 +112,16 @@ static void calc_dbat_regvals( bat_ptr->batl.pp = flg_bpp; } -#if defined (BRS5L) -void cpu_init_bsp(void) +static void cpu_init_bsp(void) { +#if defined (BRS5L) BAT dbat; calc_dbat_regvals( &dbat, (uint32_t) bsp_ram_start, (uint32_t) bsp_ram_size, - true, + false, false, false, false, @@ -133,7 +133,7 @@ void cpu_init_bsp(void) &dbat, (uint32_t) bsp_rom_start, (uint32_t) bsp_rom_size, - true, + false, false, false, false, @@ -164,10 +164,7 @@ void cpu_init_bsp(void) BPP_RW ); SET_DBAT(3,dbat.batu,dbat.batl); -} #elif defined (HAS_UBOOT) -void cpu_init_bsp(void) -{ BAT dbat; uint32_t start = 0; @@ -178,7 +175,7 @@ void cpu_init_bsp(void) &dbat, bsp_uboot_board_info.bi_memstart, bsp_uboot_board_info.bi_memsize, - true, + false, false, false, false, @@ -203,7 +200,7 @@ void cpu_init_bsp(void) &dbat, start, bsp_uboot_board_info.bi_flashsize, - true, + false, false, false, false, @@ -242,11 +239,45 @@ void cpu_init_bsp(void) ); SET_DBAT(3,dbat.batu,dbat.batl); } -} #else #warning "Using BAT register values set by environment" #endif +#if defined(BSP_TYPE_DP2) + /* Enable BAT4-7 */ + PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS(HID2, BSP_BBIT32(13)); + + /* FPGA */ + calc_dbat_regvals( + &dbat, + 0xf0020000, + 128 * 1024, + false, + true, + false, + true, + BPP_RW + ); + SET_DBAT(4, dbat.batu, dbat.batl); +#elif defined(PM520_ZE30) + /* Enable BAT4-7 */ + PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS(HID2, BSP_BBIT32(13)); + + /* External CC770 CAN controller available in version 2 */ + calc_dbat_regvals( + &dbat, + 0xf2000000, + 128 * 1024, + false, + true, + false, + true, + BPP_RW + ); + SET_DBAT(4, dbat.batu, dbat.batl); +#endif +} + void cpu_init(void) { uint32_t msr; diff --git a/c/src/lib/libbsp/powerpc/gen5200/startup/linkcmds.brs5l b/c/src/lib/libbsp/powerpc/gen5200/startup/linkcmds.brs5l index 5073165962..034aab84fa 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/startup/linkcmds.brs5l +++ b/c/src/lib/libbsp/powerpc/gen5200/startup/linkcmds.brs5l @@ -5,7 +5,7 @@ */ MEMORY { - RAM : ORIGIN = 0x0, LENGTH = 256M + RAM : ORIGIN = 0x0, LENGTH = 128M ROM : ORIGIN = 0xffe00000, LENGTH = 2M DPRAM : ORIGIN = 0xff000000, LENGTH = 1k REGS : ORIGIN = 0xf0000000, LENGTH = 64k diff --git a/c/src/lib/libbsp/powerpc/gen5200/startup/linkcmds.dp2 b/c/src/lib/libbsp/powerpc/gen5200/startup/linkcmds.dp2 new file mode 100644 index 0000000000..8288c70024 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/gen5200/startup/linkcmds.dp2 @@ -0,0 +1,15 @@ +/** + * @file + * + * Linker command file for the Direct Prototyping Data Processing board. + */ + +MEMORY { + RAM : ORIGIN = 0x0, LENGTH = 64M + ROM : ORIGIN = 0xffe00000, LENGTH = 2M + DPRAM : ORIGIN = 0xff000000, LENGTH = 1k + REGS : ORIGIN = 0xf0000000, LENGTH = 64k + NIRVANA : ORIGIN = 0x0, LENGTH = 0 +} + +INCLUDE linkcmds.base |