2010-05-20 Sebastian Huber <sebastian.huber@embedded-brains.de>

	* configure.ac: Fixed BSP option.
	* include/lpc32xx.h, startup/bspstarthooks.c: Added PLL setup.

4 files changed, 80 insertions, 1 deletions

diff --git a/c/src/lib/libbsp/arm/lpc32xx/ChangeLog b/c/src/lib/libbsp/arm/lpc32xx/ChangeLog
index 15c8264e12..d5eedd3170 100644
--- a/c/src/lib/libbsp/arm/lpc32xx/ChangeLog
+++ b/c/src/lib/libbsp/arm/lpc32xx/ChangeLog
@@ -1,5 +1,10 @@
 2010-05-20	Sebastian Huber <sebastian.huber@embedded-brains.de>
 
+	* configure.ac: Fixed BSP option.
+	* include/lpc32xx.h, startup/bspstarthooks.c: Added PLL setup.
+
+2010-05-20	Sebastian Huber <sebastian.huber@embedded-brains.de>
+
 	* startup/bspstarthooks.c: Removed start section attribute defines.
 
 2010-05-20	Sebastian Huber <sebastian.huber@embedded-brains.de>
diff --git a/c/src/lib/libbsp/arm/lpc32xx/configure.ac b/c/src/lib/libbsp/arm/lpc32xx/configure.ac
index 96691024af..41ee65fa89 100644
--- a/c/src/lib/libbsp/arm/lpc32xx/configure.ac
+++ b/c/src/lib/libbsp/arm/lpc32xx/configure.ac
@@ -63,7 +63,7 @@ RTEMS_BSPOPTS_HELP([LPC32XX_CONFIG_U6CLK],[clock configuration for UART 6])
 RTEMS_BSPOPTS_SET([LPC32XX_CONFIG_UART_CLKMODE],[*],[0x00000200U])
 RTEMS_BSPOPTS_HELP([LPC32XX_CONFIG_UART_CLKMODE],[clock mode configuration for UARTs])
 
-RTEMS_BSPOPTS_SET([LPC32XX_DISABLE_MMU],[lpc32xx_boot],[1])
+RTEMS_BSPOPTS_SET([LPC32XX_DISABLE_MMU],[lpc32xx_mzx_boot_int],[1])
 RTEMS_BSPOPTS_SET([LPC32XX_DISABLE_MMU],[*],[])
 RTEMS_BSPOPTS_HELP([LPC32XX_DISABLE_MMU],[disable MMU])
 
diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h b/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h
index 3efda3141b..8702eafb13 100644
--- a/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h
+++ b/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h
@@ -24,6 +24,8 @@
 
 #include <stdint.h>
 
+#include <bsp/utility.h>
+
 /**
  * @defgroup lpc32xx_reg Register Definitions
  *
@@ -200,6 +202,54 @@
 
 /** @} */
 
+/**
+ * @name Power Control Register (PWR_CTRL)
+ *
+ * @{
+ */
+
+#define PWR_STOP BIT32(0)
+#define PWR_HIGHCORE_ALWAYS BIT32(1)
+#define PWR_NORMAL_RUN_MODE BIT32(2)
+#define PWR_SYSCLKEN_ALWAYS BIT32(3)
+#define PWR_SYSCLKEN_HIGH BIT32(4)
+#define PWR_HIGHCORE_HIGH BIT32(5)
+#define PWR_SDRAM_AUTO_REFRESH BIT32(7)
+#define PWR_UPDATE_EMCSREFREQ BIT32(8)
+#define PWR_EMCSREFREQ BIT32(9)
+#define PWR_HCLK_USES_PERIPH_CLK BIT32(10)
+
+/** @} */
+
+/**
+ * @name HCLK PLL Control Register (HCLKPLL_CTRL)
+ *
+ * @{
+ */
+
+#define HCLK_PLL_LOCK BIT32(0)
+#define HCLK_PLL_M(val) FIELD32(val, 1, 8)
+#define HCLK_PLL_N(val) FIELD32(val, 9, 2)
+#define HCLK_PLL_P(val) FIELD32(val, 11, 2)
+#define HCLK_PLL_FBD_FCLKOUT BIT32(13)
+#define HCLK_PLL_DIRECT BIT32(14)
+#define HCLK_PLL_BYPASS BIT32(15)
+#define HCLK_PLL_POWER BIT32(16)
+
+/** @} */
+
+/**
+ * @name HCLK Divider Control Register (HCLKDIV_CTRL)
+ *
+ * @{
+ */
+
+#define HCLK_DIV_HCLK(val) FIELD32(val, 0, 2)
+#define HCLK_DIV_PERIPH_CLK(val) FIELD32(val, 2, 5)
+#define HCLK_DIV_DDRAM_CLK(val) FIELD32(val, 7, 2)
+
+/** @} */
+
 /** @} */
 
 #endif /* LIBBSP_ARM_LPC32XX_LPC32XX_H */
diff --git a/c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c b/c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c
index 93b3437569..cbe26e7866 100644
--- a/c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c
+++ b/c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c
@@ -182,8 +182,32 @@ static void BSP_START_SECTION lpc32xx_mmu_and_cache_setup(void)
   #endif
 }
 
+#if LPC32XX_OSCILLATOR_MAIN != 13000000U
+  #error "unexpected main oscillator frequency"
+#endif
+
+static void BSP_START_SECTION lpc32xx_pll_setup(void)
+{
+  uint32_t pwr_ctrl = LPC32XX_PWR_CTRL;
+
+  if ((pwr_ctrl & PWR_NORMAL_RUN_MODE) == 0) {
+    /* Enable HCLK PLL */
+    LPC32XX_HCLKPLL_CTRL = HCLK_PLL_POWER | HCLK_PLL_DIRECT | HCLK_PLL_M(16 - 1);
+    while ((LPC32XX_HCLKPLL_CTRL & HCLK_PLL_LOCK) == 0) {
+      /* Wait */
+    }
+
+    /* Setup HCLK divider */
+    LPC32XX_HCLKDIV_CTRL = HCLK_DIV_HCLK(2 - 1) | HCLK_DIV_PERIPH_CLK(16 - 1);
+
+    /* Enable HCLK PLL output */
+    LPC32XX_PWR_CTRL = pwr_ctrl | PWR_NORMAL_RUN_MODE;
+  }
+}
+
 void BSP_START_SECTION bsp_start_hook_0(void)
 {
+  lpc32xx_pll_setup();
   lpc32xx_mmu_and_cache_setup();
 }