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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2011-04-04 16:44:46 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2011-04-04 16:44:46 +0000 |
| commit | 9c24c7332c1ae6a24078449a401ae3b217a7b945 (patch) | |
| tree | d4777c56fd6d744c181e160f32ea9abd36df405b /c | |
| parent | 2011-04-04 Joel Sherrill <joel.sherrilL@OARcorp.com> (diff) | |
| download | rtems-9c24c7332c1ae6a24078449a401ae3b217a7b945.tar.bz2 | |
2011-04-04 Joel Sherrill <joel.sherrilL@OARcorp.com>
PR 1768/bsps
* shared/irq/irq_asm.S: The nbench benchmark highlighted the fact that
we do not perform a cld before calling C code in the ISR. This was
historically not a problem but gcc 4.3 changed the behavior. From
http://gcc.gnu.org/gcc-4.3/changes.html
Diffstat (limited to 'c')
| -rw-r--r-- | c/src/lib/libbsp/i386/ChangeLog | 8 | ||||
| -rw-r--r-- | c/src/lib/libbsp/i386/shared/irq/irq_asm.S | 7 |
2 files changed, 15 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/i386/ChangeLog b/c/src/lib/libbsp/i386/ChangeLog index 57ac17391a..0d1cb26c5c 100644 --- a/c/src/lib/libbsp/i386/ChangeLog +++ b/c/src/lib/libbsp/i386/ChangeLog @@ -1,3 +1,11 @@ +2011-04-04 Joel Sherrill <joel.sherrilL@OARcorp.com> + + PR 1768/bsps + * shared/irq/irq_asm.S: The nbench benchmark highlighted the fact that + we do not perform a cld before calling C code in the ISR. This was + historically not a problem but gcc 4.3 changed the behavior. From + http://gcc.gnu.org/gcc-4.3/changes.html + 2011-03-16 Jennifer Averett <jennifer.averett@OARcorp.com> PR 1729/cpukit diff --git a/c/src/lib/libbsp/i386/shared/irq/irq_asm.S b/c/src/lib/libbsp/i386/shared/irq/irq_asm.S index d899f47448..f994073f54 100644 --- a/c/src/lib/libbsp/i386/shared/irq/irq_asm.S +++ b/c/src/lib/libbsp/i386/shared/irq/irq_asm.S @@ -167,6 +167,13 @@ nested: incl PER_CPU_ISR_NEST_LEVEL(ebx) /* one nest level deeper */ incl SYM (_Thread_Dispatch_disable_level) /* disable multitasking */ + /* + * GCC versions starting with 4.3 no longer place the cld + * instruction before string operations. We need to ensure + * it is set correctly for ISR handlers. + */ + cld + /* * re-enable interrupts at processor level as the current * interrupt source is now masked via i8259 |