diff options
| author | Till Straumann <strauman@slac.stanford.edu> | 2011-07-18 16:33:39 +0000 |
|---|---|---|
| committer | Till Straumann <strauman@slac.stanford.edu> | 2011-07-18 16:33:39 +0000 |
| commit | 9515b955fedaf686bc60883c5a7447ffdbbf5ff2 (patch) | |
| tree | 2d910f8e23fcfdb49168ea1d5e13ea064379c096 /c | |
| parent | 2011-07-18 Joel Sherrill <joel.sherrill@oarcorp.com> (diff) | |
| download | rtems-9515b955fedaf686bc60883c5a7447ffdbbf5ff2.tar.bz2 | |
2011-07-18 Till Straumann <strauman@slac.stanford.edu>
* shared/startup/ppc_idle.c: Need to enable HID0[NAP] on
a 7400/7455/7457 for MSR[POW] to have an effect.
Diffstat (limited to 'c')
| -rw-r--r-- | c/src/lib/libbsp/powerpc/ChangeLog | 5 | ||||
| -rw-r--r-- | c/src/lib/libbsp/powerpc/shared/startup/ppc_idle.c | 39 |
2 files changed, 35 insertions, 9 deletions
diff --git a/c/src/lib/libbsp/powerpc/ChangeLog b/c/src/lib/libbsp/powerpc/ChangeLog index 75180fa97c..fc6cd3853f 100644 --- a/c/src/lib/libbsp/powerpc/ChangeLog +++ b/c/src/lib/libbsp/powerpc/ChangeLog @@ -1,3 +1,8 @@ +2011-07-18 Till Straumann <strauman@slac.stanford.edu> + + * shared/startup/ppc_idle.c: Need to enable HID0[NAP] on + a 7400/7455/7457 for MSR[POW] to have an effect. + 2011-07-15 Till Straumann <strauman@slac.stanford.edu> * shared/bootloader/mm.c, shared/bootloader/pci.c, diff --git a/c/src/lib/libbsp/powerpc/shared/startup/ppc_idle.c b/c/src/lib/libbsp/powerpc/shared/startup/ppc_idle.c index 88d3ae425b..f6d07774fc 100644 --- a/c/src/lib/libbsp/powerpc/shared/startup/ppc_idle.c +++ b/c/src/lib/libbsp/powerpc/shared/startup/ppc_idle.c @@ -67,20 +67,41 @@ */ #include <rtems/powerpc/registers.h> +#include <libcpu/cpuIdent.h> +#include <libcpu/spr.h> + +SPR_RW(HID0) void * bsp_ppc_idle_task_body(uintptr_t ignored) { uint32_t msr; - _CPU_MSR_GET(msr); - msr |= MSR_POW; - asm volatile( - "1: sync \n" - " mtmsr %0 \n" - " isync \n" - " b 1b \n" - ::"r"(msr) - ); + + switch ( current_ppc_cpu ) { + + case PPC_7400: + case PPC_7455: + case PPC_7457: + /* Must enable NAP mode in HID0 for MSR_POW to work */ + _write_HID0( _read_HID0() | HID0_NAP ); + break; + + default: + break; + } + + for ( ;; ) { + _CPU_MSR_GET(msr); + msr |= MSR_POW; + asm volatile( + "1: sync \n" + " mtmsr %0 \n" + " isync \n" + " b 1b \n" + ::"r"(msr) + ); + } + return 0; } |