2011-08-24 Sebastian Huber <sebastian.huber@embedded-brains.de>

	* shared/bootloader/exception.S, shared/bootloader/misc.c,
	shared/bootloader/mm.c, shared/console/polled_io.c,
	shared/startup/probeMemEnd.c: Update due to API changes.

6 files changed, 18 insertions, 16 deletions

diff --git a/c/src/lib/libbsp/powerpc/ChangeLog b/c/src/lib/libbsp/powerpc/ChangeLog
index 82944ccbec..0cfeccc4ff 100644
--- a/c/src/lib/libbsp/powerpc/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/ChangeLog
@@ -1,3 +1,9 @@
+2011-08-24	Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+	* shared/bootloader/exception.S, shared/bootloader/misc.c,
+	shared/bootloader/mm.c, shared/console/polled_io.c,
+	shared/startup/probeMemEnd.c: Update due to API changes.
+
 2011-07-27  Till Straumann <strauman@slac.stanford.edu>
 
 	* shared/start/start.S, shared/start/preload.S:
diff --git a/c/src/lib/libbsp/powerpc/shared/bootloader/exception.S b/c/src/lib/libbsp/powerpc/shared/bootloader/exception.S
index 52af8eeadb..ea1c6c7383 100644
--- a/c/src/lib/libbsp/powerpc/shared/bootloader/exception.S
+++ b/c/src/lib/libbsp/powerpc/shared/bootloader/exception.S
@@ -151,7 +151,7 @@ tlb_handlers:
 #ifdef ASSUME_REF_SET
 	andi.	r3,r1,8       # check for guarded memory
 	bne-	5f
-	mtspr	RPA,r1
+	mtspr	PPC_RPA,r1
 	mfsrr1	r3
 	tlbli	r0
 #else
@@ -167,7 +167,7 @@ both tests are combined and there is a single CR rename buffer */
 	blt-    5f            # Negative means guarded, zero R not set.
 	mfsrr1  r3            # get saved cr0 bits now to dual issue
 	ori     r1,r1,0x100
-	mtspr   RPA,r1
+	mtspr   PPC_RPA,r1
 	tlbli   r0
 /* Do not update PTE if R bit already set, this will save one cache line
 writeback at a later time, and avoid even more bus traffic in
@@ -246,14 +246,14 @@ inserted for complex cases or for statistics recording. */
 2:	lwz     r1,4(r2)      # Found:	load second word of PTE
 	mfspr   r0,DMISS      # get miss address during load delay
 #ifdef ASSUME_REF_SET
-	mtspr	RPA,r1
+	mtspr	PPC_RPA,r1
 	mfsrr1	r3
 	tlbld	r0
 #else
 	andi.   r3,r1,0x100   # check R bit ahead to help folding
 	mfsrr1  r3            # get saved cr0 bits now to dual issue
 	ori     r1,r1,0x100
-	mtspr   RPA,r1
+	mtspr   PPC_RPA,r1
 	tlbld   r0
 /* Do not update PTE if R bit already set, this will save one cache line
 writeback at a later time, and avoid even more bus traffic in
@@ -323,7 +323,7 @@ write schemes. So the protection check is ABSOLUTELY necessary. */
 	andi.   r3,r1,0x80    # check C bit
 	beq-    5f            # if (C==0) go to check protection
 3:	mfsrr1  r3            # get the saved cr0 bits
-	mtspr   RPA,r1        # set the pte
+	mtspr   PPC_RPA,r1        # set the pte
 	tlbld   r0            # load the dtlb
 	mtcrf   0x80,r3       # restore CR0
 	rfi                   # return to executing program
diff --git a/c/src/lib/libbsp/powerpc/shared/bootloader/misc.c b/c/src/lib/libbsp/powerpc/shared/bootloader/misc.c
index 9f241c27f7..25bc240b92 100644
--- a/c/src/lib/libbsp/powerpc/shared/bootloader/misc.c
+++ b/c/src/lib/libbsp/powerpc/shared/bootloader/misc.c
@@ -26,8 +26,7 @@
 #include <rtems/bspIo.h>
 #include <bsp.h>
 
-SPR_RW(DEC)
-SPR_RO(PVR)
+SPR_RO(PPC_PVR)
 
 struct inode;
 struct wait_queue;
@@ -264,7 +263,7 @@ setup_hw(void)
 	default_vga_cmd = 0;
 
 #define vpd res->VitalProductData
-	if (_read_PVR()>>16 != 1) {
+	if (_read_PPC_PVR()>>16 != 1) {
 		if ( res && vpd.ProcessorBusHz ) {
 			ticks_per_ms = vpd.ProcessorBusHz/
 			    (vpd.TimeBaseDivisor ? vpd.TimeBaseDivisor : 4000);
diff --git a/c/src/lib/libbsp/powerpc/shared/bootloader/mm.c b/c/src/lib/libbsp/powerpc/shared/bootloader/mm.c
index 219bb8e9c3..319570d7cb 100644
--- a/c/src/lib/libbsp/powerpc/shared/bootloader/mm.c
+++ b/c/src/lib/libbsp/powerpc/shared/bootloader/mm.c
@@ -95,7 +95,7 @@ typedef struct _map {
 
 SPR_RW(SDR1);
 SPR_RO(DSISR);
-SPR_RO(DAR);
+SPR_RO(PPC_DAR);
 
 /* We need a few statically allocated free maps to bootstrap the
  * memory managment */
@@ -140,7 +140,7 @@ void _handler(int vec, ctxt *p) {
 		vaddr = p->nip;
 		cause = p->msr;
 	} else { /* Valid for DSI and alignment exceptions */
-		vaddr = _read_DAR();
+		vaddr = _read_PPC_DAR();
 		cause = _read_DSISR();
 	}
 
diff --git a/c/src/lib/libbsp/powerpc/shared/console/polled_io.c b/c/src/lib/libbsp/powerpc/shared/console/polled_io.c
index 07561ff876..c486b1e127 100644
--- a/c/src/lib/libbsp/powerpc/shared/console/polled_io.c
+++ b/c/src/lib/libbsp/powerpc/shared/console/polled_io.c
@@ -373,9 +373,6 @@ unsigned int accent_table_size = 68;
 #define KBD_MODE_KCC 		0x40	/* Scan code conversion to PC format */
 #define KBD_MODE_RFU		0x80
 
-SPR_RW(DEC)
-SPR_RO(PVR)
-
 #endif /* USE_KBD_SUPPORT */
 
 /* Early messages after mm init but before console init are kept in log
diff --git a/c/src/lib/libbsp/powerpc/shared/startup/probeMemEnd.c b/c/src/lib/libbsp/powerpc/shared/startup/probeMemEnd.c
index 32b6f8afd8..11828d291b 100644
--- a/c/src/lib/libbsp/powerpc/shared/startup/probeMemEnd.c
+++ b/c/src/lib/libbsp/powerpc/shared/startup/probeMemEnd.c
@@ -110,7 +110,7 @@ extern uint32_t __rtems_end[];
 
 SPR_RW(L2CR)
 SPR_RW(L3CR)
-SPR_RO(PVR)
+SPR_RO(PPC_PVR)
 SPR_RW(HID0)
 
 
@@ -127,8 +127,8 @@ register uint32_t v, x;
 #undef  DSSALL
 	}
 	asm volatile("sync");
-	switch ( _read_PVR()>>16 ) {
-		default:		printk(__FILE__" CPU_lockUnlockCaches(): unknown CPU (PVR = 0x%08x)\n",_read_PVR());
+	switch ( _read_PPC_PVR()>>16 ) {
+		default:		printk(__FILE__" CPU_lockUnlockCaches(): unknown CPU (PVR = 0x%08x)\n",_read_PPC_PVR());
 						return -1;
 		case PPC_750:	printk("CPU_lockUnlockCaches(): Can't lock L2 on a mpc750, sorry :-(\n");
 						return -2;	/* cannot lock L2 :-( */