diff options
author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2010-06-29 00:39:44 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2010-06-29 00:39:44 +0000 |
commit | 646e7b0d2ae306a148dfa5bd9197da368b298b57 (patch) | |
tree | 7a3b6a2e6c165a43a71b115daccdde50558558ac /c | |
parent | 2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com> (diff) | |
download | rtems-646e7b0d2ae306a148dfa5bd9197da368b298b57.tar.bz2 |
2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com>
PR 1573/cpukit
* shared/score/interrupt.S: Add a per cpu data structure which contains
the information required by RTEMS for each CPU core. This
encapsulates information such as thread executing, heir, idle and
dispatch needed.
Diffstat (limited to 'c')
-rw-r--r-- | c/src/lib/libcpu/sparc64/ChangeLog | 8 | ||||
-rw-r--r-- | c/src/lib/libcpu/sparc64/shared/score/interrupt.S | 40 |
2 files changed, 13 insertions, 35 deletions
diff --git a/c/src/lib/libcpu/sparc64/ChangeLog b/c/src/lib/libcpu/sparc64/ChangeLog index 94f4c1b480..3184c16cdd 100644 --- a/c/src/lib/libcpu/sparc64/ChangeLog +++ b/c/src/lib/libcpu/sparc64/ChangeLog @@ -1,3 +1,11 @@ +2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com> + + PR 1573/cpukit + * shared/score/interrupt.S: Add a per cpu data structure which contains + the information required by RTEMS for each CPU core. This + encapsulates information such as thread executing, heir, idle and + dispatch needed. + 2010-06-17 Joel Sherrill <joel.sherrill@oarcorp.com> * .cvsignore, ChangeLog, Makefile.am, configure.ac, preinstall.am, diff --git a/c/src/lib/libcpu/sparc64/shared/score/interrupt.S b/c/src/lib/libcpu/sparc64/shared/score/interrupt.S index 34c865dd78..1540366664 100644 --- a/c/src/lib/libcpu/sparc64/shared/score/interrupt.S +++ b/c/src/lib/libcpu/sparc64/shared/score/interrupt.S @@ -26,6 +26,7 @@ */ #include <rtems/asm.h> +#include <rtems/score/percpu.h> /* @@ -178,7 +179,7 @@ PUBLIC(_ISR_Handler) setx SYM(_Thread_Dispatch_disable_level), %o5, %g3 lduw [%g3], %g5 - setx SYM(_ISR_Nest_level), %o5, %g6 + setx ISR_NEST_LEVEL, %o5, %g6 lduw [%g6], %g4 add %g5, 1, %g5 @@ -345,7 +346,7 @@ PUBLIC(_ISR_Handler) bnz simple_return ! Yes, then do a "simple" exit nop - setx SYM(_Context_Switch_necessary), %o5, %g7 + setx DISPATCH_NEEDED, %o5, %g7 /* @@ -360,21 +361,6 @@ PUBLIC(_ISR_Handler) nop /* - * Finally, check to see if signals were sent to the currently - * executing task. If so, we need to invoke the interrupt dispatcher. - */ - setx SYM(_ISR_Signals_to_thread_executing), %o5, %g5 - ldub [%g5], %o5 - - orcc %o5, %g0, %g0 ! Were signals sent to the currently - ! executing thread? - bz simple_return ! yes, then invoke the dispatcher - ! use the delay slot to clear the signals - ! to the currently executing task flag - stb %g0, [%g5] - - - /* * Invoke interrupt dispatcher. */ PUBLIC(_ISR_Dispatch) @@ -408,31 +394,15 @@ PUBLIC(_ISR_Dispatch) * _Thread_Dispatch before leaving this ISR Dispatch context. */ - setx SYM(_Context_Switch_necessary), %o5, %o1 + setx DISPATCH_NEEDED, %o5, %o1 ldub [%o1], %o2 - ! NOTE: Use some of delay slot to start loading this - setx SYM(_ISR_Signals_to_thread_executing), %o5, %o1 - ldub [%o1], %o3 - orcc %o2, %g0, %g0 ! Is thread switch necessary? - bnz dispatchAgain ! yes, then invoke the dispatcher AGAIN - ! NOTE: Use the delay slot to catch the orcc below - - /* - * Finally, check to see if signals were sent to the currently - * executing task. If so, we need to invoke the interrupt dispatcher. - */ - - ! NOTE: Delay slots above were used to perform the load AND - ! this orcc falls into the delay slot for bnz above - orcc %o3, %g0, %g0 ! Were signals sent to the currently - ! executing thread? bz allow_nest_again ! No, then clear out and return nop ! Yes, then invoke the dispatcher - dispatchAgain: +dispatchAgain: mov 3, %g4 ! syscall (enable interrupts) ta 0 ! syscall (enable interrupts) ba isr_dispatch |