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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2012-12-19 13:41:27 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2012-12-21 15:40:26 +0100 |
| commit | 566c05c896f4431f10d6cb7575eb693924bde975 (patch) | |
| tree | 2002873dce44d4aa23abaa7f0701a82b8f422d89 /c | |
| parent | libfs: Doxygen Enhancement Task #1 (diff) | |
| download | rtems-566c05c896f4431f10d6cb7575eb693924bde975.tar.bz2 | |
bsp/gen83xx: Fix CSB clock calculation for MPC8309
Diffstat (limited to 'c')
| -rw-r--r-- | c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h b/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h index c7c3d2ac14..49ababb672 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h +++ b/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h @@ -361,7 +361,12 @@ * derived values for all boards */ /* value of input clock divider (derived from pll mode reg) */ -#define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1) +#if MPC83XX_CHIP_TYPE != 8309 + #define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1) +#else + /* On the MPC8309 this bit is reserved */ + #define BSP_SYSPLL_CKID 1 +#endif /* value of system pll (derived from pll mode reg) */ #define BSP_SYSPLL_MF ((mpc83xx.clk.spmr>>(31-7))&0x0f) /* value of system pll (derived from pll mode reg) */ |