2010-12-29 Sebastian Huber <sebastian.huber@embedded-brains.de>

	* new-exceptions/bspsupport/ppc_exc_address.c,
	new-exceptions/bspsupport/ppc_exc_initialize.c: Fixed IVOR handling for
	e200z0 and e200z1.

2 files changed, 12 insertions, 4 deletions

diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_address.c b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_address.c
index 5c79df964b..c1bf1da32c 100644
--- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_address.c
+++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_address.c
@@ -57,10 +57,10 @@ static const uint8_t ivor_values [] = {
   [ASM_BOOKE_DTLBMISS_VECTOR] = 13,
   [ASM_BOOKE_ITLBMISS_VECTOR] = 14,
   [ASM_BOOKE_DEBUG_VECTOR] = 15,
-  [ASM_E500_SPE_UNAVAILABLE_VECTOR] = 32,
-  [ASM_E500_EMB_FP_DATA_VECTOR] = 33,
-  [ASM_E500_EMB_FP_ROUND_VECTOR] = 34,
-  [ASM_E500_PERFMON_VECTOR] = 35
+  [ASM_E500_SPE_UNAVAILABLE_VECTOR] = 16,
+  [ASM_E500_EMB_FP_DATA_VECTOR] = 17,
+  [ASM_E500_EMB_FP_ROUND_VECTOR] = 18,
+  [ASM_E500_PERFMON_VECTOR] = 19
 };
 
 void *ppc_exc_vector_address(unsigned vector)
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c
index 72d886f3d4..8e8cdc18d1 100644
--- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c
+++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c
@@ -38,6 +38,14 @@ static void ppc_exc_initialize_booke(void)
   /* Interupt vector prefix register */
   MTIVPR(ppc_exc_vector_base);
 
+  if (ppc_cpu_is(PPC_e200z0) || ppc_cpu_is(PPC_e200z1)) {
+    /*
+     * These cores have hard wired IVOR registers.  An access will case a
+     * program exception.
+     */
+    return;
+  }
+
   /* Interupt vector offset registers */
   MTIVOR(0,  ppc_exc_vector_address(ASM_BOOKE_CRIT_VECTOR));
   MTIVOR(1,  ppc_exc_vector_address(ASM_MACH_VECTOR));