diff options
| author | Till Straumann <strauman@slac.stanford.edu> | 2005-11-22 01:24:10 +0000 |
|---|---|---|
| committer | Till Straumann <strauman@slac.stanford.edu> | 2005-11-22 01:24:10 +0000 |
| commit | 36c30fe2e7d96ec6b8fba8e08a63e473fd8cccfe (patch) | |
| tree | 1e0c017b715b2ed7656992339df3cb01e550fa8e /c | |
| parent | 2005-11-21 Ralf Corsepius <ralf.corsepius@rtems.org> (diff) | |
| download | rtems-36c30fe2e7d96ec6b8fba8e08a63e473fd8cccfe.tar.bz2 | |
2005-11-21 Till Straumann <strauman@slac.stanford.edu>
* new-exceptions/cpu_asm.S: the book says a context
synchronizing instruction (isync) is necessary after flipping
certain bits (e.g, MSR_FP) in msr -- since this could happen as
part of a context switch I added 'isync'.
Diffstat (limited to 'c')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/ChangeLog | 7 | ||||
| -rw-r--r-- | c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S | 2 |
2 files changed, 9 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/powerpc/ChangeLog b/c/src/lib/libcpu/powerpc/ChangeLog index 37b1c5ac59..2add15fb80 100644 --- a/c/src/lib/libcpu/powerpc/ChangeLog +++ b/c/src/lib/libcpu/powerpc/ChangeLog @@ -1,3 +1,10 @@ +2005-11-21 Till Straumann <strauman@slac.stanford.edu> + + * new-exceptions/cpu_asm.S: the book says a context + synchronizing instruction (isync) is necessary after flipping + certain bits (e.g, MSR_FP) in msr -- since this could happen as + part of a context switch I added 'isync'. + 2005-11-07 Ralf Corsepius <ralf.corsepius@rtems.org> * mpc6xx/mmu/pte121.c: Eliminate unsigned32. diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S b/c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S index f4cb804eff..b1bc2b9648 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S +++ b/c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S @@ -352,6 +352,7 @@ PROC (_CPU_Context_switch): mtcrf 255, r6 mtlr r7 mtmsr r8 + isync blr @@ -375,6 +376,7 @@ PROC (_CPU_Context_restore): mtcrf 255, r5 mtlr r6 mtmsr r7 + isync lwz r1, GP_1(r3) lwz r2, GP_2(r3) #if (PPC_USE_MULTIPLE == 1) |