2010-12-30 Sebastian Huber <sebastian.huber@embedded-brains.de>

	* mpc83xx/include/mpc83xx.h, mpc83xx/network/tsec.c,
	mpc83xx/network/tsec.h: Make it possible to use the TSEC driver for
	other systems.

4 files changed, 618 insertions, 688 deletions

diff --git a/c/src/lib/libcpu/powerpc/ChangeLog b/c/src/lib/libcpu/powerpc/ChangeLog
index 4d44733ab2..f0bb32982b 100644
--- a/c/src/lib/libcpu/powerpc/ChangeLog
+++ b/c/src/lib/libcpu/powerpc/ChangeLog
@@ -1,3 +1,9 @@
+2010-12-30	Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+	* mpc83xx/include/mpc83xx.h, mpc83xx/network/tsec.c,
+	mpc83xx/network/tsec.h: Make it possible to use the TSEC driver for
+	other systems.
+
 2010-12-29	Sebastian Huber <sebastian.huber@embedded-brains.de>
 
 	* shared/include/cpuIdent.c, shared/include/cpuIdent.h: Added support
diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h b/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h
index 17cca92518..5d956d2452 100644
--- a/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h
+++ b/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h
@@ -26,14 +26,10 @@
 #error "add feature list in mpc83xx_regs.h"
 #endif
 
-/*
- * number of TSECs available
- */
-#define M83xx_TSEC_NIFACES 2
-
 #if !defined(ASM)
 
 #include <rtems.h>
+#include <bsp/tsec.h>
 
 /* Offset Register Access Reset Section/Page */
 /* System Configuration Registers */
@@ -660,290 +656,6 @@ typedef struct m83xxUSB_DRRegisters_ {
   uint8_t reserved0x2_3504[0x24000-0x23504]; /* 0x2_3504--0x2_3FFF Reserved, should be cleared */
 } m83xxUSB_DRRegisters_t;
 
-  /*
-   * this enumeration defines the index
-   * of a given rmon mib counter
-   * in the tsec_rmon_mib array
-   */
-typedef enum {
-  /* TSEC1 Transmit and Receive Counters */
-  m83xx_tsec_rmon_tr64,                    /* 0x2_4680 Transmit and receive 64-byte frame counter register R/W 0x0000_0000 15.5.3.7.1/15-60 */
-  m83xx_tsec_rmon_tr127,                   /* 0x2_4684 Transmit and receive 65- to 127-byte frame counter register R/W 0x0000_0000 15.5.3.7.2/15-61 */
-  m83xx_tsec_rmon_tr255,                   /* 0x2_4688 Transmit and receive 128- to 255-byte frame counter register R/W 0x0000_0000 15.5.3.7.3/15-61 */
-  m83xx_tsec_rmon_tr511,                   /* 0x2_468C Transmit and receive 256- to 511-byte frame counter register R/W 0x0000_0000 15.5.3.7.4/15-62 */
-  m83xx_tsec_rmon_tr1k,                    /* 0x2_4690 Transmit and receive 512- to 1023-byte frame counter register R/W 0x0000_0000 15.5.3.7.5/15-62 */
-  m83xx_tsec_rmon_trmax,                   /* 0x2_4694 Transmit and receive 1024- to 1518-byte frame counter register R/W 0x0000_0000 15.5.3.7.6/15-63 */
-  m83xx_tsec_rmon_trmgv,                   /* 0x2_4698 Transmit and receive 1519- to 1522-byte good VLAN frame count register R/W 0x0000_0000 15.5.3.7.7/15-63 */
-  /* TSEC1 Receive Counters */
-  m83xx_tsec_rmon_rbyt,                    /* 0x2_469C Receive byte counter register R/W 0x0000_0000 15.5.3.7.8/15-64 */
-  m83xx_tsec_rmon_rpkt,                    /* 0x2_46A0 Receive packet counter register R/W 0x0000_0000 15.5.3.7.9/15-64 */
-  m83xx_tsec_rmon_rfcs,                    /* 0x2_46A4 Receive FCS error counter register R/W 0x0000_0000 15.5.3.7.10/15-65 */
-  m83xx_tsec_rmon_rmca,                    /* 0x2_46A8 Receive multicast packet counter register R/W 0x0000_0000 15.5.3.7.11/15-65 */
-  m83xx_tsec_rmon_rbca,                    /* 0x2_46AC Receive broadcast packet counter register R/W 0x0000_0000 15.5.3.7.12/15-66 */
-  m83xx_tsec_rmon_rxcf,                    /* 0x2_46B0 Receive control frame packet counter register R/W 0x0000_0000 15.5.3.7.13/15-66 */
-  m83xx_tsec_rmon_rxpf,                    /* 0x2_46B4 Receive PAUSE frame packet counter register R/W 0x0000_0000 15.5.3.7.14/15-67 */
-  m83xx_tsec_rmon_rxuo,                    /* 0x2_46B8 Receive unknown OP code counter register R/W 0x0000_0000 15.5.3.7.15/15-67 */
-  m83xx_tsec_rmon_raln,                    /* 0x2_46BC Receive alignment error counter register R/W 0x0000_0000 15.5.3.7.16/15-68 */
-  m83xx_tsec_rmon_rflr,                    /* 0x2_46C0 Receive frame length error counter register R/W 0x0000_0000 15.5.3.7.17/15-68 */
-  m83xx_tsec_rmon_rcde,                    /* 0x2_46C4 Receive code error counter register R/W 0x0000_0000 15.5.3.7.18/15-69 */
-  m83xx_tsec_rmon_rcse,                    /* 0x2_46C8 Receive carrier sense error counter register R/W 0x0000_0000 15.5.3.7.19/15-69 */
-  m83xx_tsec_rmon_rund,                    /* 0x2_46CC Receive undersize packet counter register R/W 0x0000_0000 15.5.3.7.20/15-70 */
-  m83xx_tsec_rmon_rovr,                    /* 0x2_46D0 Receive oversize packet counter register R/W 0x0000_0000 15.5.3.7.21/15-70 */
-  m83xx_tsec_rmon_rfrg,                    /* 0x2_46D4 Receive fragments counter register R/W 0x0000_0000 15.5.3.7.22/15-71 */
-  m83xx_tsec_rmon_rjbr,                    /* 0x2_46D8 Receive jabber counter register R/W 0x0000_0000 15.5.3.7.23/15-71 */
-  m83xx_tsec_rmon_rdrp,                    /* 0x2_46DC Receive drop register R/W 0x0000_0000 15.5.3.7.24/15-72 */
-  /* TSEC1 Transmit Counters */
-  m83xx_tsec_rmon_tbyt,                    /* 0x2_46E0 Transmit byte counter register R/W 0x0000_0000 15.5.3.7.25/15-72 */
-  m83xx_tsec_rmon_tpkt,                    /* 0x2_46E4 Transmit packet counter register R/W 0x0000_0000 15.5.3.7.26/15-73 */
-  m83xx_tsec_rmon_tmca,                    /* 0x2_46E8 Transmit multicast packet counter register R/W 0x0000_0000 15.5.3.7.27/15-73 */
-  m83xx_tsec_rmon_tbca,                    /* 0x2_46EC Transmit broadcast packet counter register R/W 0x0000_0000 15.5.3.7.28/15-74 */
-  m83xx_tsec_rmon_txpf,                    /* 0x2_46F0 Transmit PAUSE control frame counter register R/W 0x0000_0000 15.5.3.7.29/15-74 */
-  m83xx_tsec_rmon_tdfr,                    /* 0x2_46F4 Transmit deferral packet counter register R/W 0x0000_0000 15.5.3.7.30/15-75 */
-  m83xx_tsec_rmon_tedf,                    /* 0x2_46F8 Transmit excessive deferral packet counter register R/W 0x0000_0000 15.5.3.7.31/15-75 */
-  m83xx_tsec_rmon_tscl,                    /* 0x2_46FC Transmit single collision packet counter register R/W 0x0000_0000 15.5.3.7.32/15-76 */
-  m83xx_tsec_rmon_tmcl,                    /* 0x2_4700 Transmit multiple collision packet counter register R/W 0x0000_0000 15.5.3.7.33/15-76 */
-  m83xx_tsec_rmon_tlcl,                    /* 0x2_4704 Transmit late collision packet counter register R/W 0x0000_0000 15.5.3.7.34/15-77 */
-  m83xx_tsec_rmon_txcl,                    /* 0x2_4708 Transmit excessive collision packet counter register R/W 0x0000_0000 15.5.3.7.35/15-77 */
-  m83xx_tsec_rmon_tncl,                    /* 0x2_470C Transmit total collision counter register R/W 0x0000_0000 15.5.3.7.36/15-78 */
-  m83xx_tsec_reserved1,                    /* 0x2_4710 Reserved, should be cleared R 0x0000_0000  */
-  m83xx_tsec_rmon_tdrp,                    /* 0x2_4714 Transmit drop frame counter register R/W 0x0000_0000 15.5.3.7.37/15-78 */
-  m83xx_tsec_rmon_tjbr,                    /* 0x2_4718 Transmit jabber frame counter register R/W 0x0000_0000 15.5.3.7.38/15-79 */
-  m83xx_tsec_rmon_tfcs,                    /* 0x2_471C Transmit FCS error counter register R/W 0x0000_0000 15.5.3.7.39/15-79 */
-  m83xx_tsec_rmon_txcf,                    /* 0x2_4720 Transmit control frame counter register R/W 0x0000_0000 15.5.3.7.40/15-80 */
-  m83xx_tsec_rmon_tovr,                    /* 0x2_4724 Transmit oversize frame counter register R/W 0x0000_0000 15.5.3.7.41/15-80 */
-  m83xx_tsec_rmon_tund,                    /* 0x2_4728 Transmit undersize frame counter register R/W 0x0000_0000 15.5.3.7.42/15-81 */
-  m83xx_tsec_rmon_tfrg,                    /* 0x2_472C Transmit fragments frame counter register R/W 0x0000_0000 15.5.3.7.43/15-81 */
-  m83xx_tsec_rmon_cnt
-} m83xx_tsec_rmon_idx_t;
-
-  /* TSEC1/2 General Control and Status Registers */
-typedef struct m83xxTSEC_Registers_ {
-  uint8_t reserved0x2_4000[0x24010-0x24000]; /* 0x2_4000--0x2_400F Reserved, should be cleared */
-  volatile uint32_t ievent;                  /* 0x2_4010 Interrupt event register R/W 0x0000_0000 15.5.3.1.1/15-19 */
-  volatile uint32_t imask;                   /* 0x2_4014 Interrupt mask register R/W 0x0000_0000 15.5.3.1.2/15-22 */
-  volatile uint32_t edis;                    /* 0x2_4018 Error disabled register R/W 0x0000_0000 15.5.3.1.3/15-24 */
-  uint8_t reserved0x2_401c[0x24020-0x2401c]; /* 0x2_401c--0x2_401f Reserved, should be cleared */
-  volatile uint32_t ecntrl;                  /* 0x2_4020 Ethernet control register R/W 0x0000_0000 15.5.3.1.4/15-25 */
-  volatile uint32_t minflr;                  /* 0x2_4024 Minimum frame length register R/W 0x0000_0040 15.5.3.1.5/15-26 */
-  volatile uint32_t ptv;                     /* 0x2_4028 Pause time value register R/W 0x0000_0000 15.5.3.1.6/15-27 */
-  volatile uint32_t dmactrl;                 /* 0x2_402C DMA control register R/W 0x0000_0000 15.5.3.1.7/15-28 */
-  volatile uint32_t tbipa;                   /* 0x2_4030 TBI PHY address register R/W 0x0000_0000 15.5.3.1.8/15-29 */
-  uint8_t reserved0x2_4034[0x2408c-0x24034]; /* 0x2_4034--0x2_408b Reserved, should be cleared */
-  /* TSEC1 FIFO Control and Status Registers */
-  volatile uint32_t fifo_tx_thr;             /* 0x2_408C FIFO transmit threshold register R/W 0x0000_0100 15.5.3.2.1/15-30 */
-  uint8_t reserved0x2_4090[0x24094-0x24090]; /* 0x2_4090--0x2_4093 Reserved, should be cleared */
-  volatile uint32_t fifo_tx_sp;              /* 0x2_4094 FIFO transmit space available register R/W 0x0000_0010 15.5.3.2.2/15-31 */
-  volatile uint32_t fifo_tx_starve;          /* 0x2_4098 FIFO transmit starve register R/W 0x0000_0080 15.5.3.2.3/15-31 */
-  volatile uint32_t fifo_tx_starve_shutoff;  /* 0x2_409C FIFO transmit starve shutoff register R/W 0x0000_0100 15.5.3.2.4/15-32 */
-  uint8_t reserved0x2_40A0[0x24100-0x240A0]; /* 0x2_40A0--0x2_40ff Reserved, should be cleared */
-  /* TSEC1 Transmit Control and Status Registers */
-  volatile uint32_t tctrl;                   /* 0x2_4100 Transmit control register R/W 0x0000_0000 15.5.3.3.1/15-33 */
-  volatile uint32_t tstat;                   /* 0x2_4104 Transmit status register R/W 0x0000_0000 15.5.3.3.2/15-34 */
-  uint8_t reserved0x2_4108[0x24110-0x24108]; /* 0x2_4108 Reserved, should be cleared R 0x0000_0000 */
-  volatile uint32_t txic;                    /* 0x2_4110 Transmit interrupt coalescing configuration register R/W 0x0000_0000 */
-  uint8_t reserved0x2_4114[0x24124-0x24114]; /* 0x2_4114--0x2_4120 Reserved, should be cleared */
-  volatile uint32_t ctbptr;                  /* 0x2_4124 Current TxBD pointer register R 0x0000_0000 15.5.3.3.5/15-36 */
-  uint8_t reserved0x2_4128[0x24184-0x24128]; /* 0x2_4128--0x2_4180 Reserved, should be cleared */
-  volatile uint32_t tbptr;                   /* 0x2_4184 TxBD pointer register R/W 0x0000_0000 15.5.3.3.6/15-36 */
-  uint8_t reserved0x2_4188[0x24204-0x24188]; /* 0x2_4188--0x2_4200 Reserved, should be cleared */
-  volatile uint32_t tbase;                   /* 0x2_4204 TxBD base address register R/W 0x0000_0000 15.5.3.3.7/15-37 */
-  uint8_t reserved0x2_4208[0x242B0-0x24208]; /* 0x2_4208--0x2_42AC Reserved, should be cleared */
-  volatile uint32_t ostbd;                   /* 0x2_42B0 Out-of-sequence TxBD register R/W 0x0800_0000 15.5.3.3.8/15-37 */
-  volatile uint32_t ostbdp;                  /* 0x2_42B4 Out-of-sequence Tx data buffer pointer register R/W 0x0000_0000 15.5.3.3.9/15-39 */
-  uint8_t reserved0x2_42B8[0x24300-0x242B8]; /* 0x2_42B8--0x2_42FC Reserved, should be cleared */
-  /* TSEC1 Receive Control and Status Registers */
-  volatile uint32_t rctrl;                   /* 0x2_4300 Receive control register R/W 0x0000_0000 15.5.3.4.1/15-40 */
-  volatile uint32_t rstat;                   /* 0x2_4304 Receive status register R/W 0x0000_0000 15.5.3.4.2/15-41 */
-  uint8_t reserved0x2_4308[0x2430C-0x24308]; /* 0x2_4308 Reserved, should be cleared R 0x0000_0000  */
-  volatile uint32_t rbdlen;                  /* 0x2_430C RxBD data length register R 0x0000_0000 15.5.3.4.3/15-41 */
-  volatile uint32_t rxic;                    /* 0x2_4310 Receive interrupt coalescing configuration register R/W 0x0000_0000 15.5.3.4.4/15-42 */
-  uint8_t reserved0x2_4314[0x24324-0x24314]; /* 0x2_4314--0x2_4320 Reserved, should be cleared */
-  volatile uint32_t crbptr;                  /* 0x2_4324 Current RxBD pointer register R 0x0000_0000 15.5.3.4.5/15-43 */
-  uint8_t reserved0x2_4328[0x24340-0x24328]; /* 0x2_4328--0x2_433C Reserved, should be cleared */
-  volatile uint32_t mrblr;                   /* 0x2_4340 Maximum receive buffer length register R/W 0x0000_0000 15.5.3.4.6/15-43 */
-  uint8_t reserved0x2_4344[0x24384-0x24344]; /* 0x2_4344--0x2_4380 Reserved, should be cleared */
-  volatile uint32_t rbptr;                   /* 0x2_4384 RxBD pointer register R/W 0x0000_0000 15.5.3.4.7/15-44 */
-  uint8_t reserved0x2_4388[0x24404-0x24388]; /* 0x2_4388--0x2_4400 Reserved, should be cleared */
-  volatile uint32_t rbase;                   /* 0x2_4404 RxBD base address register R/W 0x0000_0000 15.5.3.4.8/15-44 */
-  uint8_t reserved0x2_4408[0x24500-0x24408]; /* 0x2_4408--0x2_44FC Reserved, should be cleared */
-  /* TSEC1 MAC Registers */
-  volatile uint32_t maccfg1;                 /* 0x2_4500 MAC configuration register 1 R/W, R 0x0000_0000 15.5.3.6.1/15-48 */
-  volatile uint32_t maccfg2;                 /* 0x2_4504 MAC configuration register 2 R/W 0x0000_7000 15.5.3.6.2/15-49 */
-  volatile uint32_t ipgifg;                  /* 0x2_4508 Inter-packet gap/inter-frame gap register R/W 0x4060_5060 15.5.3.6.3/15-51 */
-  volatile uint32_t hafdup;                  /* 0x2_450C Half-duplex register R/W 0x00A1_F037 15.5.3.6.4/15-52 */
-  volatile uint32_t maxfrm;                  /* 0x2_4510 Maximum frame length register R/W 0x0000_0600 15.5.3.6.5/15-53 */
-  uint8_t reserved0x2_4514[0x24520-0x24514]; /* 0x2_4514--0x2_451C Reserved, should be cleared */
-  volatile uint32_t miimcfg;                 /* 0x2_4520 MII management configuration register R/W 0x0000_0000 15.5.3.6.6/15-53 */
-  volatile uint32_t miimcom;                 /* 0x2_4524 MII management command register R/W 0x0000_0000 15.5.3.6.7/15-54 */
-  volatile uint32_t miimadd;                 /* 0x2_4528 MII management address register R/W 0x0000_0000 15.5.3.6.8/15-55 */
-  volatile uint32_t miimcon;                 /* 0x2_452C MII management control register W 0x0000_0000 15.5.3.6.9/15-56 */
-  volatile uint32_t miimstat;                /* 0x2_4530 MII management status register R 0x0000_0000 15.5.3.6.10/15-56 */
-  volatile uint32_t miimind;                 /* 0x2_4534 MII management indicator register R 0x0000_0000 15.5.3.6.11/15-57 */
-  uint8_t reserved0x2_4538[0x2453c-0x24538]; /* 0x2_4538 Reserved, should be cleared  $ $ */
-  volatile uint32_t ifstat;                  /* 0x2_453C Interface status register Special 0x0000_0001 15.5.3.6.12/15-58 */
-  volatile uint32_t macstnaddr[2];             /* 0x2_4540 Station address register, part 1/2 R/W 0x0000_0000 15.5.3.6.13/15-58 */
-  uint8_t reserved0x2_4548[0x24680-0x24548]; /* 0x2_4548--0x2_467C Reserved, should be cleared */
-
-  /* TSEC1 RMON MIB Registers */
-  volatile uint32_t rmon_mib[m83xx_tsec_rmon_cnt];
-
-  /* TSEC1 General Registers */
-  volatile uint32_t car[2];                  /* 0x2_4730 Carry register one/two register R 0x0000_0000 15.5.3.7.44/15-82 */
-  volatile uint32_t cam[2];                  /* 0x2_4738 Carry register one/two mask register R/W 0xFE01_FFFF 15.5.3.7.46/15-85 */
-  uint8_t reserved0x2_4740[0x24800-0x24740]; /* 0x2_4740--0x2_47FC Reserved, should be cleared */
-
-  /* TSEC1 Hash Function Registers */
-  volatile uint32_t iaddr[8];                /* 0x2_4800 Individual address register 0-7 R/W 0x0000_0000 15.5.3.8.1/15-87 */
-  uint8_t reserved0x2_4820[0x24880-0x24820]; /* 0x2_4820--0x2_487C Reserved, should be cleared */
-  volatile uint32_t gaddr[8];                /* 0x2_4880 Group address register 0-7 R/W 0x0000_0000 15.5.3.8.2/15-88 */
-  uint8_t reserved0x2_48A0[0x24B00-0x248A0]; /* 0x2_48A0--0x2_4AFF Reserved, should be cleared */
-
-  /* TSEC1 Attribute Registers */
-  uint8_t reserved0x2_4B00[0x24BF8-0x24B00]; /* 0x2_4B00--0x2_4BF4 Reserved, should be cleared */
-  volatile uint32_t attr;                    /* 0x2_4BF8 Attribute register R 0x0000_0000 */
-  volatile uint32_t attreli;                 /* 0x2_4BFC Attribute extract length and extract index register R/W 0x0000_0000 */
-  uint8_t reserved0x2_4C00[0x25000-0x24C00]; /* 0x2_4C00--0x2_4FFF Reserved, should be cleared */
-} m83xxTSEC_Registers_t;
-
-
-/*
- * TSEC IEVENT/IMASK bit definitions
- */
-#define M83xx_TSEC_IEVENT_BABR      (1<<(31- 0))
-#define M83xx_TSEC_IEVENT_RXC       (1<<(31- 1))
-#define M83xx_TSEC_IEVENT_BSY       (1<<(31- 2))
-#define M83xx_TSEC_IEVENT_EBERR     (1<<(31- 3))
-#define M83xx_TSEC_IEVENT_MSRO      (1<<(31- 5))
-#define M83xx_TSEC_IEVENT_GTSC      (1<<(31- 6))
-#define M83xx_TSEC_IEVENT_BABT      (1<<(31- 7))
-#define M83xx_TSEC_IEVENT_TXC       (1<<(31- 8))
-#define M83xx_TSEC_IEVENT_TXE       (1<<(31- 9))
-#define M83xx_TSEC_IEVENT_TXB       (1<<(31-10))
-#define M83xx_TSEC_IEVENT_TXF       (1<<(31-11))
-#define M83xx_TSEC_IEVENT_LC        (1<<(31-13))
-#define M83xx_TSEC_IEVENT_CRL_XDA   (1<<(31-14))
-#define M83xx_TSEC_IEVENT_XFUN      (1<<(31-15))
-#define M83xx_TSEC_IEVENT_RXB       (1<<(31-16))
-#define M83xx_TSEC_IEVENT_MMRD      (1<<(31-21))
-#define M83xx_TSEC_IEVENT_MMWR      (1<<(31-22))
-#define M83xx_TSEC_IEVENT_GRSC      (1<<(31-23))
-#define M83xx_TSEC_IEVENT_RXF       (1<<(31-24))
-
-/*
- * TSEC DMACTRL bit definitions
- */
-#define M83xx_TSEC_DMACTL_TDSEN  (1<<(31-24))
-#define M83xx_TSEC_DMACTL_TBDSEN (1<<(31-25))
-#define M83xx_TSEC_DMACTL_GRS    (1<<(31-27))
-#define M83xx_TSEC_DMACTL_GTS    (1<<(31-28))
-#define M83xx_TSEC_DMACTL_WWR    (1<<(31-30))
-#define M83xx_TSEC_DMACTL_WOP    (1<<(31-31))
-
-/*
- * TSEC TSTAT bit definitions
- */
-#define M83xx_TSEC_TSTAT_THLT  (1<<(31-0))
-
-/*
- * TSEC RSTAT bit definitions
- */
-#define M83xx_TSEC_RSTAT_QHLT  (1<<(31-8))
-  /*
-   * TSEC ECNTRL bit positions
-   */
-#define M83xx_TSEC_ECNTRL_CLRCNT (1 << (31-17))  /* Clear stat counters     */
-#define M83xx_TSEC_ECNTRL_AUTOZ  (1 << (31-18))  /* auto-zero read counters */
-#define M83xx_TSEC_ECNTRL_STEN   (1 << (31-19))  /* enable statistics       */
-#define M83xx_TSEC_ECNTRL_TBIM   (1 << (31-26))  /* ten-bit-interface       */
-#define M83xx_TSEC_ECNTRL_RPM    (1 << (31-27))  /* reduced signal mode     */
-#define M83xx_TSEC_ECNTRL_R100M  (1 << (31-28))  /* RGMII100 mode           */
-  /*
-   * TSEC EDIS bit positions
-   */
-#define M83xx_TSEC_EDIS_BSYDIS    (1 << (31- 2))  /* Busy disable            */
-#define M83xx_TSEC_EDIS_EBERRDIS  (1 << (31- 3))  /* bus error disable       */
-#define M83xx_TSEC_EDIS_TXEDIS    (1 << (31- 9))  /* Tx error disable        */
-#define M83xx_TSEC_EDIS_LCDIS     (1 << (31-13))  /* Late collision disable  */
-#define M83xx_TSEC_EDIS_CRLXDADIS (1 << (31-14))  /* Collision Retry disable */
-#define M83xx_TSEC_EDIS_FUNDIS    (1 << (31-15))  /* Tx FIFO underrun disable*/
-
-  /*
-   * TSEC RCTRL bit positions
-   */
-#define M83xx_TSEC_RCTRL_BC_REJ  (1 << (31-27))  /* Broadcast Reject        */
-#define M83xx_TSEC_RCTRL_PROM    (1 << (31-28))  /* Promiscuous             */
-#define M83xx_TSEC_RCTRL_RSF     (1 << (31-29))  /* Receive short frames    */
-
-  /*
-   * TSEC TXIC bit positions
-   */
-#define M83xx_TSEC_TXIC_ICEN      (1 << (31- 0))  /* Irq coalescing enable   */
-#define M83xx_TSEC_TXIC_ICFCT(n) (((n)&0xff) << (31-10))  /* Frame coal. cnt */
-#define M83xx_TSEC_TXIC_ICTT(n) (((n)&0xffff) << (31-31))  /* Buf. coal. cnt */
-
-  /*
-   * TSEC RXIC bit positions
-   */
-#define M83xx_TSEC_RXIC_ICEN      (1 << (31- 0))  /* Irq coalescing enable   */
-#define M83xx_TSEC_RXIC_ICFCT(n) (((n)&0xff) << (31-10))  /* Frame coal. cnt */
-#define M83xx_TSEC_RXIC_ICTT(n) (((n)&0xffff) << (31-31))  /* Buf. coal. cnt */
-
-  /*
-   * TSEC MACCFG1 bit positions
-   */
-#define M83xx_TSEC_MACCFG1_SOFTRST   (1 << (31- 0))  /* Soft Reset           */
-#define M83xx_TSEC_MACCFG1_RES_RXMC  (1 << (31-12))  /* Reset Rx MAC block   */
-#define M83xx_TSEC_MACCFG1_RES_TXMC  (1 << (31-13))  /* Reset Tx MAC block   */
-#define M83xx_TSEC_MACCFG1_RES_RXFUN (1 << (31-14))  /* Reset Rx function blk*/
-#define M83xx_TSEC_MACCFG1_RES_TXFUN (1 << (31-15))  /* Reset Tx function blk*/
-#define M83xx_TSEC_MACCFG1_LOOPBACK  (1 << (31-23))  /* Loopback mode        */
-#define M83xx_TSEC_MACCFG1_RX_FLOW   (1 << (31-26))  /* Receive Flow Ctrl    */
-#define M83xx_TSEC_MACCFG1_TX_FLOW   (1 << (31-27))  /* Transmit Flow Ctrl   */
-#define M83xx_TSEC_MACCFG1_SYNVRXEN  (1 << (31-28))  /* Sync Receive Enable  */
-#define M83xx_TSEC_MACCFG1_RXEN      (1 << (31-29))  /* Receive Enable       */
-#define M83xx_TSEC_MACCFG1_SYNVTXEN  (1 << (31-30))  /* Sync Transmit Enable */
-#define M83xx_TSEC_MACCFG1_TXEN      (1 << (31-31))  /* Transmit Enable      */
-
-  /*
-   * TSEC MACCFG2 bit positions
-   */
-#define M83xx_TSEC_MACCFG2_PRELEN(n) (((n)&0x0f) << (31-19))  /* Preamble len*/
-
-#define M83xx_TSEC_MACCFG2_IFMODE_MSK (3 << (31-23)) /* mode mask            */
-#define M83xx_TSEC_MACCFG2_IFMODE_NIB (1 << (31-23)) /* nibble mode          */
-#define M83xx_TSEC_MACCFG2_IFMODE_BYT (2 << (31-23)) /* byte mode            */
-
-#define M83xx_TSEC_MACCFG2_HUGE_FRAME (1 << (31-26)) /* Huge Frame           */
-#define M83xx_TSEC_MACCFG2_LENGTH_CHK (1 << (31-27)) /* Length Check         */
-#define M83xx_TSEC_MACCFG2_PAD_CRC    (1 << (31-29)) /* MAC adds PAD/CRC     */
-#define M83xx_TSEC_MACCFG2_CRC_EN     (1 << (31-30)) /* CRC enable           */
-#define M83xx_TSEC_MACCFG2_FULLDUPLEX (1 << (31-31)) /* Full Duplex Mode     */
-
-  /*
-   * TSEC MIIMADD bit positions
-   */
-#define M83xx_TSEC_MIIMADD_PHY(n)     (((n) & 0x3f)<<(31- 23))  /* PHY addr  */
-#define M83xx_TSEC_MIIMADD_REGADDR(n) (((n) & 0x3f)<<(31- 31))  /* PHY addr  */
-
-  /*
-   * TSEC MIIMCOM bit positions
-   */
-#define M83xx_TSEC_MIIMCOM_SCAN       (1 << (31-30))     /* Scan command     */
-#define M83xx_TSEC_MIIMCOM_READ       (1 << (31-31))     /* Read command     */
-
-  /*
-   * TSEC MIIMIND bit positions
-   */
-#define M83xx_TSEC_MIIMIND_NVAL       (1 << (31-29))     /* not valid        */
-#define M83xx_TSEC_MIIMIND_SCAN       (1 << (31-30))     /* Scan in progress */
-#define M83xx_TSEC_MIIMIND_BUSY       (1 << (31-31))     /* Acc. in progress */
-
-  /*
-   * TSEC ATTR bit positions
-   */
-#define M83xx_TSEC_ATTR_RDSEN         (1 << (31-24))     /* read data snoop  */
-#define M83xx_TSEC_ATTR_RBDSEN        (1 << (31-25))     /* read BD snoop    */
-
 #if 0 /* FIXME: to be formatted soon */
   /* Security Engine Address Map Registers */
   /* Controller Registers */
@@ -1107,7 +819,7 @@ typedef struct m83xxRegisters_ {
   uint8_t                 reserved0_8700[0x22000-0x8700];
   m83xxUSB_MPHRegisters_t usb_mph;
   m83xxUSB_DRRegisters_t  usb_dr;
-  m83xxTSEC_Registers_t   tsec[M83xx_TSEC_NIFACES];
+  volatile tsec_registers tsec[TSEC_COUNT];
 } m83xxRegisters_t;
 
 extern m83xxRegisters_t mpc83xx;
@@ -1268,50 +980,4 @@ extern m83xxRegisters_t mpc83xx;
 #define RCWHR_LDP_PAR     (0 << (31-30))   /* LDP0-3 are parity pins  */
 #define RCWHR_LDP_SPC     (1 << (31-30))   /* LDP0-3 are special pins */
 
-
-#if !defined(ASM)
-typedef struct PQ_BufferDescriptor_ {
-  volatile uint16_t  status;
-  volatile uint16_t  length;
-  volatile void     *buffer;
-} PQBufferDescriptor_t;
-#endif
-
-/*
- * Bits in receive buffer descriptor status word
- */
-#define M83xx_BD_EMPTY           (1<<15)
-#define M83xx_BD_RO1             (1<<14)
-#define M83xx_BD_WRAP            (1<<13)
-#define M83xx_BD_INTERRUPT       (1<<12)
-#define M83xx_BD_LAST            (1<<11)
-#define M83xx_BD_CONTROL_CHAR    (1<<11)
-#define M83xx_BD_FIRST_IN_FRAME  (1<<10)
-#define M83xx_BD_MISS            (1<<8)
-#define M83xx_BD_BROADCAST       (1<<7)
-#define M83xx_BD_MULTICAST       (1<<6)
-#define M83xx_BD_LONG            (1<<5)
-#define M83xx_BD_NONALIGNED      (1<<4)
-#define M83xx_BD_SHORT           (1<<3)
-#define M83xx_BD_CRC_ERROR       (1<<2)
-#define M83xx_BD_OVERRUN         (1<<1)
-#define M83xx_BD_COLLISION       (1<<0)
-
-/*
- * Bits in transmit buffer descriptor status word
- * Many bits have the same meaning as those in receiver buffer descriptors.
- */
-#define M83xx_BD_READY           (1<<15)
-#define M83xx_BD_PAD_CRC         (1<<14)
-/* WRAP/Interrupt as in Rx BDs */
-#define M83xx_BD_TX_CRC          (1<<10)
-#define M83xx_BD_DEFER           (1<<9)
-#define M83xx_BD_TO1             (1<<8)
-#define M83xx_BD_HFE_            (1<<7)
-#define M83xx_BD_LATE_COLLISION  (1<<7)
-#define M83xx_BD_RETRY_LIMIT     (1<<6)
-#define M83xx_BD_RETRY_COUNT(x)  (((x)&0x3C)>>2)
-#define M83xx_BD_UNDERRUN        (1<<1)
-#define M83xx_BD_TXTRUNC         (1<<0)
-
 #endif /* _MPC83XX_MPC83XX_H */
diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.c b/c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.c
index dd3c28ea27..755a123078 100644
--- a/c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.c
+++ b/c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.c
@@ -25,8 +25,7 @@
 #include <stdlib.h>
 #include <bsp.h>
 #include <bsp/irq.h>
-#include <mpc83xx/mpc83xx.h>
-#include <mpc83xx/tsec.h>
+#include <bsp/tsec.h>
 #include <libcpu/spr.h>
 #include <rtems/error.h>
 #include <rtems/bspIo.h>
@@ -58,15 +57,15 @@ SPR_RO( PVR)
 /*
  * Device data
  */
-struct mpc83xx_tsec_struct {
+struct tsec_struct {
   struct arpcom           arpcom;
   int                     acceptBroadcast;
 
   /*
    * HW links: (filled from rtems_bsdnet_ifconfig
    */
-  m83xxTSEC_Registers_t  *reg_ptr;    /* pointer to TSEC register block */
-  m83xxTSEC_Registers_t  *mdio_ptr;   /* pointer to TSEC register block which is responsible for MDIO communication */
+  volatile tsec_registers *reg_ptr;   /* pointer to TSEC register block */
+  volatile tsec_registers *mdio_ptr;  /* pointer to TSEC register block which is responsible for MDIO communication */
   int                    irq_num_tx;  /* tx irq number                  */
   int                    irq_num_rx;  /* rx irq number                  */
   int                    irq_num_err; /* error irq number               */
@@ -111,7 +110,7 @@ struct mpc83xx_tsec_struct {
   unsigned long           txErrors;
   };
 
-static struct mpc83xx_tsec_struct tsec_driver[M83xx_TSEC_NIFACES];
+static struct tsec_struct tsec_driver[TSEC_COUNT];
 
 /*
  * default numbers for buffers
@@ -122,33 +121,33 @@ static struct mpc83xx_tsec_struct tsec_driver[M83xx_TSEC_NIFACES];
 /*
  * mask for all Tx interrupts
  */
-#define M83xx_IEVENT_TXALL (M83xx_TSEC_IEVENT_GTSC	\
-			    | M83xx_TSEC_IEVENT_TXC 	\
-			    /*| M83xx_TSEC_IEVENT_TXB*/	\
-			    | M83xx_TSEC_IEVENT_TXF )
+#define IEVENT_TXALL (TSEC_IEVENT_GTSC	\
+			    | TSEC_IEVENT_TXC 	\
+			    /*| TSEC_IEVENT_TXB*/	\
+			    | TSEC_IEVENT_TXF )
 
 /*
  * mask for all Rx interrupts
  */
-#define M83xx_IEVENT_RXALL (M83xx_TSEC_IEVENT_RXC  	\
-			    /* | M83xx_TSEC_IEVENT_RXB */	\
-			    | M83xx_TSEC_IEVENT_GRSC 	\
-			    | M83xx_TSEC_IEVENT_RXF  )
+#define IEVENT_RXALL (TSEC_IEVENT_RXC  	\
+			    /* | TSEC_IEVENT_RXB */	\
+			    | TSEC_IEVENT_GRSC 	\
+			    | TSEC_IEVENT_RXF  )
 
 /*
  * mask for all Error interrupts
  */
-#define M83xx_IEVENT_ERRALL (M83xx_TSEC_IEVENT_BABR   		\
-			    | M83xx_TSEC_IEVENT_BSY    		\
-			    | M83xx_TSEC_IEVENT_EBERR  		\
-			    | M83xx_TSEC_IEVENT_MSRO   		\
-			    | M83xx_TSEC_IEVENT_BABT   		\
-			    | M83xx_TSEC_IEVENT_TXE    		\
-			    | M83xx_TSEC_IEVENT_LC     		\
-			    | M83xx_TSEC_IEVENT_CRL_XDA		\
-			    | M83xx_TSEC_IEVENT_XFUN   )
-
-#define M83xx_TSEC_IMASK_SET(reg,mask,val) {	\
+#define IEVENT_ERRALL (TSEC_IEVENT_BABR   		\
+			    | TSEC_IEVENT_BSY    		\
+			    | TSEC_IEVENT_EBERR  		\
+			    | TSEC_IEVENT_MSRO   		\
+			    | TSEC_IEVENT_BABT   		\
+			    | TSEC_IEVENT_TXE    		\
+			    | TSEC_IEVENT_LC     		\
+			    | TSEC_IEVENT_CRL_XDA		\
+			    | TSEC_IEVENT_XFUN   )
+
+#define TSEC_IMASK_SET(reg,mask,val) {	\
   rtems_interrupt_level level;			\
   						\
   rtems_interrupt_disable(level);		\
@@ -157,7 +156,7 @@ static struct mpc83xx_tsec_struct tsec_driver[M83xx_TSEC_NIFACES];
   rtems_interrupt_enable(level);		\
 }
 
-#define M83xx_TSEC_ALIGN_BUFFER(buf,align)		\
+#define TSEC_ALIGN_BUFFER(buf,align)		\
   ((void *)( (((uint32_t)(buf))+(align)-1)		\
 	     -(((uint32_t)(buf))+(align)-1)%align))
 
@@ -174,7 +173,7 @@ static struct mpc83xx_tsec_struct tsec_driver[M83xx_TSEC_NIFACES];
  */
 #define START_TRANSMIT_EVENT RTEMS_EVENT_2
 
-static int mpc83xx_tsec_ioctl
+static int tsec_ioctl
 (
  struct ifnet *ifp,                    /* interface information            */
  ioctl_command_t command,              /* ioctl command code               */
@@ -184,7 +183,7 @@ static int mpc83xx_tsec_ioctl
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static void mpc83xx_tsec_hwinit
+static void tsec_hwinit
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -192,14 +191,14 @@ static void mpc83xx_tsec_hwinit
 +---------------------------------------------------------------------------+
 | Input Parameters:                                                         |
 \*-------------------------------------------------------------------------*/
- struct mpc83xx_tsec_struct *sc        /* control structure                */
+ struct tsec_struct *sc        /* control structure                */
 )
 /*-------------------------------------------------------------------------*\
 | Return Value:                                                             |
 |    <none>                                                                 |
 \*=========================================================================*/
 {
-  m83xxTSEC_Registers_t  *reg_ptr = sc->reg_ptr; /* pointer to TSEC registers*/
+  volatile tsec_registers *reg_ptr = sc->reg_ptr; /* pointer to TSEC registers*/
   uint8_t *mac_addr;
   size_t i;
 
@@ -213,10 +212,10 @@ static void mpc83xx_tsec_hwinit
    * - enable statistics
    * NOTE: do not clear bits set in BSP init function
    */
-  reg_ptr->ecntrl = ((reg_ptr->ecntrl & ~M83xx_TSEC_ECNTRL_AUTOZ)
-		     | M83xx_TSEC_ECNTRL_CLRCNT
-		     | M83xx_TSEC_ECNTRL_STEN
-		     | M83xx_TSEC_ECNTRL_R100M);
+  reg_ptr->ecntrl = ((reg_ptr->ecntrl & ~TSEC_ECNTRL_AUTOZ)
+		     | TSEC_ECNTRL_CLRCNT
+		     | TSEC_ECNTRL_STEN
+		     | TSEC_ECNTRL_R100M);
 
   /*
    * init DMA control register:
@@ -224,17 +223,17 @@ static void mpc83xx_tsec_hwinit
    * - write BD status before interrupt request
    * - do not poll TxBD, but wait for TSTAT[THLT] to be written
    */
-  reg_ptr->dmactrl = (M83xx_TSEC_DMACTL_TDSEN
-		      | M83xx_TSEC_DMACTL_TBDSEN
-		      | M83xx_TSEC_DMACTL_WWR
-		      | M83xx_TSEC_DMACTL_WOP);
+  reg_ptr->dmactrl = (TSEC_DMACTL_TDSEN
+		      | TSEC_DMACTL_TBDSEN
+		      | TSEC_DMACTL_WWR
+		      | TSEC_DMACTL_WOP);
 
   /*
    * init Attribute register:
    * - enable read snooping for data and BD
    */
-  reg_ptr->attr = (M83xx_TSEC_ATTR_RDSEN
-		   | M83xx_TSEC_ATTR_RBDSEN);
+  reg_ptr->attr = (TSEC_ATTR_RDSEN
+		   | TSEC_ATTR_RBDSEN);
 
 
   reg_ptr->mrblr  = MCLBYTES-64; /* take care of buffer size lost
@@ -243,12 +242,12 @@ static void mpc83xx_tsec_hwinit
   /*
    * init EDIS register: disable all error reportings
    */
-  reg_ptr->edis = (M83xx_TSEC_EDIS_BSYDIS    |
-		   M83xx_TSEC_EDIS_EBERRDIS  |
-		   M83xx_TSEC_EDIS_TXEDIS    |
-		   M83xx_TSEC_EDIS_LCDIS     |
-		   M83xx_TSEC_EDIS_CRLXDADIS |
-		   M83xx_TSEC_EDIS_FUNDIS);
+  reg_ptr->edis = (TSEC_EDIS_BSYDIS    |
+		   TSEC_EDIS_EBERRDIS  |
+		   TSEC_EDIS_TXEDIS    |
+		   TSEC_EDIS_LCDIS     |
+		   TSEC_EDIS_CRLXDADIS |
+		   TSEC_EDIS_FUNDIS);
   /*
    * init minimum frame length register
    */
@@ -264,31 +263,31 @@ static void mpc83xx_tsec_hwinit
   /*
    * init transmit interrupt coalescing register
    */
-  reg_ptr->txic = (M83xx_TSEC_TXIC_ICEN
-		   | M83xx_TSEC_TXIC_ICFCT(2)
-		   | M83xx_TSEC_TXIC_ICTT(32));
+  reg_ptr->txic = (TSEC_TXIC_ICEN
+		   | TSEC_TXIC_ICFCT(2)
+		   | TSEC_TXIC_ICTT(32));
   /*
    * init receive interrupt coalescing register
    */
 #if 0
-  reg_ptr->rxic = (M83xx_TSEC_RXIC_ICEN
-		   | M83xx_TSEC_RXIC_ICFCT(2)
-		   | M83xx_TSEC_RXIC_ICTT(32));
+  reg_ptr->rxic = (TSEC_RXIC_ICEN
+		   | TSEC_RXIC_ICFCT(2)
+		   | TSEC_RXIC_ICTT(32));
 #else
   reg_ptr->rxic = 0;
 #endif
   /*
    * init MACCFG1 register
    */
-  reg_ptr->maccfg1 = (M83xx_TSEC_MACCFG1_RX_FLOW
-		      | M83xx_TSEC_MACCFG1_TX_FLOW);
+  reg_ptr->maccfg1 = (TSEC_MACCFG1_RX_FLOW
+		      | TSEC_MACCFG1_TX_FLOW);
 
   /*
    * init MACCFG2 register
    */
-  reg_ptr->maccfg2 = ((reg_ptr->maccfg2 & M83xx_TSEC_MACCFG2_IFMODE_MSK)
-		      | M83xx_TSEC_MACCFG2_PRELEN( 7)
-		      | M83xx_TSEC_MACCFG2_FULLDUPLEX);
+  reg_ptr->maccfg2 = ((reg_ptr->maccfg2 & TSEC_MACCFG2_IFMODE_MSK)
+		      | TSEC_MACCFG2_PRELEN( 7)
+		      | TSEC_MACCFG2_FULLDUPLEX);
 
   /*
    * init station address register
@@ -323,7 +322,7 @@ static void mpc83xx_tsec_hwinit
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static void mpc83xx_tsec_mdio_init
+static void tsec_mdio_init
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -331,7 +330,7 @@ static void mpc83xx_tsec_mdio_init
 +---------------------------------------------------------------------------+
 | Input Parameters:                                                         |
 \*-------------------------------------------------------------------------*/
- struct mpc83xx_tsec_struct *sc        /* control structure                */
+ struct tsec_struct *sc        /* control structure                */
 )
 /*-------------------------------------------------------------------------*\
 | Return Value:                                                             |
@@ -342,12 +341,6 @@ static void mpc83xx_tsec_mdio_init
   /* Set TSEC registers for MDIO communication */
 
   /*
-   * FIXME: Not clear if this works for all boards.
-   * Tested only on MPC8313ERDB.
-   */
-  sc->mdio_ptr = &mpc83xx.tsec [0];
-
-  /*
    * set clock divider
    */
   sc->mdio_ptr->miimcfg = 3;
@@ -356,7 +349,7 @@ static void mpc83xx_tsec_mdio_init
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-int mpc83xx_tsec_mdio_read
+static int tsec_mdio_read
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -374,10 +367,10 @@ int mpc83xx_tsec_mdio_read
 |    0, if ok, else error                                                   |
 \*=========================================================================*/
 {
-  struct mpc83xx_tsec_struct *sc = uarg;/* control structure                */
+  struct tsec_struct *sc = uarg;/* control structure                */
 
   /* pointer to TSEC registers */
-  m83xxTSEC_Registers_t *reg_ptr = sc->mdio_ptr;
+  volatile tsec_registers *reg_ptr = sc->mdio_ptr;
 
   /*
    * make sure we work with a valid phy
@@ -397,20 +390,20 @@ int mpc83xx_tsec_mdio_read
   /*
    * set PHY/reg address
    */
-  reg_ptr->miimadd = (M83xx_TSEC_MIIMADD_PHY(phy)
-		      | M83xx_TSEC_MIIMADD_REGADDR(reg));
+  reg_ptr->miimadd = (TSEC_MIIMADD_PHY(phy)
+		      | TSEC_MIIMADD_REGADDR(reg));
   /*
    * start read cycle
    */
   reg_ptr->miimcom = 0;
-  reg_ptr->miimcom = M83xx_TSEC_MIIMCOM_READ;
+  reg_ptr->miimcom = TSEC_MIIMCOM_READ;
 
   /*
    * wait for cycle to terminate
    */
   do {
     rtems_task_wake_after(2);
-  }  while (0 != (reg_ptr->miimind & M83xx_TSEC_MIIMIND_BUSY));
+  }  while (0 != (reg_ptr->miimind & TSEC_MIIMIND_BUSY));
   reg_ptr->miimcom = 0;
   /*
    * fetch read data, if available
@@ -424,7 +417,7 @@ int mpc83xx_tsec_mdio_read
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-int mpc83xx_tsec_mdio_write
+static int tsec_mdio_write
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -442,10 +435,10 @@ int mpc83xx_tsec_mdio_write
 |    0, if ok, else error                                                   |
 \*=========================================================================*/
 {
-  struct mpc83xx_tsec_struct *sc = uarg;/* control structure                */
+  struct tsec_struct *sc = uarg;/* control structure                */
 
   /* pointer to TSEC registers */
-  m83xxTSEC_Registers_t *reg_ptr = sc->mdio_ptr;
+  volatile tsec_registers *reg_ptr = sc->mdio_ptr;
 
   /*
    * make sure we work with a valid phy
@@ -465,8 +458,8 @@ int mpc83xx_tsec_mdio_write
   /*
    * set PHY/reg address
    */
-  reg_ptr->miimadd = (M83xx_TSEC_MIIMADD_PHY(phy)
-		      | M83xx_TSEC_MIIMADD_REGADDR(reg));
+  reg_ptr->miimadd = (TSEC_MIIMADD_PHY(phy)
+		      | TSEC_MIIMADD_REGADDR(reg));
   /*
    * start write cycle
    */
@@ -477,7 +470,7 @@ int mpc83xx_tsec_mdio_write
    */
   do {
     rtems_task_wake_after(2);
-  }  while (0 != (reg_ptr->miimind & M83xx_TSEC_MIIMIND_BUSY));
+  }  while (0 != (reg_ptr->miimind & TSEC_MIIMIND_BUSY));
   reg_ptr->miimcom = 0;
   return 0;
 }
@@ -490,7 +483,7 @@ int mpc83xx_tsec_mdio_write
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static rtems_event_set mpc83xx_tsec_rx_wait_for_events
+static rtems_event_set tsec_rx_wait_for_events
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -498,7 +491,7 @@ static rtems_event_set mpc83xx_tsec_rx_wait_for_events
 +---------------------------------------------------------------------------+
 | Input Parameters:                                                         |
 \*-------------------------------------------------------------------------*/
- struct mpc83xx_tsec_struct *sc,       /* control structure                */
+ struct tsec_struct *sc,       /* control structure                */
  rtems_event_set event_mask            /* events to wait for               */
 )
 /*-------------------------------------------------------------------------*\
@@ -510,7 +503,7 @@ static rtems_event_set mpc83xx_tsec_rx_wait_for_events
  /*
   * enable Rx interrupts, make sure this is not interrupted :-)
   */
- M83xx_TSEC_IMASK_SET(sc->reg_ptr->imask,M83xx_IEVENT_RXALL,~0);
+ TSEC_IMASK_SET(sc->reg_ptr->imask,IEVENT_RXALL,~0);
 
  /*
   * wait for events to come in
@@ -533,7 +526,7 @@ static void mpc83xx_rxbd_alloc_clear
 +---------------------------------------------------------------------------+
 | Input Parameters:                                                         |
 \*-------------------------------------------------------------------------*/
- struct mpc83xx_tsec_struct *sc        /* control structure                */
+ struct tsec_struct *sc        /* control structure                */
 )
 /*-------------------------------------------------------------------------*\
 | Return Value:                                                             |
@@ -576,7 +569,7 @@ static void mpc83xx_rxbd_alloc_clear
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static void mpc83xx_tsec_receive_packets
+static void tsec_receive_packets
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -584,7 +577,7 @@ static void mpc83xx_tsec_receive_packets
 +---------------------------------------------------------------------------+
 | Input Parameters:                                                         |
 \*-------------------------------------------------------------------------*/
- struct mpc83xx_tsec_struct *sc        /* control structure                */
+ struct tsec_struct *sc        /* control structure                */
 )
 /*-------------------------------------------------------------------------*\
 | Return Value:                                                             |
@@ -600,7 +593,7 @@ static void mpc83xx_tsec_receive_packets
 
   BD_ptr = sc->Rx_NxtUsed_BD;
 
-  while ((0 == ((status = BD_ptr->status) & M83xx_BD_EMPTY)) &&
+  while ((0 == ((status = BD_ptr->status) & BD_EMPTY)) &&
 	 !finished &&
 	 (BD_ptr->buffer != NULL)) {
     /*
@@ -613,14 +606,14 @@ static void mpc83xx_tsec_receive_packets
     /*
      * Check that packet is valid
      */
-    if ((status & (M83xx_BD_LAST |
-		   M83xx_BD_FIRST_IN_FRAME |
-		   M83xx_BD_LONG |
-		   M83xx_BD_NONALIGNED |
-		   M83xx_BD_CRC_ERROR |
-		   M83xx_BD_OVERRUN ))
-	== (M83xx_BD_LAST |
-	    M83xx_BD_FIRST_IN_FRAME ) ) {
+    if ((status & (BD_LAST |
+		   BD_FIRST_IN_FRAME |
+		   BD_LONG |
+		   BD_NONALIGNED |
+		   BD_CRC_ERROR |
+		   BD_OVERRUN ))
+	== (BD_LAST |
+	    BD_FIRST_IN_FRAME ) ) {
       /*
        * send mbuf of this buffer to ether_input()
        */
@@ -654,7 +647,7 @@ static void mpc83xx_tsec_receive_packets
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static void mpc83xx_tsec_refill_rxbds
+static void tsec_refill_rxbds
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -662,7 +655,7 @@ static void mpc83xx_tsec_refill_rxbds
 +---------------------------------------------------------------------------+
 | Input Parameters:                                                         |
 \*-------------------------------------------------------------------------*/
- struct mpc83xx_tsec_struct *sc        /* control structure                */
+ struct tsec_struct *sc        /* control structure                */
 )
 /*-------------------------------------------------------------------------*\
 | Return Value:                                                             |
@@ -696,13 +689,13 @@ static void mpc83xx_tsec_refill_rxbds
       sc->Rx_mBuf_Ptr[bd_idx] = m;
 
       m->m_pkthdr.rcvif= &sc->arpcom.ac_if;
-      m->m_data        = M83xx_TSEC_ALIGN_BUFFER(m->m_ext.ext_buf,64);
+      m->m_data        = TSEC_ALIGN_BUFFER(m->m_ext.ext_buf,64);
       BD_ptr->buffer   = m->m_data;
       BD_ptr->length   = 0;
-      BD_ptr->status   = (M83xx_BD_EMPTY
-			  | M83xx_BD_INTERRUPT
+      BD_ptr->status   = (BD_EMPTY
+			  | BD_INTERRUPT
 			  | ((BD_ptr == sc->Rx_Last_BD)
-			     ? M83xx_BD_WRAP
+			     ? BD_WRAP
 			     : 0));
       /*
        * Advance BD_ptr to next BD
@@ -718,7 +711,7 @@ static void mpc83xx_tsec_refill_rxbds
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static void mpc83xx_tsec_rxDaemon
+static void tsec_rxDaemon
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -733,8 +726,8 @@ static void mpc83xx_tsec_rxDaemon
 |    <none>                                                                 |
 \*=========================================================================*/
 {
-  struct mpc83xx_tsec_struct *sc =
-    (struct mpc83xx_tsec_struct *)arg;
+  struct tsec_struct *sc =
+    (struct tsec_struct *)arg;
   bool finished = false;
   rtems_event_set events;
 #if !defined(CLREVENT_IN_IRQ)
@@ -743,33 +736,33 @@ static void mpc83xx_tsec_rxDaemon
   /*
    * enable Rx in MACCFG1 register
    */
-  sc->reg_ptr->maccfg1 |= M83xx_TSEC_MACCFG1_RXEN;
+  sc->reg_ptr->maccfg1 |= TSEC_MACCFG1_RXEN;
   while (!finished) {
     /*
      * fetch MBufs, associate them to RxBDs
      */
-    mpc83xx_tsec_refill_rxbds(sc);
+    tsec_refill_rxbds(sc);
     /*
      * wait for events to come in
      */
-    events = mpc83xx_tsec_rx_wait_for_events(sc,INTERRUPT_EVENT);
+    events = tsec_rx_wait_for_events(sc,INTERRUPT_EVENT);
 #if !defined(CLREVENT_IN_IRQ)
     /*
      * clear any pending RX events
      */
-    irq_events = sc->reg_ptr->ievent & M83xx_IEVENT_RXALL;
+    irq_events = sc->reg_ptr->ievent & IEVENT_RXALL;
     sc->reg_ptr->ievent = irq_events;
 #endif
     /*
      * fetch any completed buffers/packets received
      * and stuff them into the TCP/IP Stack
      */
-    mpc83xx_tsec_receive_packets(sc);
+    tsec_receive_packets(sc);
   }
   /*
    * disable Rx in MACCFG1 register
    */
-  sc->reg_ptr->maccfg1 &= ~M83xx_TSEC_MACCFG1_RXEN;
+  sc->reg_ptr->maccfg1 &= ~TSEC_MACCFG1_RXEN;
   /*
    * terminate daemon
    */
@@ -792,7 +785,7 @@ static void mpc83xx_txbd_alloc_clear
 +---------------------------------------------------------------------------+
 | Input Parameters:                                                         |
 \*-------------------------------------------------------------------------*/
- struct mpc83xx_tsec_struct *sc        /* control structure                */
+ struct tsec_struct *sc        /* control structure                */
 )
 /*-------------------------------------------------------------------------*\
 | Return Value:                                                             |
@@ -835,7 +828,7 @@ static void mpc83xx_txbd_alloc_clear
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-void mpc83xx_tsec_tx_start
+static void tsec_tx_start
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -850,7 +843,7 @@ struct ifnet *ifp
 |    <none>                                                                 |
 \*=========================================================================*/
 {
-  struct mpc83xx_tsec_struct *sc = ifp->if_softc;
+  struct tsec_struct *sc = ifp->if_softc;
 
   ifp->if_flags |= IFF_OACTIVE;
 
@@ -860,7 +853,7 @@ struct ifnet *ifp
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static rtems_event_set mpc83xx_tsec_tx_wait_for_events
+static rtems_event_set tsec_tx_wait_for_events
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -868,7 +861,7 @@ static rtems_event_set mpc83xx_tsec_tx_wait_for_events
 +---------------------------------------------------------------------------+
 | Input Parameters:                                                         |
 \*-------------------------------------------------------------------------*/
- struct mpc83xx_tsec_struct *sc,       /* control structure                */
+ struct tsec_struct *sc,       /* control structure                */
  rtems_event_set event_mask            /* events to wait for               */
 )
 /*-------------------------------------------------------------------------*\
@@ -880,7 +873,7 @@ static rtems_event_set mpc83xx_tsec_tx_wait_for_events
  /*
   * enable Tx interrupts, make sure this is not interrupted :-)
   */
- M83xx_TSEC_IMASK_SET(sc->reg_ptr->imask,M83xx_IEVENT_TXALL,~0);
+ TSEC_IMASK_SET(sc->reg_ptr->imask,IEVENT_TXALL,~0);
 
  /*
   * wait for events to come in
@@ -895,7 +888,7 @@ static rtems_event_set mpc83xx_tsec_tx_wait_for_events
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static void mpc83xx_tsec_tx_retire
+static void tsec_tx_retire
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -903,7 +896,7 @@ static void mpc83xx_tsec_tx_retire
 +---------------------------------------------------------------------------+
 | Input Parameters:                                                         |
 \*-------------------------------------------------------------------------*/
- struct mpc83xx_tsec_struct *sc        /* control structure                */
+ struct tsec_struct *sc        /* control structure                */
 )
 /*-------------------------------------------------------------------------*\
 | Return Value:                                                             |
@@ -918,7 +911,7 @@ static void mpc83xx_tsec_tx_retire
    * check next BDs to be empty
    */
   while ((RetBD->buffer != NULL)                       /* BD is filled      */
-	 && (0 == (RetBD->status & M83xx_BD_READY ))) {/* BD no longer ready*/
+	 && (0 == (RetBD->status & BD_READY ))) {/* BD no longer ready*/
 
     bd_idx = RetBD - sc->Tx_Frst_BD;
     m = sc->Tx_mBuf_Ptr[bd_idx];
@@ -939,7 +932,7 @@ static void mpc83xx_tsec_tx_retire
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static void mpc83xx_tsec_sendpacket
+static void tsec_sendpacket
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -947,7 +940,7 @@ static void mpc83xx_tsec_sendpacket
 +---------------------------------------------------------------------------+
 | Input Parameters:                                                         |
 \*-------------------------------------------------------------------------*/
- struct mpc83xx_tsec_struct *sc,       /* control structure                */
+ struct tsec_struct *sc,       /* control structure                */
  struct mbuf *m                        /* start of packet to send          */
 )
 /*-------------------------------------------------------------------------*\
@@ -988,19 +981,19 @@ static void mpc83xx_tsec_sendpacket
 	 * Then try to retire it
 	 * and to return its mbuf
 	 */
-	mpc83xx_tsec_tx_retire(sc);
+	tsec_tx_retire(sc);
 	if (CurrBD->buffer != NULL) {
 	  /*
 	   * Wait for anything to happen...
 	   */
-	  mpc83xx_tsec_tx_wait_for_events(sc,INTERRUPT_EVENT);
+	  tsec_tx_wait_for_events(sc,INTERRUPT_EVENT);
 	}
       }
-      status = ((M83xx_BD_PAD_CRC | M83xx_BD_TX_CRC)
+      status = ((BD_PAD_CRC | BD_TX_CRC)
 		| ((m->m_next == NULL)
-		   ? M83xx_BD_LAST | M83xx_BD_INTERRUPT
+		   ? BD_LAST | BD_INTERRUPT
 		   : 0)
-		| ((CurrBD == sc->Tx_Last_BD) ? M83xx_BD_WRAP : 0));
+		| ((CurrBD == sc->Tx_Last_BD) ? BD_WRAP : 0));
 
       /*
        * link buffer to BD
@@ -1022,7 +1015,7 @@ static void mpc83xx_tsec_sendpacket
 	FrstBD = CurrBD;
       }
       else {
-	status |= M83xx_BD_READY;
+	status |= BD_READY;
       }
       CurrBD->status = status;
       /*
@@ -1039,19 +1032,19 @@ static void mpc83xx_tsec_sendpacket
    * to BD chain, so set first BD ready now
    */
   if (FrstBD != NULL) {
-    FrstBD->status |= M83xx_BD_READY;
+    FrstBD->status |= BD_READY;
   }
   sc->Tx_NxtFill_BD = CurrBD;
   /*
    * wake up transmitter (clear TSTAT[THLT])
    */
-  sc->reg_ptr->tstat = M83xx_TSEC_TSTAT_THLT;
+  sc->reg_ptr->tstat = TSEC_TSTAT_THLT;
 }
 
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static void mpc83xx_tsec_txDaemon
+static void tsec_txDaemon
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -1066,8 +1059,8 @@ static void mpc83xx_tsec_txDaemon
 |    <none>                                                                 |
 \*=========================================================================*/
 {
-  struct mpc83xx_tsec_struct *sc =
-    (struct mpc83xx_tsec_struct *)arg;
+  struct tsec_struct *sc =
+    (struct tsec_struct *)arg;
   struct ifnet *ifp = &sc->arpcom.ac_if;
   struct mbuf *m;
   bool finished = false;
@@ -1080,25 +1073,25 @@ static void mpc83xx_tsec_txDaemon
    * enable Tx in MACCFG1 register
    * FIXME: make this irq save
    */
-  sc->reg_ptr->maccfg1 |= M83xx_TSEC_MACCFG1_TXEN;
+  sc->reg_ptr->maccfg1 |= TSEC_MACCFG1_TXEN;
   while (!finished) {
     /*
      * wait for events to come in
      */
-    events = mpc83xx_tsec_tx_wait_for_events(sc,
+    events = tsec_tx_wait_for_events(sc,
 					     START_TRANSMIT_EVENT
 					     | INTERRUPT_EVENT);
 #if !defined(CLREVENT_IN_IRQ)
     /*
      * clear any pending TX events
      */
-    irq_events = sc->reg_ptr->ievent & M83xx_IEVENT_TXALL;
+    irq_events = sc->reg_ptr->ievent & IEVENT_TXALL;
     sc->reg_ptr->ievent = irq_events;
 #endif
     /*
      * retire any sent tx BDs
      */
-    mpc83xx_tsec_tx_retire(sc);
+    tsec_tx_retire(sc);
     /*
      * Send packets till queue is empty
      */
@@ -1109,7 +1102,7 @@ static void mpc83xx_tsec_txDaemon
       IF_DEQUEUE(&ifp->if_snd, m);
 
       if (m) {
-	mpc83xx_tsec_sendpacket(sc,m);
+	tsec_sendpacket(sc,m);
       }
     } while (m != NULL);
 
@@ -1118,7 +1111,7 @@ static void mpc83xx_tsec_txDaemon
   /*
    * disable Tx in MACCFG1 register
    */
-  sc->reg_ptr->maccfg1 &= ~M83xx_TSEC_MACCFG1_TXEN;
+  sc->reg_ptr->maccfg1 &= ~TSEC_MACCFG1_TXEN;
   /*
    * terminate daemon
    */
@@ -1133,7 +1126,7 @@ static void mpc83xx_tsec_txDaemon
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static void mpc83xx_tsec_tx_irq_handler
+static void tsec_tx_irq_handler
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -1148,8 +1141,8 @@ static void mpc83xx_tsec_tx_irq_handler
 |    <none>                                                                 |
 \*=========================================================================*/
 {
-  struct mpc83xx_tsec_struct *sc =
-    (struct mpc83xx_tsec_struct *)handle;
+  struct tsec_struct *sc =
+    (struct tsec_struct *)handle;
 #if defined(CLREVENT_IN_IRQ)
   uint32_t irq_events;
 #endif
@@ -1158,13 +1151,13 @@ static void mpc83xx_tsec_tx_irq_handler
   /*
    * disable tx interrupts
    */
-  M83xx_TSEC_IMASK_SET(sc->reg_ptr->imask,M83xx_IEVENT_TXALL,0);
+  TSEC_IMASK_SET(sc->reg_ptr->imask,IEVENT_TXALL,0);
 
 #if defined(CLREVENT_IN_IRQ)
   /*
    * clear any pending TX events
    */
-  irq_events = sc->reg_ptr->ievent & M83xx_IEVENT_TXALL;
+  irq_events = sc->reg_ptr->ievent & IEVENT_TXALL;
   sc->reg_ptr->ievent = irq_events;
 #endif
   /*
@@ -1176,7 +1169,7 @@ static void mpc83xx_tsec_tx_irq_handler
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static void mpc83xx_tsec_rx_irq_handler
+static void tsec_rx_irq_handler
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -1191,8 +1184,8 @@ static void mpc83xx_tsec_rx_irq_handler
 |    <none>                                                                 |
 \*=========================================================================*/
 {
-  struct mpc83xx_tsec_struct *sc =
-    (struct mpc83xx_tsec_struct *)handle;
+  struct tsec_struct *sc =
+    (struct tsec_struct *)handle;
 #if defined(CLREVENT_IN_IRQ)
   uint32_t irq_events;
 #endif
@@ -1201,12 +1194,12 @@ static void mpc83xx_tsec_rx_irq_handler
   /*
    * disable rx interrupts
    */
-  M83xx_TSEC_IMASK_SET(sc->reg_ptr->imask,M83xx_IEVENT_RXALL,0);
+  TSEC_IMASK_SET(sc->reg_ptr->imask,IEVENT_RXALL,0);
 #if defined(CLREVENT_IN_IRQ)
   /*
    * clear any pending RX events
    */
-  irq_events = sc->reg_ptr->ievent & M83xx_IEVENT_RXALL;
+  irq_events = sc->reg_ptr->ievent & IEVENT_RXALL;
   sc->reg_ptr->ievent = irq_events;
 #endif
   /*
@@ -1219,7 +1212,7 @@ static void mpc83xx_tsec_rx_irq_handler
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static void mpc83xx_tsec_err_irq_handler
+static void tsec_err_irq_handler
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -1234,25 +1227,25 @@ static void mpc83xx_tsec_err_irq_handler
 |    <none>                                                                 |
 \*=========================================================================*/
 {
-  struct mpc83xx_tsec_struct *sc =
-    (struct mpc83xx_tsec_struct *)handle;
+  struct tsec_struct *sc =
+    (struct tsec_struct *)handle;
   /*
    * clear error events in IEVENT
    */
-  sc->reg_ptr->ievent = M83xx_IEVENT_ERRALL;
+  sc->reg_ptr->ievent = IEVENT_ERRALL;
   /*
    * has Rx been stopped? then restart it
    */
-  if (0 != (sc->reg_ptr->rstat & M83xx_TSEC_RSTAT_QHLT)) {
+  if (0 != (sc->reg_ptr->rstat & TSEC_RSTAT_QHLT)) {
     sc->rxErrors++;
-    sc->reg_ptr->rstat = M83xx_TSEC_RSTAT_QHLT;
+    sc->reg_ptr->rstat = TSEC_RSTAT_QHLT;
   }
   /*
    * has Tx been stopped? then restart it
    */
-  if (0 != (sc->reg_ptr->tstat & M83xx_TSEC_TSTAT_THLT)) {
+  if (0 != (sc->reg_ptr->tstat & TSEC_TSTAT_THLT)) {
     sc->txErrors++;
-    sc->reg_ptr->tstat = M83xx_TSEC_TSTAT_THLT;
+    sc->reg_ptr->tstat = TSEC_TSTAT_THLT;
   }
 }
 
@@ -1260,7 +1253,7 @@ static void mpc83xx_tsec_err_irq_handler
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static uint32_t mpc83xx_tsec_irq_mask
+static uint32_t tsec_irq_mask
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -1269,7 +1262,7 @@ static uint32_t mpc83xx_tsec_irq_mask
 | Input Parameters:                                                         |
 \*-------------------------------------------------------------------------*/
  int irqnum,
- struct mpc83xx_tsec_struct *sc
+ struct tsec_struct *sc
 )
 /*-------------------------------------------------------------------------*\
 | Return Value:                                                             |
@@ -1277,17 +1270,17 @@ static uint32_t mpc83xx_tsec_irq_mask
 \*=========================================================================*/
 {
   return ((irqnum == sc->irq_num_tx)
-	  ? M83xx_IEVENT_TXALL
+	  ? IEVENT_TXALL
 	  : ((irqnum == sc->irq_num_rx)
-	     ? M83xx_IEVENT_RXALL
+	     ? IEVENT_RXALL
 	     : ((irqnum == sc->irq_num_err)
-		? M83xx_IEVENT_ERRALL
+		? IEVENT_ERRALL
 		: 0)));
 }
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static void mpc83xx_tsec_irq_on
+static void tsec_irq_on
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -1303,18 +1296,18 @@ static void mpc83xx_tsec_irq_on
 |    <none>                                                                 |
 \*=========================================================================*/
 {
-  struct mpc83xx_tsec_struct *sc =
-    (struct mpc83xx_tsec_struct *)(irq_conn_data->handle);
+  struct tsec_struct *sc =
+    (struct tsec_struct *)(irq_conn_data->handle);
 
-  M83xx_TSEC_IMASK_SET(sc->reg_ptr->imask,
-		       mpc83xx_tsec_irq_mask(irq_conn_data->name,sc),
+  TSEC_IMASK_SET(sc->reg_ptr->imask,
+		       tsec_irq_mask(irq_conn_data->name,sc),
 		       ~0);
 }
 
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static void mpc83xx_tsec_irq_off
+static void tsec_irq_off
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -1330,18 +1323,18 @@ static void mpc83xx_tsec_irq_off
 |    <none>                                                                 |
 \*=========================================================================*/
 {
-  struct mpc83xx_tsec_struct *sc =
-    (struct mpc83xx_tsec_struct *)irq_conn_data->handle;
+  struct tsec_struct *sc =
+    (struct tsec_struct *)irq_conn_data->handle;
 
-  M83xx_TSEC_IMASK_SET(sc->reg_ptr->imask,
-		       mpc83xx_tsec_irq_mask(irq_conn_data->name,sc),
+  TSEC_IMASK_SET(sc->reg_ptr->imask,
+		       tsec_irq_mask(irq_conn_data->name,sc),
 		       0);
 }
 
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static int mpc83xx_tsec_irq_isOn
+static int tsec_irq_isOn
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -1357,17 +1350,17 @@ static int mpc83xx_tsec_irq_isOn
 |    <none>                                                                 |
 \*=========================================================================*/
 {
-  struct mpc83xx_tsec_struct *sc =
-    (struct mpc83xx_tsec_struct *)irq_conn_data->handle;
+  struct tsec_struct *sc =
+    (struct tsec_struct *)irq_conn_data->handle;
 
   return (0 != (sc->reg_ptr->imask
-		& mpc83xx_tsec_irq_mask(irq_conn_data->name,sc)));
+		& tsec_irq_mask(irq_conn_data->name,sc)));
 }
 
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static void mpc83xx_tsec_install_irq_handlers
+static void tsec_install_irq_handlers
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -1375,7 +1368,7 @@ static void mpc83xx_tsec_install_irq_handlers
 +---------------------------------------------------------------------------+
 | Input Parameters:                                                         |
 \*-------------------------------------------------------------------------*/
- struct mpc83xx_tsec_struct *sc,        /* ptr to control structure        */
+ struct tsec_struct *sc,        /* ptr to control structure        */
  bool   install                         /* true: install, false: remove    */
 )
 /*-------------------------------------------------------------------------*\
@@ -1388,25 +1381,25 @@ static void mpc83xx_tsec_install_irq_handlers
   rtems_irq_connect_data irq_conn_data[3] = {
     {
       sc->irq_num_tx,
-      mpc83xx_tsec_tx_irq_handler, /* rtems_irq_hdl           */
+      tsec_tx_irq_handler, /* rtems_irq_hdl           */
       (rtems_irq_hdl_param)sc,     /* (rtems_irq_hdl_param)   */
-      mpc83xx_tsec_irq_on,         /* (rtems_irq_enable)      */
-      mpc83xx_tsec_irq_off,        /* (rtems_irq_disable)     */
-      mpc83xx_tsec_irq_isOn        /* (rtems_irq_is_enabled)  */
+      tsec_irq_on,         /* (rtems_irq_enable)      */
+      tsec_irq_off,        /* (rtems_irq_disable)     */
+      tsec_irq_isOn        /* (rtems_irq_is_enabled)  */
     },{
       sc->irq_num_rx,
-      mpc83xx_tsec_rx_irq_handler, /* rtems_irq_hdl           */
+      tsec_rx_irq_handler, /* rtems_irq_hdl           */
       (rtems_irq_hdl_param)sc,     /* (rtems_irq_hdl_param)   */
-      mpc83xx_tsec_irq_on,         /* (rtems_irq_enable)      */
-      mpc83xx_tsec_irq_off,        /* (rtems_irq_disable)     */
-      mpc83xx_tsec_irq_isOn        /* (rtems_irq_is_enabled)  */
+      tsec_irq_on,         /* (rtems_irq_enable)      */
+      tsec_irq_off,        /* (rtems_irq_disable)     */
+      tsec_irq_isOn        /* (rtems_irq_is_enabled)  */
     },{
       sc->irq_num_err,
-      mpc83xx_tsec_err_irq_handler, /* rtems_irq_hdl           */
+      tsec_err_irq_handler, /* rtems_irq_hdl           */
       (rtems_irq_hdl_param)sc,      /* (rtems_irq_hdl_param)   */
-      mpc83xx_tsec_irq_on,          /* (rtems_irq_enable)      */
-      mpc83xx_tsec_irq_off,         /* (rtems_irq_disable)     */
-      mpc83xx_tsec_irq_isOn         /* (rtems_irq_is_enabled)  */
+      tsec_irq_on,          /* (rtems_irq_enable)      */
+      tsec_irq_off,         /* (rtems_irq_disable)     */
+      tsec_irq_isOn         /* (rtems_irq_is_enabled)  */
     }
   };
 
@@ -1436,7 +1429,7 @@ static void mpc83xx_tsec_install_irq_handlers
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static void mpc83xx_tsec_init
+static void tsec_init
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -1451,7 +1444,7 @@ static void mpc83xx_tsec_init
 |    zero, if success                                                       |
 \*=========================================================================*/
 {
-  struct mpc83xx_tsec_struct *sc = (struct mpc83xx_tsec_struct *)arg;
+  struct tsec_struct *sc = (struct tsec_struct *)arg;
   struct ifnet *ifp = &sc->arpcom.ac_if;
   /*
    * check, whether device is not yet running
@@ -1478,34 +1471,34 @@ static void mpc83xx_tsec_init
      * - set interrupt coalescing to BDCount/8, Time of 8 frames
      * - enable DMA snooping
      */
-    mpc83xx_tsec_hwinit(sc);
+    tsec_hwinit(sc);
     /*
      * init access to phys
      */
-    mpc83xx_tsec_mdio_init(sc);
+    tsec_mdio_init(sc);
     /*
      * Start driver tasks
      */
     sc->txDaemonTid = rtems_bsdnet_newproc("TStx",
 					   4096,
-					   mpc83xx_tsec_txDaemon,
+					   tsec_txDaemon,
 					   sc);
     sc->rxDaemonTid = rtems_bsdnet_newproc("TSrx", 4096,
-					   mpc83xx_tsec_rxDaemon,
+					   tsec_rxDaemon,
 					   sc);
     /*
      * install interrupt handlers
      */
-    mpc83xx_tsec_install_irq_handlers(sc,true);
+    tsec_install_irq_handlers(sc,true);
   }
   /*
    * Set flags appropriately
    */
   if(ifp->if_flags & IFF_PROMISC) {
-    sc->reg_ptr->rctrl |=  M83xx_TSEC_RCTRL_PROM;
+    sc->reg_ptr->rctrl |=  TSEC_RCTRL_PROM;
   }
   else {
-    sc->reg_ptr->rctrl &= ~M83xx_TSEC_RCTRL_PROM;
+    sc->reg_ptr->rctrl &= ~TSEC_RCTRL_PROM;
   }
 
 #if defined(HSC_CM01)
@@ -1513,7 +1506,7 @@ static void mpc83xx_tsec_init
    * for HSC CM01: we need to configure the PHY to use maximum skew adjust
    */
 
-  mpc83xx_tsec_mdio_write(-1,sc,23,0x0100);
+  tsec_mdio_write(-1,sc,23,0x0100);
 #endif
 
   /*
@@ -1529,7 +1522,7 @@ static void mpc83xx_tsec_init
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static void mpc83xx_tsec_off
+static void tsec_off
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -1537,7 +1530,7 @@ static void mpc83xx_tsec_off
 +---------------------------------------------------------------------------+
 | Input Parameters:                                                         |
 \*-------------------------------------------------------------------------*/
- struct mpc83xx_tsec_struct *sc         /* ptr to control structure        */
+ struct tsec_struct *sc         /* ptr to control structure        */
 )
 /*-------------------------------------------------------------------------*\
 | Return Value:                                                             |
@@ -1552,7 +1545,7 @@ static void mpc83xx_tsec_off
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static void mpc83xx_tsec_stats
+static void tsec_stats
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -1560,7 +1553,7 @@ static void mpc83xx_tsec_stats
 +---------------------------------------------------------------------------+
 | Input Parameters:                                                         |
 \*-------------------------------------------------------------------------*/
- struct mpc83xx_tsec_struct *sc         /* ptr to control structure        */
+ struct tsec_struct *sc         /* ptr to control structure        */
 )
 /*-------------------------------------------------------------------------*\
 | Return Value:                                                             |
@@ -1574,7 +1567,7 @@ static void mpc83xx_tsec_stats
    */
   media = IFM_MAKEWORD(0,0,0,sc->phy_default); /* fetch from default phy */
 
-  result = mpc83xx_tsec_ioctl(&(sc->arpcom.ac_if),
+  result = tsec_ioctl(&(sc->arpcom.ac_if),
 			      SIOCGIFMEDIA,
 			      (caddr_t)&media);
   if (result == 0) {
@@ -1587,7 +1580,7 @@ static void mpc83xx_tsec_stats
     uint32_t reg_val;
     printf("****** PHY register values****\n");
     for (reg = 0;reg <= 31;reg++) {
-      mpc83xx_tsec_mdio_read(-1,sc,reg,&reg_val);
+      tsec_mdio_read(-1,sc,reg,&reg_val);
       printf("%02d:0x%04x%c",reg,reg_val,
 	     (((reg % 4) == 3) ? '\n' : ' '));
     }
@@ -1599,38 +1592,38 @@ static void mpc83xx_tsec_stats
   printf ("   Rx Interrupts:%-8lu",   sc->rxInterrupts);
   printf ("       Rx Errors:%-8lu",   sc->rxErrors);
   printf ("      Rx packets:%-8lu\n",
-	  sc->reg_ptr->rmon_mib[m83xx_tsec_rmon_rpkt]);
+	  sc->reg_ptr->rmon_mib[TSEC_RMON_RPKT]);
   printf ("   Rx broadcasts:%-8lu",
-	  sc->reg_ptr->rmon_mib[m83xx_tsec_rmon_rbca]);
+	  sc->reg_ptr->rmon_mib[TSEC_RMON_RBCA]);
   printf ("   Rx multicasts:%-8lu",
-	  sc->reg_ptr->rmon_mib[m83xx_tsec_rmon_rmca]);
+	  sc->reg_ptr->rmon_mib[TSEC_RMON_RMCA]);
   printf ("           Giant:%-8lu\n",
-	  sc->reg_ptr->rmon_mib[m83xx_tsec_rmon_rovr]);
+	  sc->reg_ptr->rmon_mib[TSEC_RMON_ROVR]);
   printf ("       Non-octet:%-8lu",
-	  sc->reg_ptr->rmon_mib[m83xx_tsec_rmon_raln]);
+	  sc->reg_ptr->rmon_mib[TSEC_RMON_RALN]);
   printf ("         Bad CRC:%-8lu",
-	  sc->reg_ptr->rmon_mib[m83xx_tsec_rmon_rfcs]);
+	  sc->reg_ptr->rmon_mib[TSEC_RMON_RFCS]);
   printf ("         Overrun:%-8lu\n",
-	  sc->reg_ptr->rmon_mib[m83xx_tsec_rmon_rdrp]);
+	  sc->reg_ptr->rmon_mib[TSEC_RMON_RDRP]);
 
   printf ("   Tx Interrupts:%-8lu",   sc->txInterrupts);
   printf ("       Tx Errors:%-8lu",   sc->txErrors);
   printf ("      Tx packets:%-8lu\n",
-	  sc->reg_ptr->rmon_mib[m83xx_tsec_rmon_tpkt]);
+	  sc->reg_ptr->rmon_mib[TSEC_RMON_TPKT]);
   printf ("        Deferred:%-8lu",
-	  sc->reg_ptr->rmon_mib[m83xx_tsec_rmon_tdfr]);
+	  sc->reg_ptr->rmon_mib[TSEC_RMON_TDFR]);
   printf ("  Late Collision:%-8lu",
-	  sc->reg_ptr->rmon_mib[m83xx_tsec_rmon_tlcl]);
+	  sc->reg_ptr->rmon_mib[TSEC_RMON_TLCL]);
   printf ("Retransmit Limit:%-8lu\n",
-	  sc->reg_ptr->rmon_mib[m83xx_tsec_rmon_tedf]);
+	  sc->reg_ptr->rmon_mib[TSEC_RMON_TEDF]);
   printf ("        Underrun:%-8lu\n",
-	  sc->reg_ptr->rmon_mib[m83xx_tsec_rmon_tund]);
+	  sc->reg_ptr->rmon_mib[TSEC_RMON_TUND]);
 }
 
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static int mpc83xx_tsec_ioctl
+static int tsec_ioctl
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -1647,7 +1640,7 @@ static int mpc83xx_tsec_ioctl
 |    zero, if success                                                       |
 \*=========================================================================*/
 {
-  struct mpc83xx_tsec_struct *sc = ifp->if_softc;
+  struct tsec_struct *sc = ifp->if_softc;
   int error = 0;
 
   switch(command)  {
@@ -1671,10 +1664,10 @@ static int mpc83xx_tsec_ioctl
      * adjust active state
      */
     if (ifp->if_flags & IFF_RUNNING) {
-      mpc83xx_tsec_off(sc);
+      tsec_off(sc);
     }
     if (ifp->if_flags & IFF_UP) {
-      mpc83xx_tsec_init(sc);
+      tsec_init(sc);
     }
     break;
 
@@ -1682,7 +1675,7 @@ static int mpc83xx_tsec_ioctl
     /*
      * show interface statistics
      */
-    mpc83xx_tsec_stats(sc);
+    tsec_stats(sc);
     break;
 
     /*
@@ -1701,7 +1694,7 @@ static int mpc83xx_tsec_ioctl
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-int rtems_mpc83xx_tsec_mode_adapt
+static int tsec_mode_adapt
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -1717,7 +1710,7 @@ int rtems_mpc83xx_tsec_mode_adapt
 \*=========================================================================*/
 {
   int result = 0;
-  struct mpc83xx_tsec_struct *sc = ifp->if_softc;
+  struct tsec_struct *sc = ifp->if_softc;
   int media = IFM_MAKEWORD( 0, 0, 0, sc->phy_default);
 
 #ifdef DEBUG
@@ -1726,7 +1719,7 @@ int rtems_mpc83xx_tsec_mode_adapt
   /*
    * fetch media status
    */
-  result = mpc83xx_tsec_ioctl(ifp,SIOCGIFMEDIA,(caddr_t)&media);
+  result = tsec_ioctl(ifp,SIOCGIFMEDIA,(caddr_t)&media);
   if (result != 0) {
     return result;
   }
@@ -1747,7 +1740,7 @@ int rtems_mpc83xx_tsec_mode_adapt
      * set media status: set auto negotiation -> start auto-negotiation
      */
     media = IFM_MAKEWORD(0,IFM_AUTO,0,sc->phy_default);
-    result = mpc83xx_tsec_ioctl(ifp,SIOCSIFMEDIA,(caddr_t)&media);
+    result = tsec_ioctl(ifp,SIOCSIFMEDIA,(caddr_t)&media);
     if (result != 0) {
       return result;
     }
@@ -1756,7 +1749,7 @@ int rtems_mpc83xx_tsec_mode_adapt
      */
     do {
       media = IFM_MAKEWORD(0,0,0,sc->phy_default);
-      result = mpc83xx_tsec_ioctl(ifp,SIOCGIFMEDIA,(caddr_t)&media);
+      result = tsec_ioctl(ifp,SIOCGIFMEDIA,(caddr_t)&media);
       if (result != 0) {
 	return result;
       }
@@ -1771,31 +1764,31 @@ int rtems_mpc83xx_tsec_mode_adapt
    */
   if (IFM_1000_T == IFM_SUBTYPE(media)) {
     sc->reg_ptr->maccfg2 =
-      ((sc->reg_ptr->maccfg2 & ~M83xx_TSEC_MACCFG2_IFMODE_MSK)
-       | M83xx_TSEC_MACCFG2_IFMODE_BYT);
+      ((sc->reg_ptr->maccfg2 & ~TSEC_MACCFG2_IFMODE_MSK)
+       | TSEC_MACCFG2_IFMODE_BYT);
   }
   else {
     sc->reg_ptr->maccfg2 =
-      ((sc->reg_ptr->maccfg2 & ~M83xx_TSEC_MACCFG2_IFMODE_MSK)
-       | M83xx_TSEC_MACCFG2_IFMODE_NIB);
+      ((sc->reg_ptr->maccfg2 & ~TSEC_MACCFG2_IFMODE_MSK)
+       | TSEC_MACCFG2_IFMODE_NIB);
   }
   /*
    * if we are 10MBit, then switch rate to 10M
    */
   if (IFM_10_T == IFM_SUBTYPE(media)) {
-    sc->reg_ptr->ecntrl &= ~M83xx_TSEC_ECNTRL_R100M;
+    sc->reg_ptr->ecntrl &= ~TSEC_ECNTRL_R100M;
   }
   else {
-    sc->reg_ptr->ecntrl |= M83xx_TSEC_ECNTRL_R100M;
+    sc->reg_ptr->ecntrl |= TSEC_ECNTRL_R100M;
   }
   /*
    * if we are half duplex then switch to half duplex
    */
   if (0 == (IFM_FDX & IFM_OPTIONS(media))) {
-    sc->reg_ptr->maccfg2 &= ~M83xx_TSEC_MACCFG2_FULLDUPLEX;
+    sc->reg_ptr->maccfg2 &= ~TSEC_MACCFG2_FULLDUPLEX;
   }
   else {
-    sc->reg_ptr->maccfg2 |=  M83xx_TSEC_MACCFG2_FULLDUPLEX;
+    sc->reg_ptr->maccfg2 |=  TSEC_MACCFG2_FULLDUPLEX;
   }
   /*
    * store current media state for future compares
@@ -1808,7 +1801,7 @@ int rtems_mpc83xx_tsec_mode_adapt
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static void mpc83xx_tsec_watchdog
+static void tsec_watchdog
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -1824,46 +1817,27 @@ static void mpc83xx_tsec_watchdog
 |    1, if success                                                       |
 \*=========================================================================*/
 {
-  rtems_mpc83xx_tsec_mode_adapt(ifp);
+  tsec_mode_adapt(ifp);
   ifp->if_timer    = TSEC_WATCHDOG_TIMEOUT;
 }
 
-/*=========================================================================*\
-| Function:                                                                 |
-\*-------------------------------------------------------------------------*/
-static int mpc83xx_tsec_driver_attach
-(
-/*-------------------------------------------------------------------------*\
-| Purpose:                                                                  |
-|   attach the driver                                                       |
-+---------------------------------------------------------------------------+
-| Input Parameters:                                                         |
-\*-------------------------------------------------------------------------*/
- struct rtems_bsdnet_ifconfig *config  /* interface configuration          */
+static int tsec_driver_attach(
+  struct rtems_bsdnet_ifconfig *config,
+  int unitNumber,
+  char *unitName,
+  volatile tsec_registers *reg_ptr,
+  volatile tsec_registers *mdio_ptr
 )
-/*-------------------------------------------------------------------------*\
-| Return Value:                                                             |
-|    1, if success                                                          |
-\*=========================================================================*/
 {
-  struct mpc83xx_tsec_struct *sc;
+  struct tsec_struct *sc;
   struct ifnet *ifp;
-  int    unitNumber;
-  char   *unitName;
   uint32_t svr = _read_SVR();
   uint32_t pvr = _read_PVR();
 
  /*
-  * Parse driver name
-  */
-  if((unitNumber = rtems_bsdnet_parse_driver_name(config, &unitName)) < 0) {
-    return 0;
-  }
-
- /*
   * Is driver free?
   */
-  if ((unitNumber <= 0) || (unitNumber > M83xx_TSEC_NIFACES)) {
+  if ((unitNumber <= 0) || (unitNumber > TSEC_COUNT)) {
 
     printk ("Bad TSEC unit number.\n");
     return 0;
@@ -1897,7 +1871,8 @@ static int mpc83xx_tsec_driver_attach
   sc->acceptBroadcast = !config->ignore_broadcast;
 
   /* get pointer to TSEC register block */
-  sc->reg_ptr         = &mpc83xx.tsec[unitNumber-1];
+  sc->reg_ptr         = reg_ptr;
+  sc->mdio_ptr        = mdio_ptr;
 
   if (svr == 0x80b00010 && pvr == 0x80850010) {
     /*
@@ -1928,8 +1903,8 @@ static int mpc83xx_tsec_driver_attach
   /*
    * setup info about mdio interface
    */
-  sc->mdio_info.mdio_r   = mpc83xx_tsec_mdio_read;
-  sc->mdio_info.mdio_w   = mpc83xx_tsec_mdio_write;
+  sc->mdio_info.mdio_r   = tsec_mdio_read;
+  sc->mdio_info.mdio_w   = tsec_mdio_write;
   sc->mdio_info.has_gmii = 1; /* we support gigabit IF */
 
   /*
@@ -1954,11 +1929,11 @@ static int mpc83xx_tsec_driver_attach
   ifp->if_unit    = unitNumber;
   ifp->if_name    = unitName;
   ifp->if_mtu     = (config->mtu > 0) ? config->mtu : ETHERMTU;
-  ifp->if_init    = mpc83xx_tsec_init;
-  ifp->if_ioctl   = mpc83xx_tsec_ioctl;
-  ifp->if_start   = mpc83xx_tsec_tx_start;
+  ifp->if_init    = tsec_init;
+  ifp->if_ioctl   = tsec_ioctl;
+  ifp->if_start   = tsec_tx_start;
   ifp->if_output  = ether_output;
-  ifp->if_watchdog =  mpc83xx_tsec_watchdog; /* XXX: timer is set in "init" */
+  ifp->if_watchdog =  tsec_watchdog; /* XXX: timer is set in "init" */
 
   ifp->if_flags   = (config->ignore_broadcast) ? 0 : IFF_BROADCAST;
   /*ifp->if_flags   = IFF_BROADCAST | IFF_SIMPLEX;*/
@@ -1977,30 +1952,24 @@ static int mpc83xx_tsec_driver_attach
   return 1;
 }
 
-/*=========================================================================*\
-| Function:                                                                 |
-\*-------------------------------------------------------------------------*/
-int rtems_mpc83xx_tsec_driver_attach_detach
-(
-/*-------------------------------------------------------------------------*\
-| Purpose:                                                                  |
-|   attach or detach the driver                                             |
-+---------------------------------------------------------------------------+
-| Input Parameters:                                                         |
-\*-------------------------------------------------------------------------*/
- struct rtems_bsdnet_ifconfig *config, /* interface configuration          */
- int attaching                         /* 0 = detach, else attach          */
+int tsec_driver_attach_detach(
+  struct rtems_bsdnet_ifconfig *config,
+  int unitNumber,
+  char *unitName,
+  volatile tsec_registers *reg_ptr,
+  volatile tsec_registers *mdio_ptr,
+  int attaching
 )
-/*-------------------------------------------------------------------------*\
-| Return Value:                                                             |
-|    1, if success                                                       |
-\*=========================================================================*/
 {
   if (attaching) {
-    return mpc83xx_tsec_driver_attach(config);
-  }
-  else {
+    return tsec_driver_attach(
+      config,
+      unitNumber,
+      unitName,
+      reg_ptr,
+      mdio_ptr
+    );
+  } else {
     return 0;
   }
 }
-
diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.h b/c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.h
index fa4a4e3e8a..96c2c331a6 100644
--- a/c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.h
+++ b/c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.h
@@ -17,66 +17,355 @@
 | this file declares the MPC83xx TSEC networking driver           |
 \*===============================================================*/
 
-#include <rtems/rtems_bsdnet.h>
-
-/*=========================================================================*\
-| Function:                                                                 |
-\*-------------------------------------------------------------------------*/
-int mpc83xx_tsec_mdio_read
-(
-/*-------------------------------------------------------------------------*\
-| Purpose:                                                                  |
-|   read register of a phy                                                  |
-+---------------------------------------------------------------------------+
-| Input Parameters:                                                         |
-\*-------------------------------------------------------------------------*/
- int phy,                              /* PHY number to access or -1       */
- void *uarg,                           /* unit argument                    */
- unsigned reg,                         /* register address                 */
- uint32_t *pval                        /* ptr to read buffer               */
- );
-/*-------------------------------------------------------------------------*\
-| Return Value:                                                             |
-|    0, if ok, -1 if failed                                                 |
-\*=========================================================================*/
-
-/*=========================================================================*\
-| Function:                                                                 |
-\*-------------------------------------------------------------------------*/
-int mpc83xx_tsec_mdio_write
-(
-/*-------------------------------------------------------------------------*\
-| Purpose:                                                                  |
-|   write register of a phy                                                 |
-+---------------------------------------------------------------------------+
-| Input Parameters:                                                         |
-\*-------------------------------------------------------------------------*/
- int phy,                              /* PHY number to access or -1       */
- void *uarg,                           /* unit argument                    */
- unsigned reg,                         /* register address                 */
- uint32_t val                          /* write value                      */
- );
-/*-------------------------------------------------------------------------*\
-| Return Value:                                                             |
-|    0, if ok, -1 if failed                                                 |
-\*=========================================================================*/
-
-/*=========================================================================*\
-| Function:                                                                 |
-\*-------------------------------------------------------------------------*/
-int rtems_mpc83xx_tsec_driver_attach_detach
-(
-/*-------------------------------------------------------------------------*\
-| Purpose:                                                                  |
-|   attach or detach the driver                                             |
-+---------------------------------------------------------------------------+
-| Input Parameters:                                                         |
-\*-------------------------------------------------------------------------*/
- struct rtems_bsdnet_ifconfig *config, /* interface configuration          */
- int attaching                         /* 0 = detach, else attach          */
- );
-/*-------------------------------------------------------------------------*\
-| Return Value:                                                             |
-|    1, if success                                                       |
-\*=========================================================================*/
+#ifndef LIBCPU_POWERPC_TSEC_H
+#define LIBCPU_POWERPC_TSEC_H
 
+#include <stdint.h>
+#include <bsp/tsec-config.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+  /*
+   * this enumeration defines the index
+   * of a given rmon mib counter
+   * in the tsec_rmon_mib array
+   */
+typedef enum {
+  /* TSEC1 Transmit and Receive Counters */
+  TSEC_RMON_TR64,                    /* 0x2_4680 Transmit and receive 64-byte frame counter register R/W 0x0000_0000 15.5.3.7.1/15-60 */
+  TSEC_RMON_TR127,                   /* 0x2_4684 Transmit and receive 65- to 127-byte frame counter register R/W 0x0000_0000 15.5.3.7.2/15-61 */
+  TSEC_RMON_TR255,                   /* 0x2_4688 Transmit and receive 128- to 255-byte frame counter register R/W 0x0000_0000 15.5.3.7.3/15-61 */
+  TSEC_RMON_TR511,                   /* 0x2_468C Transmit and receive 256- to 511-byte frame counter register R/W 0x0000_0000 15.5.3.7.4/15-62 */
+  TSEC_RMON_TR1K,                    /* 0x2_4690 Transmit and receive 512- to 1023-byte frame counter register R/W 0x0000_0000 15.5.3.7.5/15-62 */
+  TSEC_RMON_TRMAX,                   /* 0x2_4694 Transmit and receive 1024- to 1518-byte frame counter register R/W 0x0000_0000 15.5.3.7.6/15-63 */
+  TSEC_RMON_TRMGV,                   /* 0x2_4698 Transmit and receive 1519- to 1522-byte good VLAN frame count register R/W 0x0000_0000 15.5.3.7.7/15-63 */
+  /* TSEC1 Receive Counters */
+  TSEC_RMON_RBYT,                    /* 0x2_469C Receive byte counter register R/W 0x0000_0000 15.5.3.7.8/15-64 */
+  TSEC_RMON_RPKT,                    /* 0x2_46A0 Receive packet counter register R/W 0x0000_0000 15.5.3.7.9/15-64 */
+  TSEC_RMON_RFCS,                    /* 0x2_46A4 Receive FCS error counter register R/W 0x0000_0000 15.5.3.7.10/15-65 */
+  TSEC_RMON_RMCA,                    /* 0x2_46A8 Receive multicast packet counter register R/W 0x0000_0000 15.5.3.7.11/15-65 */
+  TSEC_RMON_RBCA,                    /* 0x2_46AC Receive broadcast packet counter register R/W 0x0000_0000 15.5.3.7.12/15-66 */
+  TSEC_RMON_RXCF,                    /* 0x2_46B0 Receive control frame packet counter register R/W 0x0000_0000 15.5.3.7.13/15-66 */
+  TSEC_RMON_RXPF,                    /* 0x2_46B4 Receive PAUSE frame packet counter register R/W 0x0000_0000 15.5.3.7.14/15-67 */
+  TSEC_RMON_RXUO,                    /* 0x2_46B8 Receive unknown OP code counter register R/W 0x0000_0000 15.5.3.7.15/15-67 */
+  TSEC_RMON_RALN,                    /* 0x2_46BC Receive alignment error counter register R/W 0x0000_0000 15.5.3.7.16/15-68 */
+  TSEC_RMON_RFLR,                    /* 0x2_46C0 Receive frame length error counter register R/W 0x0000_0000 15.5.3.7.17/15-68 */
+  TSEC_RMON_RCDE,                    /* 0x2_46C4 Receive code error counter register R/W 0x0000_0000 15.5.3.7.18/15-69 */
+  TSEC_RMON_RCSE,                    /* 0x2_46C8 Receive carrier sense error counter register R/W 0x0000_0000 15.5.3.7.19/15-69 */
+  TSEC_RMON_RUND,                    /* 0x2_46CC Receive undersize packet counter register R/W 0x0000_0000 15.5.3.7.20/15-70 */
+  TSEC_RMON_ROVR,                    /* 0x2_46D0 Receive oversize packet counter register R/W 0x0000_0000 15.5.3.7.21/15-70 */
+  TSEC_RMON_RFRG,                    /* 0x2_46D4 Receive fragments counter register R/W 0x0000_0000 15.5.3.7.22/15-71 */
+  TSEC_RMON_RJBR,                    /* 0x2_46D8 Receive jabber counter register R/W 0x0000_0000 15.5.3.7.23/15-71 */
+  TSEC_RMON_RDRP,                    /* 0x2_46DC Receive drop register R/W 0x0000_0000 15.5.3.7.24/15-72 */
+  /* TSEC1 Transmit Counters */
+  TSEC_RMON_TBYT,                    /* 0x2_46E0 Transmit byte counter register R/W 0x0000_0000 15.5.3.7.25/15-72 */
+  TSEC_RMON_TPKT,                    /* 0x2_46E4 Transmit packet counter register R/W 0x0000_0000 15.5.3.7.26/15-73 */
+  TSEC_RMON_TMCA,                    /* 0x2_46E8 Transmit multicast packet counter register R/W 0x0000_0000 15.5.3.7.27/15-73 */
+  TSEC_RMON_TBCA,                    /* 0x2_46EC Transmit broadcast packet counter register R/W 0x0000_0000 15.5.3.7.28/15-74 */
+  TSEC_RMON_TXPF,                    /* 0x2_46F0 Transmit PAUSE control frame counter register R/W 0x0000_0000 15.5.3.7.29/15-74 */
+  TSEC_RMON_TDFR,                    /* 0x2_46F4 Transmit deferral packet counter register R/W 0x0000_0000 15.5.3.7.30/15-75 */
+  TSEC_RMON_TEDF,                    /* 0x2_46F8 Transmit excessive deferral packet counter register R/W 0x0000_0000 15.5.3.7.31/15-75 */
+  TSEC_RMON_TSCL,                    /* 0x2_46FC Transmit single collision packet counter register R/W 0x0000_0000 15.5.3.7.32/15-76 */
+  TSEC_RMON_TMCL,                    /* 0x2_4700 Transmit multiple collision packet counter register R/W 0x0000_0000 15.5.3.7.33/15-76 */
+  TSEC_RMON_TLCL,                    /* 0x2_4704 Transmit late collision packet counter register R/W 0x0000_0000 15.5.3.7.34/15-77 */
+  TSEC_RMON_TXCL,                    /* 0x2_4708 Transmit excessive collision packet counter register R/W 0x0000_0000 15.5.3.7.35/15-77 */
+  TSEC_RMON_TNCL,                    /* 0x2_470C Transmit total collision counter register R/W 0x0000_0000 15.5.3.7.36/15-78 */
+  TSEC_RESERVED1,                    /* 0x2_4710 Reserved, should be cleared R 0x0000_0000  */
+  TSEC_RMON_TDRP,                    /* 0x2_4714 Transmit drop frame counter register R/W 0x0000_0000 15.5.3.7.37/15-78 */
+  TSEC_RMON_TJBR,                    /* 0x2_4718 Transmit jabber frame counter register R/W 0x0000_0000 15.5.3.7.38/15-79 */
+  TSEC_RMON_TFCS,                    /* 0x2_471C Transmit FCS error counter register R/W 0x0000_0000 15.5.3.7.39/15-79 */
+  TSEC_RMON_TXCF,                    /* 0x2_4720 Transmit control frame counter register R/W 0x0000_0000 15.5.3.7.40/15-80 */
+  TSEC_RMON_TOVR,                    /* 0x2_4724 Transmit oversize frame counter register R/W 0x0000_0000 15.5.3.7.41/15-80 */
+  TSEC_RMON_TUND,                    /* 0x2_4728 Transmit undersize frame counter register R/W 0x0000_0000 15.5.3.7.42/15-81 */
+  TSEC_RMON_TFRG,                    /* 0x2_472C Transmit fragments frame counter register R/W 0x0000_0000 15.5.3.7.43/15-81 */
+  TSEC_RMON_CNT
+} tsec_rmon_idx;
+
+  /* TSEC1/2 General Control and Status Registers */
+typedef struct {
+  uint8_t reserved0x2_4000[0x24010-0x24000]; /* 0x2_4000--0x2_400F Reserved, should be cleared */
+  uint32_t ievent;                  /* 0x2_4010 Interrupt event register R/W 0x0000_0000 15.5.3.1.1/15-19 */
+  uint32_t imask;                   /* 0x2_4014 Interrupt mask register R/W 0x0000_0000 15.5.3.1.2/15-22 */
+  uint32_t edis;                    /* 0x2_4018 Error disabled register R/W 0x0000_0000 15.5.3.1.3/15-24 */
+  uint8_t reserved0x2_401c[0x24020-0x2401c]; /* 0x2_401c--0x2_401f Reserved, should be cleared */
+  uint32_t ecntrl;                  /* 0x2_4020 Ethernet control register R/W 0x0000_0000 15.5.3.1.4/15-25 */
+  uint32_t minflr;                  /* 0x2_4024 Minimum frame length register R/W 0x0000_0040 15.5.3.1.5/15-26 */
+  uint32_t ptv;                     /* 0x2_4028 Pause time value register R/W 0x0000_0000 15.5.3.1.6/15-27 */
+  uint32_t dmactrl;                 /* 0x2_402C DMA control register R/W 0x0000_0000 15.5.3.1.7/15-28 */
+  uint32_t tbipa;                   /* 0x2_4030 TBI PHY address register R/W 0x0000_0000 15.5.3.1.8/15-29 */
+  uint8_t reserved0x2_4034[0x2408c-0x24034]; /* 0x2_4034--0x2_408b Reserved, should be cleared */
+  /* TSEC1 FIFO Control and Status Registers */
+  uint32_t fifo_tx_thr;             /* 0x2_408C FIFO transmit threshold register R/W 0x0000_0100 15.5.3.2.1/15-30 */
+  uint8_t reserved0x2_4090[0x24094-0x24090]; /* 0x2_4090--0x2_4093 Reserved, should be cleared */
+  uint32_t fifo_tx_sp;              /* 0x2_4094 FIFO transmit space available register R/W 0x0000_0010 15.5.3.2.2/15-31 */
+  uint32_t fifo_tx_starve;          /* 0x2_4098 FIFO transmit starve register R/W 0x0000_0080 15.5.3.2.3/15-31 */
+  uint32_t fifo_tx_starve_shutoff;  /* 0x2_409C FIFO transmit starve shutoff register R/W 0x0000_0100 15.5.3.2.4/15-32 */
+  uint8_t reserved0x2_40A0[0x24100-0x240A0]; /* 0x2_40A0--0x2_40ff Reserved, should be cleared */
+  /* TSEC1 Transmit Control and Status Registers */
+  uint32_t tctrl;                   /* 0x2_4100 Transmit control register R/W 0x0000_0000 15.5.3.3.1/15-33 */
+  uint32_t tstat;                   /* 0x2_4104 Transmit status register R/W 0x0000_0000 15.5.3.3.2/15-34 */
+  uint8_t reserved0x2_4108[0x24110-0x24108]; /* 0x2_4108 Reserved, should be cleared R 0x0000_0000 */
+  uint32_t txic;                    /* 0x2_4110 Transmit interrupt coalescing configuration register R/W 0x0000_0000 */
+  uint8_t reserved0x2_4114[0x24124-0x24114]; /* 0x2_4114--0x2_4120 Reserved, should be cleared */
+  uint32_t ctbptr;                  /* 0x2_4124 Current TxBD pointer register R 0x0000_0000 15.5.3.3.5/15-36 */
+  uint8_t reserved0x2_4128[0x24184-0x24128]; /* 0x2_4128--0x2_4180 Reserved, should be cleared */
+  uint32_t tbptr;                   /* 0x2_4184 TxBD pointer register R/W 0x0000_0000 15.5.3.3.6/15-36 */
+  uint8_t reserved0x2_4188[0x24204-0x24188]; /* 0x2_4188--0x2_4200 Reserved, should be cleared */
+  uint32_t tbase;                   /* 0x2_4204 TxBD base address register R/W 0x0000_0000 15.5.3.3.7/15-37 */
+  uint8_t reserved0x2_4208[0x242B0-0x24208]; /* 0x2_4208--0x2_42AC Reserved, should be cleared */
+  uint32_t ostbd;                   /* 0x2_42B0 Out-of-sequence TxBD register R/W 0x0800_0000 15.5.3.3.8/15-37 */
+  uint32_t ostbdp;                  /* 0x2_42B4 Out-of-sequence Tx data buffer pointer register R/W 0x0000_0000 15.5.3.3.9/15-39 */
+  uint8_t reserved0x2_42B8[0x24300-0x242B8]; /* 0x2_42B8--0x2_42FC Reserved, should be cleared */
+  /* TSEC1 Receive Control and Status Registers */
+  uint32_t rctrl;                   /* 0x2_4300 Receive control register R/W 0x0000_0000 15.5.3.4.1/15-40 */
+  uint32_t rstat;                   /* 0x2_4304 Receive status register R/W 0x0000_0000 15.5.3.4.2/15-41 */
+  uint8_t reserved0x2_4308[0x2430C-0x24308]; /* 0x2_4308 Reserved, should be cleared R 0x0000_0000  */
+  uint32_t rbdlen;                  /* 0x2_430C RxBD data length register R 0x0000_0000 15.5.3.4.3/15-41 */
+  uint32_t rxic;                    /* 0x2_4310 Receive interrupt coalescing configuration register R/W 0x0000_0000 15.5.3.4.4/15-42 */
+  uint8_t reserved0x2_4314[0x24324-0x24314]; /* 0x2_4314--0x2_4320 Reserved, should be cleared */
+  uint32_t crbptr;                  /* 0x2_4324 Current RxBD pointer register R 0x0000_0000 15.5.3.4.5/15-43 */
+  uint8_t reserved0x2_4328[0x24340-0x24328]; /* 0x2_4328--0x2_433C Reserved, should be cleared */
+  uint32_t mrblr;                   /* 0x2_4340 Maximum receive buffer length register R/W 0x0000_0000 15.5.3.4.6/15-43 */
+  uint8_t reserved0x2_4344[0x24384-0x24344]; /* 0x2_4344--0x2_4380 Reserved, should be cleared */
+  uint32_t rbptr;                   /* 0x2_4384 RxBD pointer register R/W 0x0000_0000 15.5.3.4.7/15-44 */
+  uint8_t reserved0x2_4388[0x24404-0x24388]; /* 0x2_4388--0x2_4400 Reserved, should be cleared */
+  uint32_t rbase;                   /* 0x2_4404 RxBD base address register R/W 0x0000_0000 15.5.3.4.8/15-44 */
+  uint8_t reserved0x2_4408[0x24500-0x24408]; /* 0x2_4408--0x2_44FC Reserved, should be cleared */
+  /* TSEC1 MAC Registers */
+  uint32_t maccfg1;                 /* 0x2_4500 MAC configuration register 1 R/W, R 0x0000_0000 15.5.3.6.1/15-48 */
+  uint32_t maccfg2;                 /* 0x2_4504 MAC configuration register 2 R/W 0x0000_7000 15.5.3.6.2/15-49 */
+  uint32_t ipgifg;                  /* 0x2_4508 Inter-packet gap/inter-frame gap register R/W 0x4060_5060 15.5.3.6.3/15-51 */
+  uint32_t hafdup;                  /* 0x2_450C Half-duplex register R/W 0x00A1_F037 15.5.3.6.4/15-52 */
+  uint32_t maxfrm;                  /* 0x2_4510 Maximum frame length register R/W 0x0000_0600 15.5.3.6.5/15-53 */
+  uint8_t reserved0x2_4514[0x24520-0x24514]; /* 0x2_4514--0x2_451C Reserved, should be cleared */
+  uint32_t miimcfg;                 /* 0x2_4520 MII management configuration register R/W 0x0000_0000 15.5.3.6.6/15-53 */
+  uint32_t miimcom;                 /* 0x2_4524 MII management command register R/W 0x0000_0000 15.5.3.6.7/15-54 */
+  uint32_t miimadd;                 /* 0x2_4528 MII management address register R/W 0x0000_0000 15.5.3.6.8/15-55 */
+  uint32_t miimcon;                 /* 0x2_452C MII management control register W 0x0000_0000 15.5.3.6.9/15-56 */
+  uint32_t miimstat;                /* 0x2_4530 MII management status register R 0x0000_0000 15.5.3.6.10/15-56 */
+  uint32_t miimind;                 /* 0x2_4534 MII management indicator register R 0x0000_0000 15.5.3.6.11/15-57 */
+  uint8_t reserved0x2_4538[0x2453c-0x24538]; /* 0x2_4538 Reserved, should be cleared  $ $ */
+  uint32_t ifstat;                  /* 0x2_453C Interface status register Special 0x0000_0001 15.5.3.6.12/15-58 */
+  uint32_t macstnaddr[2];             /* 0x2_4540 Station address register, part 1/2 R/W 0x0000_0000 15.5.3.6.13/15-58 */
+  uint8_t reserved0x2_4548[0x24680-0x24548]; /* 0x2_4548--0x2_467C Reserved, should be cleared */
+
+  /* TSEC1 RMON MIB Registers */
+  uint32_t rmon_mib[TSEC_RMON_CNT];
+
+  /* TSEC1 General Registers */
+  uint32_t car[2];                  /* 0x2_4730 Carry register one/two register R 0x0000_0000 15.5.3.7.44/15-82 */
+  uint32_t cam[2];                  /* 0x2_4738 Carry register one/two mask register R/W 0xFE01_FFFF 15.5.3.7.46/15-85 */
+  uint8_t reserved0x2_4740[0x24800-0x24740]; /* 0x2_4740--0x2_47FC Reserved, should be cleared */
+
+  /* TSEC1 Hash Function Registers */
+  uint32_t iaddr[8];                /* 0x2_4800 Individual address register 0-7 R/W 0x0000_0000 15.5.3.8.1/15-87 */
+  uint8_t reserved0x2_4820[0x24880-0x24820]; /* 0x2_4820--0x2_487C Reserved, should be cleared */
+  uint32_t gaddr[8];                /* 0x2_4880 Group address register 0-7 R/W 0x0000_0000 15.5.3.8.2/15-88 */
+  uint8_t reserved0x2_48A0[0x24B00-0x248A0]; /* 0x2_48A0--0x2_4AFF Reserved, should be cleared */
+
+  /* TSEC1 Attribute Registers */
+  uint8_t reserved0x2_4B00[0x24BF8-0x24B00]; /* 0x2_4B00--0x2_4BF4 Reserved, should be cleared */
+  uint32_t attr;                    /* 0x2_4BF8 Attribute register R 0x0000_0000 */
+  uint32_t attreli;                 /* 0x2_4BFC Attribute extract length and extract index register R/W 0x0000_0000 */
+  uint8_t reserved0x2_4C00[0x25000-0x24C00]; /* 0x2_4C00--0x2_4FFF Reserved, should be cleared */
+} tsec_registers;
+
+/*
+ * TSEC IEVENT/IMASK bit definitions
+ */
+#define TSEC_IEVENT_BABR      (1<<(31- 0))
+#define TSEC_IEVENT_RXC       (1<<(31- 1))
+#define TSEC_IEVENT_BSY       (1<<(31- 2))
+#define TSEC_IEVENT_EBERR     (1<<(31- 3))
+#define TSEC_IEVENT_MSRO      (1<<(31- 5))
+#define TSEC_IEVENT_GTSC      (1<<(31- 6))
+#define TSEC_IEVENT_BABT      (1<<(31- 7))
+#define TSEC_IEVENT_TXC       (1<<(31- 8))
+#define TSEC_IEVENT_TXE       (1<<(31- 9))
+#define TSEC_IEVENT_TXB       (1<<(31-10))
+#define TSEC_IEVENT_TXF       (1<<(31-11))
+#define TSEC_IEVENT_LC        (1<<(31-13))
+#define TSEC_IEVENT_CRL_XDA   (1<<(31-14))
+#define TSEC_IEVENT_XFUN      (1<<(31-15))
+#define TSEC_IEVENT_RXB       (1<<(31-16))
+#define TSEC_IEVENT_MMRD      (1<<(31-21))
+#define TSEC_IEVENT_MMWR      (1<<(31-22))
+#define TSEC_IEVENT_GRSC      (1<<(31-23))
+#define TSEC_IEVENT_RXF       (1<<(31-24))
+
+/*
+ * TSEC DMACTRL bit definitions
+ */
+#define TSEC_DMACTL_TDSEN  (1<<(31-24))
+#define TSEC_DMACTL_TBDSEN (1<<(31-25))
+#define TSEC_DMACTL_GRS    (1<<(31-27))
+#define TSEC_DMACTL_GTS    (1<<(31-28))
+#define TSEC_DMACTL_WWR    (1<<(31-30))
+#define TSEC_DMACTL_WOP    (1<<(31-31))
+
+/*
+ * TSEC TSTAT bit definitions
+ */
+#define TSEC_TSTAT_THLT  (1<<(31-0))
+
+/*
+ * TSEC RSTAT bit definitions
+ */
+#define TSEC_RSTAT_QHLT  (1<<(31-8))
+  /*
+   * TSEC ECNTRL bit positions
+   */
+#define TSEC_ECNTRL_CLRCNT (1 << (31-17))  /* Clear stat counters     */
+#define TSEC_ECNTRL_AUTOZ  (1 << (31-18))  /* auto-zero read counters */
+#define TSEC_ECNTRL_STEN   (1 << (31-19))  /* enable statistics       */
+#define TSEC_ECNTRL_TBIM   (1 << (31-26))  /* ten-bit-interface       */
+#define TSEC_ECNTRL_RPM    (1 << (31-27))  /* reduced signal mode     */
+#define TSEC_ECNTRL_R100M  (1 << (31-28))  /* RGMII100 mode           */
+  /*
+   * TSEC EDIS bit positions
+   */
+#define TSEC_EDIS_BSYDIS    (1 << (31- 2))  /* Busy disable            */
+#define TSEC_EDIS_EBERRDIS  (1 << (31- 3))  /* bus error disable       */
+#define TSEC_EDIS_TXEDIS    (1 << (31- 9))  /* Tx error disable        */
+#define TSEC_EDIS_LCDIS     (1 << (31-13))  /* Late collision disable  */
+#define TSEC_EDIS_CRLXDADIS (1 << (31-14))  /* Collision Retry disable */
+#define TSEC_EDIS_FUNDIS    (1 << (31-15))  /* Tx FIFO underrun disable*/
+
+  /*
+   * TSEC RCTRL bit positions
+   */
+#define TSEC_RCTRL_BC_REJ  (1 << (31-27))  /* Broadcast Reject        */
+#define TSEC_RCTRL_PROM    (1 << (31-28))  /* Promiscuous             */
+#define TSEC_RCTRL_RSF     (1 << (31-29))  /* Receive short frames    */
+
+  /*
+   * TSEC TXIC bit positions
+   */
+#define TSEC_TXIC_ICEN      (1 << (31- 0))  /* Irq coalescing enable   */
+#define TSEC_TXIC_ICFCT(n) (((n)&0xff) << (31-10))  /* Frame coal. cnt */
+#define TSEC_TXIC_ICTT(n) (((n)&0xffff) << (31-31))  /* Buf. coal. cnt */
+
+  /*
+   * TSEC RXIC bit positions
+   */
+#define TSEC_RXIC_ICEN      (1 << (31- 0))  /* Irq coalescing enable   */
+#define TSEC_RXIC_ICFCT(n) (((n)&0xff) << (31-10))  /* Frame coal. cnt */
+#define TSEC_RXIC_ICTT(n) (((n)&0xffff) << (31-31))  /* Buf. coal. cnt */
+
+  /*
+   * TSEC MACCFG1 bit positions
+   */
+#define TSEC_MACCFG1_SOFTRST   (1 << (31- 0))  /* Soft Reset           */
+#define TSEC_MACCFG1_RES_RXMC  (1 << (31-12))  /* Reset Rx MAC block   */
+#define TSEC_MACCFG1_RES_TXMC  (1 << (31-13))  /* Reset Tx MAC block   */
+#define TSEC_MACCFG1_RES_RXFUN (1 << (31-14))  /* Reset Rx function blk*/
+#define TSEC_MACCFG1_RES_TXFUN (1 << (31-15))  /* Reset Tx function blk*/
+#define TSEC_MACCFG1_LOOPBACK  (1 << (31-23))  /* Loopback mode        */
+#define TSEC_MACCFG1_RX_FLOW   (1 << (31-26))  /* Receive Flow Ctrl    */
+#define TSEC_MACCFG1_TX_FLOW   (1 << (31-27))  /* Transmit Flow Ctrl   */
+#define TSEC_MACCFG1_SYNVRXEN  (1 << (31-28))  /* Sync Receive Enable  */
+#define TSEC_MACCFG1_RXEN      (1 << (31-29))  /* Receive Enable       */
+#define TSEC_MACCFG1_SYNVTXEN  (1 << (31-30))  /* Sync Transmit Enable */
+#define TSEC_MACCFG1_TXEN      (1 << (31-31))  /* Transmit Enable      */
+
+  /*
+   * TSEC MACCFG2 bit positions
+   */
+#define TSEC_MACCFG2_PRELEN(n) (((n)&0x0f) << (31-19))  /* Preamble len*/
+
+#define TSEC_MACCFG2_IFMODE_MSK (3 << (31-23)) /* mode mask            */
+#define TSEC_MACCFG2_IFMODE_NIB (1 << (31-23)) /* nibble mode          */
+#define TSEC_MACCFG2_IFMODE_BYT (2 << (31-23)) /* byte mode            */
+
+#define TSEC_MACCFG2_HUGE_FRAME (1 << (31-26)) /* Huge Frame           */
+#define TSEC_MACCFG2_LENGTH_CHK (1 << (31-27)) /* Length Check         */
+#define TSEC_MACCFG2_PAD_CRC    (1 << (31-29)) /* MAC adds PAD/CRC     */
+#define TSEC_MACCFG2_CRC_EN     (1 << (31-30)) /* CRC enable           */
+#define TSEC_MACCFG2_FULLDUPLEX (1 << (31-31)) /* Full Duplex Mode     */
+
+  /*
+   * TSEC MIIMADD bit positions
+   */
+#define TSEC_MIIMADD_PHY(n)     (((n) & 0x3f)<<(31- 23))  /* PHY addr  */
+#define TSEC_MIIMADD_REGADDR(n) (((n) & 0x3f)<<(31- 31))  /* PHY addr  */
+
+  /*
+   * TSEC MIIMCOM bit positions
+   */
+#define TSEC_MIIMCOM_SCAN       (1 << (31-30))     /* Scan command     */
+#define TSEC_MIIMCOM_READ       (1 << (31-31))     /* Read command     */
+
+  /*
+   * TSEC MIIMIND bit positions
+   */
+#define TSEC_MIIMIND_NVAL       (1 << (31-29))     /* not valid        */
+#define TSEC_MIIMIND_SCAN       (1 << (31-30))     /* Scan in progress */
+#define TSEC_MIIMIND_BUSY       (1 << (31-31))     /* Acc. in progress */
+
+  /*
+   * TSEC ATTR bit positions
+   */
+#define TSEC_ATTR_RDSEN         (1 << (31-24))     /* read data snoop  */
+#define TSEC_ATTR_RBDSEN        (1 << (31-25))     /* read BD snoop    */
+
+typedef struct {
+  volatile uint16_t  status;
+  volatile uint16_t  length;
+  volatile void     *buffer;
+} PQBufferDescriptor_t;
+
+/*
+ * Bits in receive buffer descriptor status word
+ */
+#define BD_EMPTY           (1<<15)
+#define BD_RO1             (1<<14)
+#define BD_WRAP            (1<<13)
+#define BD_INTERRUPT       (1<<12)
+#define BD_LAST            (1<<11)
+#define BD_CONTROL_CHAR    (1<<11)
+#define BD_FIRST_IN_FRAME  (1<<10)
+#define BD_MISS            (1<<8)
+#define BD_BROADCAST       (1<<7)
+#define BD_MULTICAST       (1<<6)
+#define BD_LONG            (1<<5)
+#define BD_NONALIGNED      (1<<4)
+#define BD_SHORT           (1<<3)
+#define BD_CRC_ERROR       (1<<2)
+#define BD_OVERRUN         (1<<1)
+#define BD_COLLISION       (1<<0)
+
+/*
+ * Bits in transmit buffer descriptor status word
+ * Many bits have the same meaning as those in receiver buffer descriptors.
+ */
+#define BD_READY           (1<<15)
+#define BD_PAD_CRC         (1<<14)
+/* WRAP/Interrupt as in Rx BDs */
+#define BD_TX_CRC          (1<<10)
+#define BD_DEFER           (1<<9)
+#define BD_TO1             (1<<8)
+#define BD_HFE_            (1<<7)
+#define BD_LATE_COLLISION  (1<<7)
+#define BD_RETRY_LIMIT     (1<<6)
+#define BD_RETRY_COUNT(x)  (((x)&0x3C)>>2)
+#define BD_UNDERRUN        (1<<1)
+#define BD_TXTRUNC         (1<<0)
+
+struct rtems_bsdnet_ifconfig;
+
+int tsec_driver_attach_detach(
+  struct rtems_bsdnet_ifconfig *config,
+  int unitNumber,
+  char *unitName,
+  volatile tsec_registers *reg_ptr,
+  volatile tsec_registers *mdio_ptr,
+  int attaching
+);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBCPU_POWERPC_TSEC_H */