diff options
author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2011-02-16 08:33:02 +0000 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2011-02-16 08:33:02 +0000 |
commit | 0f801cdc62e14da69932be7dbb0708113e90a963 (patch) | |
tree | fd24109d7d9c84199100e9175ad63a94ba14b34b /c | |
parent | 2011-02-16 Sebastian Huber <sebastian.huber@embedded-brains.de> (diff) | |
download | rtems-0f801cdc62e14da69932be7dbb0708113e90a963.tar.bz2 |
2011-02-16 Sebastian Huber <sebastian.huber@embedded-brains.de>
* shared/include/powerpc-utility.h: Fixed LINKER_SYMBOL() for
assembler compatibilty. Added synchronization, cache, and alternate
time base functions.
Diffstat (limited to 'c')
-rw-r--r-- | c/src/lib/libcpu/powerpc/ChangeLog | 6 | ||||
-rw-r--r-- | c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h | 200 |
2 files changed, 204 insertions, 2 deletions
diff --git a/c/src/lib/libcpu/powerpc/ChangeLog b/c/src/lib/libcpu/powerpc/ChangeLog index a81252e311..4df2cce276 100644 --- a/c/src/lib/libcpu/powerpc/ChangeLog +++ b/c/src/lib/libcpu/powerpc/ChangeLog @@ -1,3 +1,9 @@ +2011-02-16 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * shared/include/powerpc-utility.h: Fixed LINKER_SYMBOL() for + assembler compatibilty. Added synchronization, cache, and alternate + time base functions. + 2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org> * mpc55xx/include/mpc55xx.h: diff --git a/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h b/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h index 2d8f9b38e9..a52c6551a5 100644 --- a/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h +++ b/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h @@ -8,7 +8,7 @@ */ /* - * Copyright (c) 2008 + * Copyright (c) 2008, 2010, 2011 * Embedded Brains GmbH * Obere Lagerstr. 30 * D-82178 Puchheim @@ -48,7 +48,7 @@ extern "C" { #include <libcpu/cpuIdent.h> -#define LINKER_SYMBOL(sym) extern char sym [] +#define LINKER_SYMBOL(sym) extern char sym []; /** * @brief Read one byte from @a src. @@ -211,6 +211,167 @@ static inline void ppc_synchronize_instructions(void) __asm__ volatile ("isync"); } +static inline void ppc_enforce_in_order_execution_of_io(void) +{ + RTEMS_COMPILER_MEMORY_BARRIER(); + + __asm__ volatile ("eieio"); +} + +static inline void ppc_data_cache_block_flush(void *addr) +{ + __asm__ volatile ( + "dcbf 0, %0" + : + : "r" (addr) + : "memory" + ); +} + +static inline void ppc_data_cache_block_flush_2( + void *base, + void *offset +) +{ + __asm__ volatile ( + "dcbf %0, %1" + : + : "b" (base), "r" (offset) + : "memory" + ); +} + +static inline void ppc_data_cache_block_invalidate(void *addr) +{ + __asm__ volatile ( + "dcbi 0, %0" + : + : "r" (addr) + : "memory" + ); +} + +static inline void ppc_data_cache_block_invalidate_2( + void *base, + void *offset +) +{ + __asm__ volatile ( + "dcbi %0, %1" + : + : "b" (base), "r" (offset) + : "memory" + ); +} + +static inline void ppc_data_cache_block_store(void *addr) +{ + __asm__ volatile ( + "dcbst 0, %0" + : + : "r" (addr) + ); +} + +static inline void ppc_data_cache_block_store_2( + void *base, + void *offset +) +{ + __asm__ volatile ( + "dcbst %0, %1" + : + : "b" (base), "r" (offset) + : "memory" + ); +} + +static inline void ppc_data_cache_block_touch(void *addr) +{ + __asm__ volatile ( + "dcbt 0, %0" + : + : "r" (addr) + ); +} + +static inline void ppc_data_cache_block_touch_2( + void *base, + void *offset +) +{ + __asm__ volatile ( + "dcbt %0, %1" + : + : "b" (base), "r" (offset) + ); +} + +static inline void ppc_data_cache_block_touch_for_store(void *addr) +{ + __asm__ volatile ( + "dcbtst 0, %0" + : + : "r" (addr) + ); +} + +static inline void ppc_data_cache_block_touch_for_store_2( + void *base, + void *offset +) +{ + __asm__ volatile ( + "dcbtst %0, %1" + : + : "b" (base), "r" (offset) + ); +} + +static inline void ppc_data_cache_block_clear_to_zero(void *addr) +{ + __asm__ volatile ( + "dcbz 0, %0" + : + : "r" (addr) + : "memory" + ); +} + +static inline void ppc_data_cache_block_clear_to_zero_2( + void *base, + void *offset +) +{ + __asm__ volatile ( + "dcbz %0, %1" + : + : "b" (base), "r" (offset) + : "memory" + ); +} + +static inline void ppc_instruction_cache_block_invalidate(void *addr) +{ + __asm__ volatile ( + "icbi 0, %0" + : + : "r" (addr) + ); +} + +static inline void ppc_instruction_cache_block_invalidate_2( + void *base, + void *offset +) +{ + __asm__ volatile ( + "icbi %0, %1" + : + : "b" (base), "r" (offset) + ); +} + /** * @brief Enables external exceptions. * @@ -575,6 +736,41 @@ static inline void ppc_set_time_base_64(uint64_t val) PPC_Set_timebase_register(val); } +static inline uint32_t ppc_alternate_time_base(void) +{ + return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBL); +} + +static inline uint32_t ppc_alternate_time_base_upper(void) +{ + return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBU); +} + +static inline uint64_t ppc_alternate_time_base_64(void) +{ + uint32_t atbl; + uint32_t atbu_0; + uint32_t atbu_1; + + do { + atbu_0 = ppc_alternate_time_base_upper(); + atbl = ppc_alternate_time_base(); + atbu_1 = ppc_alternate_time_base_upper(); + } while (atbu_0 != atbu_1); + + return (((uint64_t) atbu_1) << 32) | ((uint64_t) atbl); +} + +static inline uint32_t ppc_processor_id(void) +{ + return PPC_SPECIAL_PURPOSE_REGISTER(BOOKE_PIR); +} + +static inline void ppc_set_processor_id(uint32_t val) +{ + PPC_SET_SPECIAL_PURPOSE_REGISTER(BOOKE_PIR, val); +} + void ppc_code_copy(void *dest, const void *src, size_t n); #endif /* ifndef ASM */ |