|author||Sebastian Huber <email@example.com>||2017-07-04 14:15:03 +0200|
|committer||Sebastian Huber <firstname.lastname@example.org>||2017-07-07 13:27:24 +0200|
|parent||bsps/arm: Fix bit field offset in GIC support (diff)|
arm: Fix ARMv7-M interrupt processing4.11.2
Right after a "msr basepri_max, %[basepri]" instruction an interrupt service may still take place (observed at least on Cortex-M7). However, pendable service calls that are activated during this interrupt service may be delayed until interrupts are enable again. The _ARMV7M_Pendable_service_call() did not check that a thread dispatch is allowed. Move this test from _ARMV7M_Interrupt_service_leave() to _ARMV7M_Pendable_service_call(). Close #3060.
Diffstat (limited to 'c')
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