diff options
author | Chris Johns <chrisj@rtems.org> | 2016-08-16 15:49:41 +1000 |
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committer | Chris Johns <chrisj@rtems.org> | 2016-09-01 11:11:09 +1000 |
commit | caf2cbd81331b3368db97006a922556c59b09061 (patch) | |
tree | a2ef334d15d9f1ca2ed4d577ff543ba31e2034e9 /c/src | |
parent | arm/xilinx_zynq: ensure that cache is cleaned and MMU disabled when initializ... (diff) | |
download | rtems-caf2cbd81331b3368db97006a922556c59b09061.tar.bz2 |
arm/xilinx_zynq: Start the second core when an SMP build.
Diffstat (limited to 'c/src')
-rw-r--r-- | c/src/lib/libbsp/arm/xilinx-zynq/startup/bspsmp.c | 15 | ||||
-rw-r--r-- | c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstartmmu.c | 7 |
2 files changed, 22 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspsmp.c b/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspsmp.c index 3940352d9b..310014d8de 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspsmp.c +++ b/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspsmp.c @@ -14,9 +14,24 @@ #include <rtems/score/smpimpl.h> +extern void _start(void); + bool _CPU_SMP_Start_processor(uint32_t cpu_index) { /* + * Enable the second CPU. + */ + if (cpu_index != 0) { + volatile uint32_t* const kick_address = (uint32_t*) 0xfffffff0UL; + _ARM_Data_synchronization_barrier(); + _ARM_Instruction_synchronization_barrier(); + *kick_address = (uint32_t) _start; + _ARM_Data_synchronization_barrier(); + _ARM_Instruction_synchronization_barrier(); + _ARM_Send_event(); + } + + /* * Wait for secondary processor to complete its basic initialization so that * we can enable the unified L2 cache. */ diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstartmmu.c b/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstartmmu.c index c7a1089bf4..e0a7743e57 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstartmmu.c +++ b/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstartmmu.c @@ -22,6 +22,13 @@ BSP_START_DATA_SECTION static const arm_cp15_start_section_config zynq_mmu_config_table[] = { ARMV7_CP15_START_DEFAULT_SECTIONS, +#if defined(RTEMS_SMP) + { + .begin = 0xffff0000U, + .end = 0xffffffffU, + .flags = ARMV7_MMU_DEVICE + }, +#endif { .begin = 0xe0000000U, .end = 0xe0200000U, |