diff options
author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2012-12-21 09:26:27 +0100 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2012-12-21 15:40:27 +0100 |
commit | a640b204c066d999a8e88a3370f8b254ee813398 (patch) | |
tree | 4f1e29c6ddd0f4ef68cbabb027635b529edc4878 /c/src | |
parent | bsp/gen83xx: Fix CSB clock calculation for MPC8309 (diff) | |
download | rtems-a640b204c066d999a8e88a3370f8b254ee813398.tar.bz2 |
bsp/gen83xx: Fix RCWLR_CEVCO defines
Diffstat (limited to 'c/src')
-rw-r--r-- | c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h b/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h index 59214254e8..a120fa0b81 100644 --- a/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h +++ b/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h @@ -921,8 +921,9 @@ extern m83xxRegisters_t mpc83xx; #define RCWLR_COREPLL(n) (((n)&0xff)<<(31-15)) /* for MPC8309: */ -#define RCWLR_CEVCOD_1_4 (0<<(31-25)) /* QUICC internal PLL divider 1:4 */ -#define RCWLR_CEVCOD_1_2 (2<<(31-25)) /* QUICC internal PLL divider 1:2 */ +#define RCWLR_CEVCOD_1_8 (2<<(31-25)) /* QUICC internal PLL divider 1:8 */ +#define RCWLR_CEVCOD_1_4 (1<<(31-25)) /* QUICC internal PLL divider 1:4 */ +#define RCWLR_CEVCOD_1_2 (0<<(31-25)) /* QUICC internal PLL divider 1:2 */ /* QUICC Engine PLL mult. factor */ #define RCWLR_CEPDF_2 (1<<(31-26)) /* QUICC Engine divide PLL out by 2*/ /* QUICC Engine PLL mult. factor */ |