diff options
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-08-26 16:59:56 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-08-26 17:10:18 +0200 |
| commit | 9907ddeb5a1e823129ab7aeeeed1ed4f7a60151c (patch) | |
| tree | b2b96e7351a0d957e6eb5f43d9f07ad65a6d3d1a /c/src | |
| parent | rtems: Add more clock tick functions (diff) | |
| download | rtems-9907ddeb5a1e823129ab7aeeeed1ed4f7a60151c.tar.bz2 | |
bsp/altera-cyclone-v: Update to hwlib 13.1
This version is distributed with SoC EDS 14.0.0.200.
Diffstat (limited to 'c/src')
16 files changed, 8786 insertions, 3841 deletions
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am index 939ccc7c56..a581dee90d 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am @@ -77,6 +77,7 @@ include_bsp_HEADERS += hwlib/include/hwlib.h #include_bsp_HEADERS += hwlib/include/alt_interrupt.h # Some of the headers from hwlib need the files from socal. Install them. +include_bsp_socal_HEADERS += hwlib/include/socal/alt_acpidmap.h include_bsp_socal_HEADERS += hwlib/include/socal/alt_clkmgr.h include_bsp_socal_HEADERS += hwlib/include/socal/alt_gpio.h include_bsp_socal_HEADERS += hwlib/include/socal/alt_i2c.h @@ -118,7 +119,7 @@ libbsp_a_CPPFLAGS = libbsp_a_LIBADD = # for the Altera hwlib -libbsp_a_CPPFLAGS += -I ${srcdir}/hwlib/include +libbsp_a_CPPFLAGS += -I${srcdir}/hwlib/include libbsp_a_CPPFLAGS += -std=gnu99 CFLAGS += -Wno-missing-prototypes diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt index 154b3439ea..d0f505da76 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt @@ -16,37 +16,4 @@ Altera provides the hwlib with their SoC Embedded Design Suite (EDS). HWLIB Version: -------------- -The files have been taken from the following hwlib versions: - -|======================================== -| Version | File -| | -| 13.0SP1 | include/alt_address_space.h -| 13.0SP1 | include/alt_clock_group.h -| 13.0SP1 | include/alt_clock_manager.h -| 13.0SP1 | include/alt_generalpurpose_io.h -| 13.0SP1 | include/alt_hwlibs_ver.h -| 13.1 | include/alt_i2c.h -| 13.0SP1 | include/alt_interrupt_common.h -| 13.0SP1 | include/alt_mpu_registers.h -| 13.0SP1 | include/alt_reset_manager.h -| 13.0SP1 | include/hwlib.h -| 13.0SP1 | include/socal/alt_clkmgr.h -| 13.0SP1 | include/socal/alt_gpio.h -| 13.1 | include/socal/alt_i2c.h -| 13.0SP1 | include/socal/alt_l3.h -| 13.0SP1 | include/socal/alt_rstmgr.h -| 13.0SP1 | include/socal/alt_sdr.h -| 13.0SP1 | include/socal/alt_sysmgr.h -| 13.0SP1 | include/socal/alt_uart.h -| 13.0SP1 | include/socal/hps.h -| 13.0SP1 | include/socal/socal.h -| 13.0SP1 | src/hwmgr/alt_address_space.c -| 13.0SP1 | src/hwmgr/alt_clock_manager.c -| 13.0SP1 | src/hwmgr/alt_generalpurpose_io.c -| 13.1 | src/hwmgr/alt_i2c.c -| 13.0SP1 | src/hwmgr/alt_reset_manager.c -|======================================== - -hwlib 13.0SP1 is from SoC EDS 13.0.1.232 -hwlib 13.1 is from SoC EDS 14.0.0.200 +All files are from hwlib 13.1 distributed with SoC EDS 14.0.0.200. diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_address_space.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_address_space.h index b66ccdf344..781cc49aa3 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_address_space.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_address_space.h @@ -32,8 +32,8 @@ * ******************************************************************************/ -#ifndef __ALT_ADDR_SPACE_H__ -#define __ALT_ADDR_SPACE_H__ +#ifndef __ALT_ADDRESS_SPACE_H__ +#define __ALT_ADDRESS_SPACE_H__ #include <stdbool.h> #include "hwlib.h" @@ -82,7 +82,7 @@ extern "C" #define L2_CACHE_ADDR_FILTERING_END_ADDR (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_END_OFST) // Address Filtering End Register - End Value Mask #define L2_CACHE_ADDR_FILTERING_END_ADDR_MASK 0xFFF00000 -// Address Filtering End Register - Reset End Address Value (3 GB) +// Address Filtering End Register - Reset End Address Value (3 GiB) #define L2_CACHE_ADDR_FILTERING_END_RESET 0xC0000000 #ifndef __ASSEMBLY__ @@ -192,10 +192,10 @@ typedef enum ALT_ADDR_SPACE_MPU_ATTR_e */ typedef enum ALT_ADDR_SPACE_NONMPU_ATTR_e { - ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM, /*!< Maps the SDRAM to address 0x0 + ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM, /*!< Maps the SDRAM to address 0x0 * for the non-MPU L3 masters. */ - ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM /*!< Maps the On-chip RAM to address + ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM /*!< Maps the On-chip RAM to address * 0x0 for the non-MPU L3 * masters. Note that the On-chip * RAM is also always mapped to @@ -276,12 +276,12 @@ ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr, * * When address 0x0 is mapped to the Boot ROM or on-chip RAM, only the lowest * 64KB of the boot region are accessible because the size of the Boot ROM and - * on-chip RAM are only 64KB. Addresses in the range 0x100000 (1MB) to - * 0xC0000000 (3GB) access SDRAM and addresses in the range 0xC0000000 (3GB) to - * 0xFFFFFFFF access the L3 interconnect. Thus, the lowest 1MB of SDRAM is not + * on-chip RAM are only 64KB. Addresses in the range 0x100000 (1MiB) to + * 0xC0000000 (3GiB) access SDRAM and addresses in the range 0xC0000000 (3GiB) to + * 0xFFFFFFFF access the L3 interconnect. Thus, the lowest 1MiB of SDRAM is not * accessible to the MPU unless address 0 is remapped to SDRAM after reset. * - * This function remaps the addresses between 0x0 to 0x100000 (1MB) to access + * This function remaps the addresses between 0x0 to 0x100000 (1MiB) to access * SDRAM. * * \internal @@ -332,13 +332,13 @@ ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram(void); * \param addr_filt_start * [out] An output parameter variable for the address filtering * start address for the range of physical addresses redirected to - * the SDRAM AXI master port. The value returned is always a 1 MB + * the SDRAM AXI master port. The value returned is always a 1 MiB * aligned address. * * \param addr_filt_end * [out] An output parameter variable for the address filtering * end address for the range of physical addresses redirected to - * the SDRAM AXI master port. The value returned is always a 1 MB + * the SDRAM AXI master port. The value returned is always a 1 MiB * aligned address. * * \retval ALT_E_SUCCESS The operation was successful. @@ -353,7 +353,7 @@ ALT_STATUS_CODE alt_l2_addr_filter_cfg_get(uint32_t* addr_filt_start, /*! * Set the L2 cache address filtering configuration settings. * - * Address filtering start and end values must be 1 MB aligned. + * Address filtering start and end values must be 1 MiB aligned. * * \param addr_filt_start * The address filtering start address for the range of physical @@ -380,6 +380,441 @@ ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start, /*! @} */ +/******************************************************************************/ +/*! \addtogroup ADDR_SPACE_MGR_MEM_COHERENCE ACP Memory Coherence and ID Mapping + * + * This API provides management of the ACP ID Mapper that enables data coherent + * access to the MPU address space by external masters. The set of external + * masters include L3 master peripherals and FPGA soft IP. + * + * The Accelerator Coherency Port (ACP) allows peripherals - including FPGA + * based soft IP - to maintain data coherency with the Cortex-A9 MPCore + * processors and the Snoop Control Unit (SCU). + * + * The ACP supports up to six masters. However, soft IP implemented in the FPGA + * fabric can have a larger number of masters that need to access the ACP. The + * ACP ID Mapper expands the number of masters able to access the ACP. The ACP + * ID Mapper is situated between the interconnect and the ACP of the MPU + * subsystem. It has the following characteristics: + * * Support for up to six concurrent ID mappings. + * * 1 GiB coherent window into 4 GiB MPU address space + * * Remaps the 5-bit user sideband signals used by the Snoop Control Unit (SCU) + * and L2 cache. + * + * The function of the ACP ID Mapper is to map 12-bit Advanced Microcontroller + * Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) IDs (input + * identifiers) from the Level 3 (L3) interconnect to 3-bit AXI IDs (output + * identifiers) required by the ACP slave port. + * + * The ACP ID Mapper supports the two ID mapping modes: + * * Dynamic Mapping - In this mode an input ID is automatically mapped to an + * available output ID. The dynamic mode is more flexible because the hardware + * handles the mapping. The hardware mapping allows an output ID to be used + * for more than one input ID. Output IDs are assigned to input IDs on a + * first-come, first-served basis. + * * Fixed Mapping - In this mode there is a one-to-one mapping from input IDs + * to output IDs. + * + * Out of the total of eight ACP output ID values, only six are available to the + * ACP ID Mapper for remapping. The first two output IDs (0 and 1) are + * dedicated to the Cortex-A9 processor cores in the MPU subsystem, leaving the + * last six output IDs (2-7) available to the ACP ID mapper. Output IDs 2-6 + * support fixed and dynamic modes of operation while output ID 7 supports + * dynamic mode only. + * + * The following table summarizes the usage of the 3-bit ouput ID values by the + * ACP ID Mapper and their settings at reset. + * + * Output ID | Usage | Reset State + * :-----------|:--------------------------------------------------|:------------ + * 0 | Reserved for Cortex-A9 cores. | - + * 1 | Reserved for Cortex-A9 cores. | - + * 2 | Assigned to Debug Access Port (DAP) input ID at | Fixed + * : | reset. After reset, can be reconfigured to either | DAP Master + * : | fixed or dynamic. |: + * 3 | Configurable fixed or dynamic mode. | Dynamic + * 4 | Configurable fixed or dynamic mode. | Dynamic + * 5 | Configurable fixed or dynamic mode. | Dynamic + * 6 | Configurable fixed or dynamic mode. | Dynamic + * 7 | Dynamic mode only. | Dynamic + * + * Where <em>Output ID</em> is the ACP ID Mapper output value that goes to the ACP. + * + * Additionally, for masters unable to drive the AXI user sideband signals of + * incoming transactions, the ACP ID Mapper allows control of the AXI user + * sideband signal values. Not all masters drive these signals, so the ACP ID + * Mapper makes it possible to drive the 5-bit user sideband signal with either + * a default value (in dynamic mode) or specific values (in fixed mode). + * + * The ACP ID Mapper can also control which 1 GiB coherent window into memory is + * accessed by masters of the L3 interconnect. Each fixed mapping can be + * assigned a different user sideband signal and memory window to allow specific + * settings for different masters. All dynamic mappings share a common user + * sideband signal and memory window setting. One important exception, however, + * is that the ACP ID mapper always allows user sideband signals from the + * FPGA-to-HPS bridge to pass through to the ACP regardless of the configured + * user sideband value associated with the ID. + * + * The ACP ID Mapper has a 1 GiB address window into the MPU address space, which + * is by default a view into the bottom 1 GiB of SDRAM. The ACP ID Mapper allows + * transactions to be routed to different 1 GiB-sized memory views, called pages, + * in both dynamic and fixed modes. + * + * See: <em>Chapter 6: Cortex-A9 Microprocessor Unit Subsystem</em> in + * <em>Volume 3: Hard Processor System Technical Reference Manual</em> of the + * <em>Arria V or Cyclone V Device Handbook</em> for a complete discussion of + * the operation and restrictions on the ACP and the ACP ID Mapper. + * + * @{ + */ + +/******************************************************************************/ +/*! + * \name External Master ID Macros + * + * These macros define the HPS external master identifiers that are 12-bit input + * IDs to the ACP ID Mapper. Some of the masters have a range of identifier + * values assigned to them and are distinguished by taking a <em>(var)\</em> + * argument. + * @{ + */ + +/*! Bit mask for the relevant 12 bits of an external master ID */ +#define ALT_ACP_ID_MAP_MASTER_ID_MASK 0xfff + +/*! Master ID for L2M0 */ +#define ALT_ACP_ID_MAP_MASTER_ID_L2M0(var) (0x00000002 | (0x000007f8 & (var))) +/*! Master ID for DMA */ +#define ALT_ACP_ID_MAP_MASTER_ID_DMA(var) (0x00000001 | (0x00000078 & (var))) +/*! Master ID for EMAC0 */ +#define ALT_ACP_ID_MAP_MASTER_ID_EMAC0(var) (0x00000801 | (0x00000878 & (var))) +/*! Master ID for EMAC1 */ +#define ALT_ACP_ID_MAP_MASTER_ID_EMAC1(var) (0x00000802 | (0x00000878 & (var))) +/*! Master ID for USB0 */ +#define ALT_ACP_ID_MAP_MASTER_ID_USB0 0x00000803 +/*! Master ID for USB1 */ +#define ALT_ACP_ID_MAP_MASTER_ID_USB1 0x00000806 +/*! Master ID for NAND controller */ +#define ALT_ACP_ID_MAP_MASTER_ID_NAND(var) (0x00000804 | (0x00000ff8 & (var))) +/*! Master ID for Embedded Trace Router (ETR) */ +#define ALT_ACP_ID_MAP_MASTER_ID_TMC 0x00000800 +/*! Master ID for Debug Access Port (DAP) */ +#define ALT_ACP_ID_MAP_MASTER_ID_DAP 0x00000004 +/*! Master ID for SD/MMC controller */ +#define ALT_ACP_ID_MAP_MASTER_ID_SDMMC 0x00000805 +/*! Master ID for FPGA to HPS (F2H) bridge - conduit for soft IP masters in FPGA fabric */ +#define ALT_ACP_ID_MAP_MASTER_ID_F2H(var) (0x00000000 | (0x000007f8 & (var))) +/*! @} */ + +/******************************************************************************/ +/*! + * This type defines the enumerations 3-bit output ids to ACP ID mapper. + */ +typedef enum ALT_ACP_ID_OUTPUT_ID_e +{ + ALT_ACP_ID_OUT_FIXED_ID_2 = 2, /*!< Assigned to the input ID of the DAP at reset. + * After reset, can be either fixed or dynamic, + * programmed by software. + */ + ALT_ACP_ID_OUT_DYNAM_ID_3 = 3, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_4 = 4, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_5 = 5, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_6 = 6, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_7 = 7 /*!< Dynamic mapping only */ +} ALT_ACP_ID_OUTPUT_ID_t; + +/*! + * This type defines the enumerations used to specify the 1 GiB page view of the + * MPU address space used by an ACP ID mapping configuration. + */ +typedef enum ALT_ACP_ID_MAP_PAGE_e +{ + ALT_ACP_ID_MAP_PAGE_0 = 0, /*!< Page 0 - MPU address range 0x00000000 - 0x3FFFFFFF */ + ALT_ACP_ID_MAP_PAGE_1 = 1, /*!< Page 1 - MPU address range 0x40000000 - 0x7FFFFFFF */ + ALT_ACP_ID_MAP_PAGE_2 = 2, /*!< Page 2 - MPU address range 0x80000000 - 0xBFFFFFFF */ + ALT_ACP_ID_MAP_PAGE_3 = 3 /*!< Page 3 - MPU address range 0xC0000000 - 0xFFFFFFFF */ +} ALT_ACP_ID_MAP_PAGE_t; + +/******************************************************************************/ +/*! + * Configure a fixed ACP ID mapping for read transactions originating from + * external masters identified by \e input_id. The \e input_id value is + * translated to the specified 3-bit \e output_id required by the ACP slave + * port. + * + * \param input_id + * The 12 bit external master ID originating read transactions + * targeted for ID translation. Valid argument range must be 0 <= + * \e output_id <= 4095. + * + * \param output_id + * The 3-bit output ID value the ACP ID Mapper translates read + * transactions identified by \e input_id to. This is the value + * propogated to the ACP slave port. Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the ID tranlation mapping. + * + * \param aruser + * The 5-bit AXI ARUSER read user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e aruser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e input_id, and/or \e output_id + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e page argument is invalid. + */ +ALT_STATUS_CODE alt_acp_id_map_fixed_read_set(const uint32_t input_id, + const uint32_t output_id, + const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t aruser); + +/******************************************************************************/ +/*! + * Configure a fixed ACP ID mapping for write transactions originating from + * external masters identified by \e input_id. The \e input_id value is + * translated to the specified 3-bit \e output_id required by the ACP slave + * port. + * + * \param input_id + * The 12 bit external master ID originating write transactions + * targeted for ID translation. Valid argument range must be 0 <= + * \e output_id <= 4095. + * + * \param output_id + * The 3-bit output ID value the ACP ID Mapper translates write + * transactions identified by \e input_id to. This is the value + * propogated to the ACP slave port. Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the ID tranlation mapping. + * + * \param awuser + * The 5-bit AXI AWUSER write user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e awuser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e input_id, and/or \e output_id + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e page argument is invalid. + */ +ALT_STATUS_CODE alt_acp_id_map_fixed_write_set(const uint32_t input_id, + const uint32_t output_id, + const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t awuser); + +/******************************************************************************/ +/*! + * Configure the designated 3-bit output ID as an available identifier resource + * for use by the dynamic ID mapping function of the ACP ID Mapper for read + * transactions. The \e output_id value is available for dynamic assignment to + * external master read transaction IDs that do not have an explicit fixed ID + * mapping. + * + * \param output_id + * The 3-bit output ID value designated as an available ID for use + * by the dynamic mapping function of the ACP ID Mapper. The \e + * ouput_id value is used exclusively for dynamic ID mapping until + * reconfigured as a fixed ID mapping by a call to + * alt_acp_id_map_fixed_read_set(). Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_read_set(const uint32_t output_id); + +/******************************************************************************/ +/*! + * Configure the designated 3-bit output ID as an available identifier resource + * for use by the dynamic ID mapping function of the ACP ID Mapper for write + * transactions. The \e output_id value is available for dynamic assignment to + * external master write transaction IDs that do not have an explicit fixed ID + * mapping. + * + * \param output_id + * The 3-bit output ID value designated as an available ID for use + * by the dynamic mapping function of the ACP ID Mapper. The \e + * ouput_id value is used exclusively for dynamic ID mapping until + * reconfigured as a fixed ID mapping by a call to + * alt_acp_id_map_fixed_write_set(). Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id); + +/******************************************************************************/ +/*! + * Configure the page and user read sideband signal options that are applied to + * all read transactions that have their input IDs dynamically mapped. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the dynamic ID tranlation mapping. + * + * \param aruser + * The 5-bit AXI ARUSER read user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e aruser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e page and/or \e aruser + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e mid argument is not a valid master + * identifier. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_read_options_set(const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t aruser); + +/******************************************************************************/ +/*! + * Configure the page and user write sideband signal options that are applied to + * all write transactions that have their input IDs dynamically mapped. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the dynamic ID tranlation mapping. + * + * \param awuser + * The 5-bit AXI AWUSER write user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e aruser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e page and/or \e awuser + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e mid argument is not a valid master + * identifier. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_write_options_set(const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t awuser); + +/******************************************************************************/ +/*! + * Return the current read transaction mapping configuration used by the ACP ID + * Mapper for the specified output ID. + * + * If \e output_id is configured as a fixed mapping then \b true is returned in + * the \e fixed output parameter and the translation mapping options configured + * for that \e output_id are returned in the other output parameters. + * + * If \e output_id is configured as a dynamic mapping then \b false is returned + * in the \e fixed output parameter and the translation mapping options + * configured for all dynamically remapped output IDs are returned in the other + * output parameters. + * + * \param output_id + * The output ID to return the mapping configuration for. 0 <= \e + * output_id <= 7. + * + * \param fixed + * [out] Set to \b true if the specified \e output_id is a fixed ID + * mapping configuration. Set to \b false if the mapping + * configuration is dynamic. + * + * \param input_id + * [out] The input ID of the external master that a fixed ID + * mapping is applied to for the \e output_id. If \e fixed is \b + * false then this output parameter is set to 0 and its value + * should be considered as not applicable. + * + * \param page + * [out] The MPU address space page view used by the mapping + * configuration. + * + * \param aruser + * [out] The 5-bit AXI ARUSER read user sideband signal value used + * by the mapping configuration when masters are unable to drive + * the AXI user sideband signals. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. The \e + * output_id argument violates its range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_read_options_get(const uint32_t output_id, + bool* fixed, + uint32_t* input_id, + ALT_ACP_ID_MAP_PAGE_t* page, + uint32_t* aruser); + +/******************************************************************************/ +/*! + * Return the current write transaction mapping configuration used by the ACP ID + * Mapper for the specified output ID. + * + * If \e output_id is configured as a fixed mapping then \b true is returned in + * the \e fixed output parameter and the translation mapping options configured + * for that \e output_id are returned in the other output parameters. + * + * If \e output_id is configured as a dynamic mapping then \b false is returned + * in the \e fixed output parameter and the translation mapping options + * configured for all dynamically remapped output IDs are returned in the other + * output parameters. + * + * \param output_id + * The output ID to return the mapping configuration for. 0 <= \e + * output_id <= 7. + * + * \param fixed + * [out] Set to \b true if the specified \e output_id is a fixed ID + * mapping configuration. Set to \b false if the mapping + * configuration is dynamic. + * + * \param input_id + * [out] The input ID of the external master that a fixed ID + * mapping is applied to for the \e output_id. If \e fixed is \b + * false then this output parameter is set to 0 and its value + * should be considered as not applicable. + * + * \param page + * [out] The MPU address space page view used by the mapping + * configuration. + * + * \param awuser + * [out] The 5-bit AXI AWUSER write user sideband signal value used + * by the mapping configuration when masters are unable to drive + * the AXI user sideband signals. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. The \e + * output_id argument violates its range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id, + bool* fixed, + uint32_t* input_id, + ALT_ACP_ID_MAP_PAGE_t* page, + uint32_t* awuser); + +/*! @} */ + /*! @} */ #endif /* __ASSEMBLY__ */ @@ -387,4 +822,4 @@ ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start, #ifdef __cplusplus } #endif /* __cplusplus */ -#endif /* __ALT_ADDR_SPACE_H__ */ +#endif /* __ALT_ADDRESS_SPACE_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_group.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_group.h index a5e8c92715..a43608e9f3 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_group.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_group.h @@ -1,37 +1,39 @@ -/*! \file - * Contains the definition of an opaque data structure that contains raw - * configuration information for a clock group. - */ - /****************************************************************************** -* -* Copyright 2013 Altera Corporation. All Rights Reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of the author may not be used to endorse or promote products -* derived from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -* OF SUCH DAMAGE. -* -******************************************************************************/ + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +/*! + * \file + * + * Contains the definition of an opaque data structure that contains raw + * configuration information for a clock group. + */ #ifndef __ALT_CLK_GRP_H__ #define __ALT_CLK_GRP_H__ @@ -44,48 +46,65 @@ extern "C" { #endif /* __cplusplus */ - -/*! This type definition enumerates the clock groups -*/ +/*! + * This type definition enumerates the clock groups + */ typedef enum ALT_CLK_GRP_e { - ALT_MAIN_PLL_CLK_GRP, /*!< Main PLL clock group */ + ALT_MAIN_PLL_CLK_GRP, /*!< Main PLL clock group */ - ALT_PERIPH_PLL_CLK_GRP, /*!< Peripheral PLL clock group */ + ALT_PERIPH_PLL_CLK_GRP, /*!< Peripheral PLL clock group */ - ALT_SDRAM_PLL_CLK_GRP /*!< SDRAM PLL clock group */ + ALT_SDRAM_PLL_CLK_GRP /*!< SDRAM PLL clock group */ } ALT_CLK_GRP_t; - - -/*! This type definition defines an opaque data structure for holding the - * configuration settings for a complete clock group. +/*! + * This type definition defines an opaque data structure for holding the + * configuration settings for a complete clock group. */ typedef struct ALT_CLK_GROUP_RAW_CFG_s { - uint32_t verid; /*!< SoC FPGA version identifier. This field - * encapsulates the silicon identifier and - * version information associated with this - * clock group configuration. It is used to - * assert that this clock group configuration - * is valid for this device. - */ - uint32_t siliid2; /*!< Reserved register - reserved for future - * device IDs or capability flags/ - */ - ALT_CLK_GRP_t clkgrpsel; /*!< Clock group union discriminator */ - - - /*! This union holds the raw register values for configuration of the set of - * possible clock groups on the SoC FPGA. The \e clkgrpsel discriminator - * identifies the valid clock group union data member. + uint32_t verid; /*!< SoC FPGA version identifier. This field + * encapsulates the silicon identifier and + * version information associated with this + * clock group configuration. It is used to + * assert that this clock group configuration + * is valid for this device. */ + + uint32_t siliid2; /*!< Reserved register - reserved for future + * device IDs or capability flags. */ + + ALT_CLK_GRP_t clkgrpsel; /*!< Clock group union discriminator. */ + + /*! + * This union holds the register values for configuration of the set of + * possible clock groups on the SoC FPGA. The \e clkgrpsel discriminator + * identifies the valid clock group union data member. */ union ALT_CLK_GROUP_RAW_CFG_u { - ALT_CLKMGR_MAINPLL_t mainpllgrp; /*!< Raw clock group configuration for Main PLL group */ - ALT_CLKMGR_PERPLL_t perpllgrp; /*!< Raw clock group configuration for Peripheral PLL group */ - ALT_CLKMGR_SDRPLL_t sdrpllgrp; /*!< Raw clock group configuration for SDRAM PLL group */ + /*! Clock group configuration for Main PLL group. */ + union + { + ALT_CLKMGR_MAINPLL_t fld; /*!< Field access. */ + ALT_CLKMGR_MAINPLL_raw_t raw; /*!< Raw access. */ + } mainpllgrp; + + /*! Clock group configuration for Peripheral PLL group. */ + union + { + ALT_CLKMGR_PERPLL_t fld; /*!< Field access. */ + ALT_CLKMGR_PERPLL_raw_t raw; /*!< Raw access. */ + } perpllgrp; + + /*! Clock group configuration for SDRAM PLL group. */ + union + { + ALT_CLKMGR_SDRPLL_t fld; /*!< Field access. */ + ALT_CLKMGR_SDRPLL_raw_t raw; /*!< Raw access. */ + } sdrpllgrp; + } clkgrp; } ALT_CLK_GROUP_RAW_CFG_t; diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h index 7cf0e12048..d6d96544f7 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h @@ -6,20 +6,20 @@ /****************************************************************************** * * Copyright 2013 Altera Corporation. All Rights Reserved. -* +* * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* +* * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* +* * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* +* * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. -* +* * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO @@ -30,7 +30,7 @@ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY * OF SUCH DAMAGE. -* +* ******************************************************************************/ #ifndef __ALT_CLK_MGR_H__ @@ -82,7 +82,7 @@ typedef enum ALT_CLK_e /*!< \b OSC_CLK_2_HPS * External Oscillator input: * * Input Pin - * * Optional clock source to SDRAM PLL + * * Optional clock source to SDRAM PLL * and Peripheral PLL if selected * * Typically used for Ethernet * reference clock @@ -132,7 +132,7 @@ typedef enum ALT_CLK_e * * Input Pin */ - + /* PLLs */ ALT_CLK_MAIN_PLL, /*!< \b main_pll_ref_clkin @@ -142,7 +142,7 @@ typedef enum ALT_CLK_e */ ALT_CLK_PERIPHERAL_PLL, - /*!< \b periph_pll_ref_clkin + /*!< \b periph_pll_ref_clkin * Peripheral PLL input reference * clock, used to designate the * Peripheral PLL in PLL clock @@ -236,7 +236,7 @@ typedef enum ALT_CLK_e ALT_CLK_L4_SP, /*!< \b l4_sp_clk - * Clock for L4 slave peripherals (SP) bus + * Clock for L4 slave peripherals (SP) bus */ ALT_CLK_DBG_BASE, @@ -279,14 +279,14 @@ typedef enum ALT_CLK_e */ ALT_CLK_MAIN_NAND_SDMMC, - /*!< \b main_nand_sdmmc_clk + /*!< \b main_nand_sdmmc_clk * Main PLL C4 Output. Input clock to * flash controller clocks block. * * Alias for \e ALT_CLK_MAIN_PLL_C4 */ ALT_CLK_CFG, - /*!< \b cfg_clk + /*!< \b cfg_clk * FPGA manager configuration clock. */ @@ -295,7 +295,7 @@ typedef enum ALT_CLK_e * Clock to FPGA fabric */ - + /* Peripherals Clock Group - The following clocks are derived from the Peripheral PLL */ ALT_CLK_PERIPHERAL_PLL_C0, /*!< \b Peripheral PLL C0 Output */ @@ -556,7 +556,7 @@ typedef enum ALT_CLK_PLL_LOCK_STATUS_e * assertion conditions. * * \param lock_stat_mask - * Specifies the PLL lock status conditions to clear. \e lock_stat_mask + * Specifies the PLL lock status conditions to clear. \e lock_stat_mask * is a mask of logically OR'ed \ref ALT_CLK_PLL_LOCK_STATUS_t * values designating the PLL lock conditions to clear. * @@ -588,12 +588,12 @@ uint32_t alt_clk_lock_status_get(void); * * \retval ALT_E_TRUE The specified PLL is currently locked. * \retval ALT_E_FALSE The specified PLL is currently not locked. - * \retval ALT_E_BAD_ARG The \e pll argument designates a non PLL clock + * \retval ALT_E_BAD_ARG The \e pll argument designates a non PLL clock * value. * \internal * NOTE: This function uses the * * \b hps::clkmgr::inter::mainplllocked - * * \b hps::clkmgr::inter::perplllocked, + * * \b hps::clkmgr::inter::perplllocked, * * \b hps::clkmgr::inter::sdrplllocked * * bits to determine if the PLL is locked or not. @@ -612,30 +612,30 @@ ALT_STATUS_CODE alt_clk_pll_is_locked(ALT_CLK_t pll); * request from the reset manager sets the safe mode bit in the clock manager * control register. No other control register bits are affected by the safe * mode request from the reset manager. - * + * * While in safe mode, clock manager register settings which control clock * behavior are not changed. However, the output of the registers which control * the clock manager state are forced to the safe mode values such that the * following conditions occur: * * All PLLs are bypassed to the \b osc1_clk clock, including their counters. * * Clock dividers select their default reset values. - * * The flash controllers source clock selections are set to the peripheral + * * The flash controllers source clock selections are set to the peripheral * PLL. * * All clocks are enabled. * * Safe mode is optionally applied to debug clocks. - * + * * A write by software is the only way to clear the safe mode bit. All registers * and clocks need to be configured correctly and all software-managed clocks * need to be gated off before clearing safe mode. Software can then gate clocks * on as required. - * + * * On cold reset, all clocks are put in safe mode. - * + * * On warm reset, safe mode is optionally and independently applied to debug * clocks and normal (i.e.non-debug) clocks based on clock manager register * settings. The default response for warm reset is to put all clocks in safe * mode. - * + * * The APIs in this group provide control of the Clock Manager safe mode warm * reset response behavior. * @{ @@ -651,12 +651,12 @@ typedef enum ALT_CLK_SAFE_DOMAIN_e /*! * This enumeration literal specifies the normal safe mode domain. The * normal domain consists of all clocks except debug clocks. - */ + */ ALT_CLK_DOMAIN_NORMAL, /*! * This enumeration literal specifies the debug safe mode domain. The debug * domain consists of all debug clocks. - */ + */ ALT_CLK_DOMAIN_DEBUG } ALT_CLK_SAFE_DOMAIN_t; @@ -703,7 +703,7 @@ bool alt_clk_is_in_safe_mode(ALT_CLK_SAFE_DOMAIN_t clk_domain); * * In summary, the PLL bypass controls permit: * * Each PLL to be individually bypassed. - * * Bypass of all PLL clock outputs to \b osc1_clk or alternatively the PLLs + * * Bypass of all PLL clock outputs to \b osc1_clk or alternatively the PLLs * reference clock input source reference clock selection. * * Isolation of a the PLL VCO frequency registers (multiplier and divider), phase shift registers (negative phase) , and post scale counters. @@ -720,7 +720,7 @@ bool alt_clk_is_in_safe_mode(ALT_CLK_SAFE_DOMAIN_t clk_domain); * * \retval ALT_E_SUCCESS The operation was succesful. * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The \e pll argument specified a non PLL clock + * \retval ALT_E_BAD_ARG The \e pll argument specified a non PLL clock * value. */ ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll); @@ -751,7 +751,7 @@ ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, /*! * Return whether the specified PLL is in bypass or not. * - * \internal + * \internal * This function must also test the \b clkmgr.ctrl.safemode bit in * addition to the PLLs bypass bit to tell whether the bypass mode is * effect or not. @@ -762,7 +762,7 @@ ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, * * \retval ALT_E_TRUE The PLL is in bypass mode. * \retval ALT_E_FALSE The PLL is not in bypass mode. - * \retval ALT_E_BAD_ARG The \e pll argument designates a non PLL clock + * \retval ALT_E_BAD_ARG The \e pll argument designates a non PLL clock * value. */ ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll); @@ -824,7 +824,7 @@ ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll); * * \retval ALT_E_SUCCESS The operation was succesful. * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock + * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock * value. */ ALT_STATUS_CODE alt_clk_clock_disable(ALT_CLK_t clk); @@ -839,7 +839,7 @@ ALT_STATUS_CODE alt_clk_clock_disable(ALT_CLK_t clk); * * \retval ALT_E_SUCCESS The operation was succesful. * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock + * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock * value. */ ALT_STATUS_CODE alt_clk_clock_enable(ALT_CLK_t clk); @@ -853,7 +853,7 @@ ALT_STATUS_CODE alt_clk_clock_enable(ALT_CLK_t clk); * * \retval ALT_E_TRUE The clock is enabled. * \retval ALT_E_FALSE The clock is not enabled. - * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock + * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock * value. */ ALT_STATUS_CODE alt_clk_is_enabled(ALT_CLK_t clk); @@ -912,12 +912,12 @@ ALT_STATUS_CODE alt_clk_is_enabled(ALT_CLK_t clk); * Get the input reference clock source selection value for the specified clock * or PLL. * - * NOTE: This function returns a clock value even though \e clk may specify a - * clock that does not have a selectable input reference clock source. In - * this case, the clock value returned is the static clock source for the + * NOTE: This function returns a clock value even though \e clk may specify a + * clock that does not have a selectable input reference clock source. In + * this case, the clock value returned is the static clock source for the * specified clock. For example calling alt_clk_source_get() with \e clk * set to \ref ALT_CLK_MAIN_PLL will return \ref ALT_CLK_OSC1. - * + * * \param clk * The clock or PLL to retrieve the input reference clock source * selection value for. @@ -939,14 +939,14 @@ ALT_CLK_t alt_clk_source_get(ALT_CLK_t clk); * * \retval ALT_E_SUCCESS The operation was succesful. * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The \e clk argument designates a clock that - * does not have a selectable input reference + * \retval ALT_E_BAD_ARG The \e clk argument designates a clock that + * does not have a selectable input reference * clock source. - * \retval ALT_E_INV_OPTION The \e ref_clk argument designates a clock that - * is an invalid reference clock source for the + * \retval ALT_E_INV_OPTION The \e ref_clk argument designates a clock that + * is an invalid reference clock source for the * specified clock. */ -ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk, +ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk, ALT_CLK_t ref_clk); /*! @} */ @@ -981,7 +981,7 @@ ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk, * \retval ALT_E_SUCCESS The operation was succesful. * \retval ALT_E_ERROR The operation failed. * \retval ALT_E_BAD_ARG A bad argument value was passed. Either the \e clk - * argument is bad or not a valid external clock + * argument is bad or not a valid external clock * source * \retval ALT_E_ARG_RANGE The frequency value violates the range constraints * for the specified clock. @@ -1018,17 +1018,17 @@ alt_freq_t alt_clk_ext_clk_freq_get(ALT_CLK_t clk); typedef struct ALT_CLK_PLL_CFG_s { ALT_CLK_t ref_clk; /*!< PLL Reference Clock Source */ - uint32_t mult; /*!< VCO Frequency Configuration - + uint32_t mult; /*!< VCO Frequency Configuration - * Multiplier (M) value, range 1 to 4096 */ - uint32_t div; /*!< VCO Frequency Configuration - + uint32_t div; /*!< VCO Frequency Configuration - * Divider (N) value, range 1 to 64 */ uint32_t cntrs[6]; /*!< Post-Scale Counters (C0 - C5) - * range 1 to 512 */ uint32_t pshift[6]; /*!< Phase Shift - 1/8 (45 degrees) of - * negative phase shift per increment, + * negative phase shift per increment, * range 0 to 4096 */ } ALT_CLK_PLL_CFG_t; @@ -1262,7 +1262,7 @@ ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk, * The following interrupt request (IRQ) signals are sourced from the Clock * Manager: * - * * \b clkmgr_IRQ - Clock Manager lock status interrupt output. The PLL lock + * * \b clkmgr_IRQ - Clock Manager lock status interrupt output. The PLL lock * status interrupt is the logical \e OR of six interrupt * sources defining the loss or achievement of lock status for * each PLL. The six PLL lock status conditions are: @@ -1275,7 +1275,7 @@ ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk, * * They are enumeratated by the type \ref ALT_CLK_PLL_LOCK_STATUS_t. * - * Each PLL lock condition may be individually disabled/enabled + * Each PLL lock condition may be individually disabled/enabled * as a contributor to the determination of the \b clkmgr_IRQ * assertion status. * @@ -1283,7 +1283,7 @@ ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk, * the PLL lock conditions causing the \b clkmgr_IRQ * assertion. * - * * \b mpuwakeup_IRQ - MPU wakeup interrupt output. This interrupt notifies the + * * \b mpuwakeup_IRQ - MPU wakeup interrupt output. This interrupt notifies the * MPU to "wake up" after a transition of the Main PLL into * or out of bypass mode has been safely achieved. The need * for the "wake up" notification is because the PLL clocks @@ -1368,14 +1368,14 @@ ALT_STATUS_CODE alt_clk_irq_enable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask); * * A known good clock group configuration may be generated by one of the * following methods: - * - * * As static design information generated by an ACDS clock configuration tool + * + * * As static design information generated by an ACDS clock configuration tool * and passed to embedded software for dynamic loading. - * + * * * By calling alt_clk_group_cfg_raw_get() at run-time from an SoC FPGA that has * programmatically established a known good clock group configuration using * the clock manager API configuration functions. - * + * * @{ */ @@ -1407,7 +1407,7 @@ ALT_STATUS_CODE alt_clk_group_cfg_raw_get(ALT_CLK_GRP_t clk_group, * * This function is used to safely set the configuration state of a clock * group from a raw clock group configuration specification. The raw clock - * group configuration specification may be a configuration previously + * group configuration specification may be a configuration previously * captured with alt_clk_group_cfg_raw_get() or a group clock configuration * generated by an external utility. * @@ -1422,10 +1422,13 @@ ALT_STATUS_CODE alt_clk_group_cfg_raw_get(ALT_CLK_GRP_t clk_group, */ ALT_STATUS_CODE alt_clk_group_cfg_raw_set(const ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg); +ALT_STATUS_CODE alt_clk_clkmgr_init(void); + /*! @} */ /*! @} */ #ifdef __cplusplus } + #endif /* __cplusplus */ #endif /* __ALT_CLK_MGR_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_generalpurpose_io.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_generalpurpose_io.h index d8a38f5347..0a7abaef8e 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_generalpurpose_io.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_generalpurpose_io.h @@ -5,20 +5,20 @@ /****************************************************************************** * * Copyright 2013 Altera Corporation. All Rights Reserved. -* +* * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* +* * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* +* * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* +* * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. -* +* * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO @@ -29,7 +29,7 @@ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY * OF SUCH DAMAGE. -* +* ******************************************************************************/ #ifndef __ALT_GPIO_H__ @@ -57,8 +57,8 @@ extern "C" { /******************************************************************************/ /*! \addtogroup ALT_GPIO_API The General Purpose Input/Output Manager API * - * This module defines the General Purpose Input/Output Manager API for - * accessing, configuring, and controlling the General Purpose Input/Output + * This module defines the General Purpose Input/Output Manager API for + * accessing, configuring, and controlling the General Purpose Input/Output * Manager resources. These include both the general-purpose GPIO signals and * the input-only GPI signals that are shared with the DDR interface.\n \n * The GPIO API presents two views or perspectives of the GPIO signals. The first @@ -100,7 +100,7 @@ extern "C" { */ /******************************************************************************/ /*! - * This type definition enumerates the data direction (input or output) of + * This type definition enumerates the data direction (input or output) of * the GPIO signals. */ @@ -114,7 +114,7 @@ typedef enum ALT_GPIO_PIN_DIR_e /******************************************************************************/ /*! - * This type definition enumerates the type of interrupt source + * This type definition enumerates the type of interrupt source * (level-triggered or edge-triggered) of the GPIO signals. */ @@ -128,7 +128,7 @@ typedef enum ALT_GPIO_PIN_TYPE_e /******************************************************************************/ /*! - * This type definition enumerates the polarity of the interrupt sources + * This type definition enumerates the polarity of the interrupt sources * (falling-edge or rising-edge for edge-triggered interrupts, active-low or * active-high for level-triggered interrupts) of the GPIO signals. */ @@ -193,7 +193,7 @@ typedef enum ALT_GPIO_PIN_DATA_e /******************************************************************************/ /*! - * This type definition enumerates the GPIO ports that the GPIO manager + * This type definition enumerates the GPIO ports that the GPIO manager * handles. */ @@ -208,7 +208,7 @@ typedef enum ALT_GPIO_PORT_e * \b Port \b B - 29-bit GPIO port B. */ ALT_GPIO_PORTB, - + /*! * \b Port \b C - 29-bit GPIO port C. \n 13 bits are used for GPIO signals, * 14 bits are used for GPI-only signals that are shared @@ -224,12 +224,12 @@ typedef enum ALT_GPIO_PORT_e ALT_GPIO_PORT_UNKNOWN } ALT_GPIO_PORT_t; - + /******************************************************************************/ /*! * This type definition enumerates the individual bits within the GPIO ports - * used by the GPIO manager. The bit-ordering must match the hardware - * bit-ordering. Since the ordering and packing of bitfields is not + * used by the GPIO manager. The bit-ordering must match the hardware + * bit-ordering. Since the ordering and packing of bitfields is not * standardized in C/C++, the following are defined as masks. \n * For example, to set bits 3 and 4 of GPIO port B outputs (assuming the bits * had previously been set to outputs), the user could use the syntax: \par @@ -310,20 +310,38 @@ typedef enum ALT_GPIO_PORTBIT_e /******************************************************************************/ /*! - * Sets the specified GPIO data bits to use the data direction(s) + * Initialize the GPIO modules before use + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_gpio_init(void); + +/******************************************************************************/ +/*! + * Uninitialize the GPIO modules & return to reset state + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_gpio_uninit(void); + +/******************************************************************************/ +/*! + * Sets the specified GPIO data bits to use the data direction(s) * specified. * * * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to apply this - * operation to. Other bits (where mask bits equal zero) are + * The group of bits (where mask bits equal one) to apply this + * operation to. Other bits (where mask bits equal zero) are * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to * configure all data direction bits of the port. * \param config * The data-directions of the bits to be set in this operation. - * Individual bits are: \n \b 0 - Use as an input (default). \n + * Individual bits are: \n \b 0 - Use as an input (default). \n * \b 1 - Use as an output. * * \retval ALT_E_SUCCESS The operation was successful. @@ -335,18 +353,18 @@ ALT_STATUS_CODE alt_gpio_port_datadir_set(ALT_GPIO_PORT_t gpio_pid, /******************************************************************************/ /*! - * Returns the data direction configuration of selected bits of the + * Returns the data direction configuration of selected bits of the * specified GPIO module. * * \param gpio_pid * The GPIO port identifier. * \param mask * The group of bits (where mask bits equal one) to read and - * return. Other bits (where mask bits equal zero) are returned + * return. Other bits (where mask bits equal zero) are returned * as zero. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to * return all data direction bits of the port. * - * \retval uint32_t \n Individual bits are: \n \b 0 - The signal is + * \retval uint32_t \n Individual bits are: \n \b 0 - The signal is * configured as an input. * \n \b 1 - The signal is configured as an output. * @@ -367,7 +385,7 @@ uint32_t alt_gpio_port_datadir_get(ALT_GPIO_PORT_t gpio_pid, * operation to. Other bits (mask bits equal zero) are * not changed. * \param val - * The 32-bit word to write to the GPIO outputs. Only the 29 LSBs + * The 32-bit word to write to the GPIO outputs. Only the 29 LSBs * are used. Setting the three MSBs causes an error. * * \retval ALT_E_SUCCESS The operation was successful. @@ -387,8 +405,8 @@ ALT_STATUS_CODE alt_gpio_port_data_write(ALT_GPIO_PORT_t gpio_pid, * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to return. Other - * bits (where mask bits equal zero) are returned as zero. Specify + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all data bits of * the port. * @@ -408,21 +426,21 @@ uint32_t alt_gpio_port_data_read(ALT_GPIO_PORT_t gpio_pid, uint32_t mask); */ /******************************************************************************/ /*! - * Sets edge-triggered or level-triggered interrupt configuration for the + * Sets edge-triggered or level-triggered interrupt configuration for the * specified signals of the specified GPIO module. * * * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to apply this + * The group of bits (where mask bits equal one) to apply this * operation to. Other bits (where mask bits equal zero) are * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to * configure all interrupt type bits of the port. * \param config - * The interrupt configuration to write. Individual bits - * are: \n \b 0 - Set the - * interrupt for this bit to be level-sensitive (default). \n \b + * The interrupt configuration to write. Individual bits + * are: \n \b 0 - Set the + * interrupt for this bit to be level-sensitive (default). \n \b * 1 - Set the interrupt for this bit to be edge-sensitive. * * \retval ALT_E_SUCCESS The operation was successful. @@ -434,20 +452,20 @@ ALT_STATUS_CODE alt_gpio_port_int_type_set(ALT_GPIO_PORT_t gpio_pid, /******************************************************************************/ /*! - * Returns the interrupt configuration (edge-triggered or level-triggered) for - * the specified bits of the specified GPIO module. + * Returns the interrupt configuration (edge-triggered or level-triggered) for + * the specified bits of the specified GPIO module. * * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to return. Other - * bits (where mask bits equal zero) are returned as zero. Specify + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all configuration * bits of the port. * \retval uint32_t - * The current interrupt source configuration. Individual bits - * are: \n \b 0 - The interrupt for this bit is set to be - * level-sensitive. \n \b 1 - + * The current interrupt source configuration. Individual bits + * are: \n \b 0 - The interrupt for this bit is set to be + * level-sensitive. \n \b 1 - * The interrupt for this bit is set to be edge-sensitive. * */ @@ -463,12 +481,12 @@ uint32_t alt_gpio_port_int_type_get(ALT_GPIO_PORT_t gpio_pid, * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to apply this + * The group of bits (where mask bits equal one) to apply this * operation to. Other bits (where mask bits equal zero) are * not changed. * \param config - * The interrupt polarity configuration to set. Individual bits - * are: \n \b 0 - Set the interrupt polarity for this bit to + * The interrupt polarity configuration to set. Individual bits + * are: \n \b 0 - Set the interrupt polarity for this bit to * active-low or falling-edge mode (default). \n \b 1 - Set the * interrupt polarity for this bit to active-high or rising-edge mode. * @@ -481,21 +499,21 @@ ALT_STATUS_CODE alt_gpio_port_int_pol_set(ALT_GPIO_PORT_t gpio_pid, /******************************************************************************/ /*! - * Returns the active-high or active-low polarity configuration for the + * Returns the active-high or active-low polarity configuration for the * possible interrupt sources of the specified GPIO module. * * * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to return. Other - * bits (where mask bits equal zero) are returned as zero. Specify + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all the * configuration bits of the port. - * + * * \retval uint32_t - * The current polarity configuration. Individual bits are: \n - * \b 0 = The interrupt polarity for this bit is set to + * The current polarity configuration. Individual bits are: \n + * \b 0 = The interrupt polarity for this bit is set to * active-low or falling-edge mode. \n \b 1 = The interrupt * polarity for this bit is set to active-high or rising-edge mode. * @@ -512,7 +530,7 @@ uint32_t alt_gpio_port_int_pol_get(ALT_GPIO_PORT_t gpio_pid, */ /******************************************************************************/ /*! - * Sets the debounce configuration for input signals of the specified GPIO + * Sets the debounce configuration for input signals of the specified GPIO * module. If debounce is selected, metastability flip-flops are inserted to * debounce signals presented to the GPIO inputs. A signal must be steady for * two periods of the gpio_db_clk clock before it is considered valid. The @@ -521,13 +539,13 @@ uint32_t alt_gpio_port_int_pol_get(ALT_GPIO_PORT_t gpio_pid, * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to apply this + * The group of bits (where mask bits equal one) to apply this * operation to. Other bits (where mask bits equal zero) are * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to * configure the debounce setting for all bits of the port. * \param config * The debounce configuration to set. Individual bits are: \n - * \b 0 - Debounce is not selected for this signal (default). \n + * \b 0 - Debounce is not selected for this signal (default). \n * \b 1 - Debounce is selected for this signal. * * \retval ALT_E_SUCCESS The operation was successful. @@ -546,14 +564,14 @@ ALT_STATUS_CODE alt_gpio_port_debounce_set(ALT_GPIO_PORT_t gpio_pid, * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to return. Other - * bits (where mask bits equal zero) are returned as zero. Specify + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all debounce * configuration bits of the port. - * + * * \retval uint32_t - * The current debounce configuration.Individual bits are: \n - * \b 0 - Debounce is not selected for this signal. \n \b 1 - + * The current debounce configuration.Individual bits are: \n + * \b 0 - Debounce is not selected for this signal. \n \b 1 - * Debounce is selected for this signal. * */ @@ -562,8 +580,8 @@ uint32_t alt_gpio_port_debounce_get(ALT_GPIO_PORT_t gpio_pid, /******************************************************************************/ /*! - * Sets the synchronization configuration for the signals of the specified - * GPIO register. This allows for synchronizing level-sensitive interrupts to + * Sets the synchronization configuration for the signals of the specified + * GPIO register. This allows for synchronizing level-sensitive interrupts to * an internal clock signal. This is a port-wide option that controls all * level-sensitive interrupt signals of that GPIO port. * @@ -572,7 +590,7 @@ uint32_t alt_gpio_port_debounce_get(ALT_GPIO_PORT_t gpio_pid, * \param config * \n \b Any \b non-zero \b value - Synchronize to internal clock signal. * \n \b Zero - Do not synchronize to internal clock signal. - * + * * * \retval ALT_E_SUCCESS The operation was successful. * \retval ALT_E_ERROR The operation failed. @@ -584,8 +602,8 @@ ALT_STATUS_CODE alt_gpio_port_sync_set(ALT_GPIO_PORT_t gpio_pid, /******************************************************************************/ /*! * - * Returns the synchronization configuration for the signals of the - * specified GPIO register. This allows for synchronizing level-sensitive + * Returns the synchronization configuration for the signals of the + * specified GPIO register. This allows for synchronizing level-sensitive * interrupts to the internal clock signal. This is a port-wide option that * controls all level-sensitive interrupt signals of that GPIO port. * @@ -605,7 +623,7 @@ ALT_STATUS_CODE alt_gpio_port_sync_get(ALT_GPIO_PORT_t gpio_pid); /*! * Configures a group of GPIO signals with identical setup parameters. Allows * for configuring all parameters of a given port at one time. - * + * * \param gpio_pid * The GPIO port identifier. * \param mask @@ -621,11 +639,11 @@ ALT_STATUS_CODE alt_gpio_port_sync_get(ALT_GPIO_PORT_t gpio_pid); * Debounce signals or not. * \param data * Set the data output to this value. - * + * * \retval ALT_E_SUCCESS The operation was successful. * \retval ALT_E_ERROR The operation failed. * \retval ALT_E_BAD_ARG Invalid input argument. - + */ ALT_STATUS_CODE alt_gpio_port_config(ALT_GPIO_PORT_t gpio_pid, uint32_t mask, ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type, @@ -699,11 +717,11 @@ uint32_t alt_gpio_port_int_enable_get(ALT_GPIO_PORT_t gpio_pid); * \param gpio_pid * The GPIO port identifier. * \param mask - * Which bits to change among the port \n \b 0 = + * Which bits to change among the port \n \b 0 = * Do not change this bit. \n \b 1 = Allow this bit to change. * \param val - * The interrupt mask to write. Individual bits are: \n \b 0 = - * Do not mask the interrupt for this bit (default). \n \b 1 = + * The interrupt mask to write. Individual bits are: \n \b 0 = + * Do not mask the interrupt for this bit (default). \n \b 1 = * Mask the interrupt for this bit. * * \retval ALT_E_SUCCESS The operation was successful. @@ -720,10 +738,10 @@ ALT_STATUS_CODE alt_gpio_port_int_mask_set(ALT_GPIO_PORT_t gpio_pid, * * \param gpio_pid * The GPIO port identifier. - * + * * \retval uint32_t - * The interrupt mask that was read. Individual bits are: \n - * \b 0 = The interrupt for this bit is not masked. \n \b 1 = The + * The interrupt mask that was read. Individual bits are: \n + * \b 0 = The interrupt for this bit is not masked. \n \b 1 = The * interrupt for this bit is masked. * */ @@ -731,16 +749,16 @@ uint32_t alt_gpio_port_int_mask_get(ALT_GPIO_PORT_t gpio_pid); /******************************************************************************/ /*! - * Returns the interrupt pending status of all signals of the specified GPIO + * Returns the interrupt pending status of all signals of the specified GPIO * register. * * * \param gpio_pid * The GPIO port identifier. - + * \retval uint32_t - * The current interrupt pending status. Individual bits are: \n - * \b 0 - The interrupt for this bit is not pending. \n \b 1 - + * The current interrupt pending status. Individual bits are: \n + * \b 0 - The interrupt for this bit is not pending. \n \b 1 - * The interrupt for this bit is pending. * */ @@ -748,15 +766,15 @@ uint32_t alt_gpio_port_int_status_get(ALT_GPIO_PORT_t gpio_pid); /******************************************************************************/ /*! - * Clear the interrupt pending status of selected signals of the + * Clear the interrupt pending status of selected signals of the * specified GPIO register. * * * \param gpio_pid * The GPIO port identifier. * \param clrmask - * The interrupt bits to clear. Individual bits are: \n \b 0 - - * The interrupt for this bit will not be changed. \n \b 1 - + * The interrupt bits to clear. Individual bits are: \n \b 0 - + * The interrupt for this bit will not be changed. \n \b 1 - * The interrupt for this bit will be cleared. * * \retval ALT_E_SUCCESS The operation was successful. @@ -1029,7 +1047,7 @@ typedef struct ALT_GPIO_PIN_RECORD_s /******************************************************************************/ /*! * Configures all parameters for one bit (signal) of the GPIO ports. - * + * * \param signal_num * The GPIO port signal index. * \param dir @@ -1043,7 +1061,7 @@ typedef struct ALT_GPIO_PIN_RECORD_s * \param data * If the GPIO signal is set to be an output, set it to * this value - * + * * \retval ALT_E_SUCCESS The operation was successful. * \retval ALT_E_ERROR The operation failed. * \retval ALT_E_BAD_ARG Invalid input argument. @@ -1056,78 +1074,78 @@ ALT_STATUS_CODE alt_gpio_bit_config(ALT_GPIO_1BIT_t signal_num, /******************************************************************************/ /*! * Returns the configuration parameters of a given GPIO bit. - * + * * \param signal_num * The GPIO port signal index. * \param config * Pointer to a single GPIO_CONFIG_RECORD_s configuration record. * The fields of this configuration record are filled in - * by the function. - * + * by the function. + * * \retval ALT_E_SUCCESS The operation was successful. * \retval ALT_E_ERROR The operation failed. * \retval ALT_E_BAD_ARG Invalid input argument. - + */ ALT_STATUS_CODE alt_gpio_bitconfig_get(ALT_GPIO_1BIT_t signal_num, ALT_GPIO_CONFIG_RECORD_t *config); /******************************************************************************/ /*! - * Configures a list of GPIO bits. The GPIO bits do not have to be - * configured the same, as was the case for the mask version of this function, + * Configures a list of GPIO bits. The GPIO bits do not have to be + * configured the same, as was the case for the mask version of this function, * alt_gpio_port_config(). Each bit may be configured differently and bits may * be listed in any order. - * + * * \param config_array * Pointer to an array of GPIO_CONFIG_RECORD_s configuration * records. These definitions contain all the parameters - * needed to set up the listed pins. All or - * any subset of the GPIO signals can be configured. Signals do - * not have to be listed in numerical order or be unique. If a - * signal number is listed multiple times, the last configuration + * needed to set up the listed pins. All or + * any subset of the GPIO signals can be configured. Signals do + * not have to be listed in numerical order or be unique. If a + * signal number is listed multiple times, the last configuration * listed is used. \n Configuration terminates either when \b len * signals have been configured or if the next signal number index * in the array is equal to \b ALT_END_OF_GPIO_SIGNALS (-1). - * + * * \param len - * Length of array to configure. - * + * Length of array to configure. + * * \retval ALT_E_SUCCESS The operation was successful. * \retval ALT_E_ERROR The operation failed. * \retval ALT_E_BAD_ARG Invalid input argument. - + */ ALT_STATUS_CODE alt_gpio_group_config(ALT_GPIO_CONFIG_RECORD_t* config_array, uint32_t len); /******************************************************************************/ /*! - * Returns a list of the pin signal indices and the associated configuration + * Returns a list of the pin signal indices and the associated configuration * settings (data direction, interrupt type, polarity, and debounce) of that * list of signals. - * + * * \param config_array * Pointer to an array of ALT_GPIO_CONFIG_RECORD_t configuration * records. Only the signal indices in the first field of each * configuration record need be filled in. This function will * fill in all the other fields of the configuration record, * returning all configuration parameters in the array. - * Signals do not have to be listed in numerical order or be - * unique. If a signal number is listed multiple times, the + * Signals do not have to be listed in numerical order or be + * unique. If a signal number is listed multiple times, the * configuration record will contain multiple entries for * that signal. \n Configuration reading terminates either when * \b len signal configurations have been read or if the next * signal number index in the array is equal to * \b ALT_END_OF_GPIO_SIGNALS (-1). * \param len - * Length of configuration array to read and return. - * - * + * Length of configuration array to read and return. + * + * * \retval ALT_E_SUCCESS The operation was successful. * \retval ALT_E_ERROR The operation failed. * \retval ALT_E_BAD_ARG Invalid input argument. - + */ ALT_STATUS_CODE alt_gpio_group_config_get(ALT_GPIO_CONFIG_RECORD_t *config_array, uint32_t len); @@ -1140,30 +1158,30 @@ ALT_STATUS_CODE alt_gpio_group_config_get(ALT_GPIO_CONFIG_RECORD_t *config_array * alt_gpio_group_config_get() is this version follows a separate list of * signal indices instead of having the signal list provided in the first * field of the configuration records in the array. - * + * * \param pinid_array * Pointer to a list of signal index numbers. These indices * are copied to the first field of each configuration record * in the returned array. * \param config_array * Pointer to an array of ALT_GPIO_CONFIG_RECORD_t configuration - * records. This function will fill in the fields of the - * configuration record, returning all configuration parameters - * in the array. Signals do not have to be listed in numerical - * order or be unique. If a signal number is listed multiple - * times, the configuration record array will contain multiple + * records. This function will fill in the fields of the + * configuration record, returning all configuration parameters + * in the array. Signals do not have to be listed in numerical + * order or be unique. If a signal number is listed multiple + * times, the configuration record array will contain multiple * identical entries for that signal. \n Configuration reading * terminates either when \b len signal configurations have been * read or if the next signal number index in the array is equal * to \b ALT_END_OF_GPIO_SIGNALS (-1). * \param len - * Length of configuration array to read. - * - * + * Length of configuration array to read. + * + * * \retval ALT_E_SUCCESS The operation was successful. * \retval ALT_E_ERROR The operation failed. * \retval ALT_E_BAD_ARG Invalid input argument. - * + * */ ALT_STATUS_CODE alt_gpio_group_config_get2(ALT_GPIO_1BIT_t* pinid_array, ALT_GPIO_CONFIG_RECORD_t *config_array, uint32_t len); @@ -1218,10 +1236,10 @@ ALT_GPIO_PORTBIT_t alt_gpio_bit_to_port_pin(ALT_GPIO_1BIT_t pin_num); /******************************************************************************/ /*! - * Extracts the GPIO Signal Index Number from the supplied GPIO port ID and - * signal mask. If passed a bitmask composed of more than one signal, the + * Extracts the GPIO Signal Index Number from the supplied GPIO port ID and + * signal mask. If passed a bitmask composed of more than one signal, the * signal number of the lowest bit in the bitmask presented is returned. - * + * */ ALT_GPIO_1BIT_t alt_gpio_port_pin_to_bit(ALT_GPIO_PORT_t pid, uint32_t bitmask); diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_hwlibs_ver.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_hwlibs_ver.h index 57f0f0d6ad..7596d50d66 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_hwlibs_ver.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_hwlibs_ver.h @@ -36,17 +36,21 @@ * ***********************************************************************/ -/* This is the major revision of the Altera ACDS Release */ +/* This is the major revision of the Altera ACDS Release */ #define ALTERA_ACDS_MAJOR_REV 13 -/* This is the minor revision of the Altera ACDS Release */ -#define ALTERA_ACDS_MINOR_REV 0 +/* This is the minor revision of the Altera ACDS Release */ +#define ALTERA_ACDS_MINOR_REV 1 -/* This is an internal HwLibs revision control code. */ -/* End-users should NOT depend upon the value of this field */ +/* This is an internal HwLibs revision/feature control code. */ +/* End-users should NOT depend upon the value of this field */ #define ALTERA_HWLIBS_REV 0 /* This is a text string containing the current release and service pack IDs */ -#define ALTERA_ACDS_REV_STR "13.0SP1" +#define ALTERA_ACDS_REV_STR "13.1" + +/* This is a text string containing the current SoC EDS ID */ +#define ALTERA_SOCEDS_REV_STR "Altera SoC Embedded Design Suite v13.1" + #endif /* __ALT_HWLIBS_VER_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h index db1e6dd4f5..004fd3188c 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h @@ -343,6 +343,8 @@ typedef enum ALT_INT_INTERRUPT_e ALT_INT_INTERRUPT_SPI3_IRQ = 189, /*!< * Interrupts sourced from the SPI Controllers 0 - 3. + * SPI0_IRQ corresponds to SPIM0. SPI1_IRQ corresponds to SPIM1. + * SPI2_IRQ corresponds to SPIS0. SPI3_IRQ corresponds to SPIS1. * * All interrupts in this group are level triggered. */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_reset_manager.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_reset_manager.h index 7b0da342fb..d719e3f05e 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_reset_manager.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_reset_manager.h @@ -239,6 +239,48 @@ ALT_STATUS_CODE alt_reset_warm_reset(uint32_t warm_reset_delay, bool fpga_handshake, bool etr_stall); +#if 0 +/*! \addtogroup RST_MGR_MPU + * + * This functional group provides reset control for the Cortex-A9 MPU module. + * + * @{ + */ + +/*! @} */ + +/*! \addtogroup RST_MGR_PERIPH + * + * This functional group provides inidividual reset control for the HPS + * peripheral modules. + * + * @{ + */ + +/*! @} */ + +/*! \addtogroup RST_MGR_BRG + * + * This functional group provides inidividual reset control for the bridge + * interfaces between the HPS and FPGA. + * + * @{ + */ + +/*! @} */ + +/*! \addtogroup RST_MGR_MISC + * + * This functional group provides inidividual reset control for miscellaneous + * HPS modules. + * + * @{ + */ + +/*! @} */ + +#endif + /*! @} */ /*! @} */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/hwlib.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/hwlib.h index 7a3bbfdce9..aba7e877c4 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/hwlib.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/hwlib.h @@ -91,7 +91,6 @@ typedef int32_t ALT_STATUS_CODE; /*! The buffer does not contain enough free space for the operation. */ #define ALT_E_BUF_OVF (-20) - /*! * Indicates a FALSE condition. */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_acpidmap.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_acpidmap.h new file mode 100644 index 0000000000..3a6bf0fffa --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_acpidmap.h @@ -0,0 +1,3569 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_ACPIDMAP */ + +#ifndef __ALTERA_ALT_ACPIDMAP_H__ +#define __ALTERA_ALT_ACPIDMAP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : ACP ID Mapper Registers - ALT_ACPIDMAP + * ACP ID Mapper Registers + * + * Registers in the ACP ID Mapper module + * + */ +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 2 - vid2rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x1 | ARUSER value to SCU for ID=2 + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x4 | Remap Master ID = DAP ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x1 | Force Mapping for ID=2 + * + */ +/* + * Field : ARUSER value to SCU for ID=2 - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2RD. + */ +struct ALT_ACPIDMAP_VID2RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU for ID=2 */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID = DAP ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping for ID=2 */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2RD. */ +typedef volatile struct ALT_ACPIDMAP_VID2RD_s ALT_ACPIDMAP_VID2RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2RD_OFST 0x0 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 2 - vid2wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x1 | AWUSER value to SCU for ID=2 + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x4 | Remap Master ID = DAP ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x1 | Force Mapping for ID=2 + * + */ +/* + * Field : AWUSER value to SCU for ID=2 - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2WR. + */ +struct ALT_ACPIDMAP_VID2WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU for ID=2 */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID = DAP ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping for ID=2 */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2WR. */ +typedef volatile struct ALT_ACPIDMAP_VID2WR_s ALT_ACPIDMAP_VID2WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2WR_OFST 0x4 + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 3 - vid3rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3RD. + */ +struct ALT_ACPIDMAP_VID3RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3RD. */ +typedef volatile struct ALT_ACPIDMAP_VID3RD_s ALT_ACPIDMAP_VID3RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3RD_OFST 0x8 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 3 - vid3wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3WR. + */ +struct ALT_ACPIDMAP_VID3WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3WR. */ +typedef volatile struct ALT_ACPIDMAP_VID3WR_s ALT_ACPIDMAP_VID3WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3WR_OFST 0xc + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 4 - vid4rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4RD. + */ +struct ALT_ACPIDMAP_VID4RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4RD. */ +typedef volatile struct ALT_ACPIDMAP_VID4RD_s ALT_ACPIDMAP_VID4RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4RD_OFST 0x10 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 4 - vid4wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4WR. + */ +struct ALT_ACPIDMAP_VID4WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4WR. */ +typedef volatile struct ALT_ACPIDMAP_VID4WR_s ALT_ACPIDMAP_VID4WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4WR_OFST 0x14 + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 5 - vid5rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5RD. + */ +struct ALT_ACPIDMAP_VID5RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5RD. */ +typedef volatile struct ALT_ACPIDMAP_VID5RD_s ALT_ACPIDMAP_VID5RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5RD_OFST 0x18 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 5 - vid5wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5WR. + */ +struct ALT_ACPIDMAP_VID5WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5WR. */ +typedef volatile struct ALT_ACPIDMAP_VID5WR_s ALT_ACPIDMAP_VID5WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5WR_OFST 0x1c + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 6 - vid6rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6RD. + */ +struct ALT_ACPIDMAP_VID6RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6RD. */ +typedef volatile struct ALT_ACPIDMAP_VID6RD_s ALT_ACPIDMAP_VID6RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6RD_OFST 0x20 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 6 - vid6wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6WR. + */ +struct ALT_ACPIDMAP_VID6WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6WR. */ +typedef volatile struct ALT_ACPIDMAP_VID6WR_s ALT_ACPIDMAP_VID6WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6WR_OFST 0x24 + +/* + * Register : Read AXI Master Mapping Register for Dynamic Virtual ID Remap - dynrd + * + * The Read AXI Master Mapping Register contains the USER, and ADDR page signals + * mapping values for transaction that dynamically remapped to one of the available + * 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNRD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNRD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNRD. + */ +struct ALT_ACPIDMAP_DYNRD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNRD. */ +typedef volatile struct ALT_ACPIDMAP_DYNRD_s ALT_ACPIDMAP_DYNRD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNRD register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNRD_OFST 0x28 + +/* + * Register : Write AXI Master Mapping Register for Dynamic Virtual ID Remap - dynwr + * + * The Write AXI Master Mapping Register contains the USER, and ADDR page signals + * mapping values for transaction that dynamically remapped to one of the available + * 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNWR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNWR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNWR. + */ +struct ALT_ACPIDMAP_DYNWR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNWR. */ +typedef volatile struct ALT_ACPIDMAP_DYNWR_s ALT_ACPIDMAP_DYNWR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNWR register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNWR_OFST 0x2c + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 2 - vid2rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | 0x1 | ARUSER value to SCU for ID=2 (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | 0x4 | Remap Master ID = DAP ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | 0x1 | Force Mapping for ID=2 (Status) + * + */ +/* + * Field : ARUSER value to SCU for ID=2 (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2RD_S. + */ +struct ALT_ACPIDMAP_VID2RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU for ID=2 (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID = DAP ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping for ID=2 (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID2RD_S_s ALT_ACPIDMAP_VID2RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2RD_S_OFST 0x30 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 2 - vid2wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | 0x1 | AWUSER value to SCU for ID=2 (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | 0x4 | Remap Master ID = DAP ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | 0x1 | Force Mapping for ID=2 (Status) + * + */ +/* + * Field : AWUSER value to SCU for ID=2 (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2WR_S. + */ +struct ALT_ACPIDMAP_VID2WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU for ID=2 (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID = DAP ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping for ID=2 (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID2WR_S_s ALT_ACPIDMAP_VID2WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2WR_S_OFST 0x34 + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 3 - vid3rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3RD_S. + */ +struct ALT_ACPIDMAP_VID3RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID3RD_S_s ALT_ACPIDMAP_VID3RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3RD_S_OFST 0x38 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 3 - vid3wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3WR_S. + */ +struct ALT_ACPIDMAP_VID3WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID3WR_S_s ALT_ACPIDMAP_VID3WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3WR_S_OFST 0x3c + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 4 - vid4rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4RD_S. + */ +struct ALT_ACPIDMAP_VID4RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID4RD_S_s ALT_ACPIDMAP_VID4RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4RD_S_OFST 0x40 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 4 - vid4wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4WR_S. + */ +struct ALT_ACPIDMAP_VID4WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID4WR_S_s ALT_ACPIDMAP_VID4WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4WR_S_OFST 0x44 + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 5 - vid5rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5RD_S. + */ +struct ALT_ACPIDMAP_VID5RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID5RD_S_s ALT_ACPIDMAP_VID5RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5RD_S_OFST 0x48 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 5 - vid5wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5WR_S. + */ +struct ALT_ACPIDMAP_VID5WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID5WR_S_s ALT_ACPIDMAP_VID5WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5WR_S_OFST 0x4c + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 6 - vid6rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6RD_S. + */ +struct ALT_ACPIDMAP_VID6RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID6RD_S_s ALT_ACPIDMAP_VID6RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6RD_S_OFST 0x50 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 6 - vid6wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6WR_S. + */ +struct ALT_ACPIDMAP_VID6WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID6WR_S_s ALT_ACPIDMAP_VID6WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6WR_S_OFST 0x54 + +/* + * Register : Read AXI Master Mapping Status Register for Dynamic Virtual ID Remap - dynrd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, and + * ADDR page signals mapping values for transaction that dynamically remapped to + * one of the available 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_S_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_S_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_S_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNRD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNRD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNRD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNRD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNRD_S. + */ +struct ALT_ACPIDMAP_DYNRD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNRD_S. */ +typedef volatile struct ALT_ACPIDMAP_DYNRD_S_s ALT_ACPIDMAP_DYNRD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNRD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNRD_S_OFST 0x58 + +/* + * Register : Write AXI Master Mapping Status Register for Dynamic Virtual ID Remap - dynwr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, and + * ADDR page signals mapping values for transaction that dynamically remapped to + * one of the available 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_S_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_S_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_S_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNWR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNWR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNWR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNWR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNWR_S. + */ +struct ALT_ACPIDMAP_DYNWR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNWR_S. */ +typedef volatile struct ALT_ACPIDMAP_DYNWR_S_s ALT_ACPIDMAP_DYNWR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNWR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNWR_S_OFST 0x5c + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_ACPIDMAP. + */ +struct ALT_ACPIDMAP_s +{ + volatile ALT_ACPIDMAP_VID2RD_t vid2rd; /* ALT_ACPIDMAP_VID2RD */ + volatile ALT_ACPIDMAP_VID2WR_t vid2wr; /* ALT_ACPIDMAP_VID2WR */ + volatile ALT_ACPIDMAP_VID3RD_t vid3rd; /* ALT_ACPIDMAP_VID3RD */ + volatile ALT_ACPIDMAP_VID3WR_t vid3wr; /* ALT_ACPIDMAP_VID3WR */ + volatile ALT_ACPIDMAP_VID4RD_t vid4rd; /* ALT_ACPIDMAP_VID4RD */ + volatile ALT_ACPIDMAP_VID4WR_t vid4wr; /* ALT_ACPIDMAP_VID4WR */ + volatile ALT_ACPIDMAP_VID5RD_t vid5rd; /* ALT_ACPIDMAP_VID5RD */ + volatile ALT_ACPIDMAP_VID5WR_t vid5wr; /* ALT_ACPIDMAP_VID5WR */ + volatile ALT_ACPIDMAP_VID6RD_t vid6rd; /* ALT_ACPIDMAP_VID6RD */ + volatile ALT_ACPIDMAP_VID6WR_t vid6wr; /* ALT_ACPIDMAP_VID6WR */ + volatile ALT_ACPIDMAP_DYNRD_t dynrd; /* ALT_ACPIDMAP_DYNRD */ + volatile ALT_ACPIDMAP_DYNWR_t dynwr; /* ALT_ACPIDMAP_DYNWR */ + volatile ALT_ACPIDMAP_VID2RD_S_t vid2rd_s; /* ALT_ACPIDMAP_VID2RD_S */ + volatile ALT_ACPIDMAP_VID2WR_S_t vid2wr_s; /* ALT_ACPIDMAP_VID2WR_S */ + volatile ALT_ACPIDMAP_VID3RD_S_t vid3rd_s; /* ALT_ACPIDMAP_VID3RD_S */ + volatile ALT_ACPIDMAP_VID3WR_S_t vid3wr_s; /* ALT_ACPIDMAP_VID3WR_S */ + volatile ALT_ACPIDMAP_VID4RD_S_t vid4rd_s; /* ALT_ACPIDMAP_VID4RD_S */ + volatile ALT_ACPIDMAP_VID4WR_S_t vid4wr_s; /* ALT_ACPIDMAP_VID4WR_S */ + volatile ALT_ACPIDMAP_VID5RD_S_t vid5rd_s; /* ALT_ACPIDMAP_VID5RD_S */ + volatile ALT_ACPIDMAP_VID5WR_S_t vid5wr_s; /* ALT_ACPIDMAP_VID5WR_S */ + volatile ALT_ACPIDMAP_VID6RD_S_t vid6rd_s; /* ALT_ACPIDMAP_VID6RD_S */ + volatile ALT_ACPIDMAP_VID6WR_S_t vid6wr_s; /* ALT_ACPIDMAP_VID6WR_S */ + volatile ALT_ACPIDMAP_DYNRD_S_t dynrd_s; /* ALT_ACPIDMAP_DYNRD_S */ + volatile ALT_ACPIDMAP_DYNWR_S_t dynwr_s; /* ALT_ACPIDMAP_DYNWR_S */ + volatile uint32_t _pad_0x60_0x1000[1000]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_ACPIDMAP. */ +typedef volatile struct ALT_ACPIDMAP_s ALT_ACPIDMAP_t; +/* The struct declaration for the raw register contents of register group ALT_ACPIDMAP. */ +struct ALT_ACPIDMAP_raw_s +{ + volatile uint32_t vid2rd; /* ALT_ACPIDMAP_VID2RD */ + volatile uint32_t vid2wr; /* ALT_ACPIDMAP_VID2WR */ + volatile uint32_t vid3rd; /* ALT_ACPIDMAP_VID3RD */ + volatile uint32_t vid3wr; /* ALT_ACPIDMAP_VID3WR */ + volatile uint32_t vid4rd; /* ALT_ACPIDMAP_VID4RD */ + volatile uint32_t vid4wr; /* ALT_ACPIDMAP_VID4WR */ + volatile uint32_t vid5rd; /* ALT_ACPIDMAP_VID5RD */ + volatile uint32_t vid5wr; /* ALT_ACPIDMAP_VID5WR */ + volatile uint32_t vid6rd; /* ALT_ACPIDMAP_VID6RD */ + volatile uint32_t vid6wr; /* ALT_ACPIDMAP_VID6WR */ + volatile uint32_t dynrd; /* ALT_ACPIDMAP_DYNRD */ + volatile uint32_t dynwr; /* ALT_ACPIDMAP_DYNWR */ + volatile uint32_t vid2rd_s; /* ALT_ACPIDMAP_VID2RD_S */ + volatile uint32_t vid2wr_s; /* ALT_ACPIDMAP_VID2WR_S */ + volatile uint32_t vid3rd_s; /* ALT_ACPIDMAP_VID3RD_S */ + volatile uint32_t vid3wr_s; /* ALT_ACPIDMAP_VID3WR_S */ + volatile uint32_t vid4rd_s; /* ALT_ACPIDMAP_VID4RD_S */ + volatile uint32_t vid4wr_s; /* ALT_ACPIDMAP_VID4WR_S */ + volatile uint32_t vid5rd_s; /* ALT_ACPIDMAP_VID5RD_S */ + volatile uint32_t vid5wr_s; /* ALT_ACPIDMAP_VID5WR_S */ + volatile uint32_t vid6rd_s; /* ALT_ACPIDMAP_VID6RD_S */ + volatile uint32_t vid6wr_s; /* ALT_ACPIDMAP_VID6WR_S */ + volatile uint32_t dynrd_s; /* ALT_ACPIDMAP_DYNRD_S */ + volatile uint32_t dynwr_s; /* ALT_ACPIDMAP_DYNWR_S */ + volatile uint32_t _pad_0x60_0x1000[1000]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_ACPIDMAP. */ +typedef volatile struct ALT_ACPIDMAP_raw_s ALT_ACPIDMAP_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_ACPIDMAP_H__ */ + diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/socal.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/socal.h index b0375e5fa1..f6090cd0ca 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/socal.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/socal.h @@ -1,39 +1,50 @@ -/******************************************************************************* -* * -* Copyright 2013 Altera Corporation. All Rights Reserved. * -* * -* Redistribution and use in source and binary forms, with or without * -* modification, are permitted provided that the following conditions are met: * -* * -* 1. Redistributions of source code must retain the above copyright notice, * -* this list of conditions and the following disclaimer. * -* * -* 2. Redistributions in binary form must reproduce the above copyright notice, * -* this list of conditions and the following disclaimer in the documentation * -* and/or other materials provided with the distribution. * -* * -* 3. The name of the author may not be used to endorse or promote products * -* derived from this software without specific prior written permission. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * -* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * -* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * -* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * -* * -*******************************************************************************/ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + /*! \file Altera - ALT_SOCAL */ #ifndef __ALTERA_SOCAL_H__ #define __ALTERA_SOCAL_H__ -#include <rtems/score/basedefs.h> +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#include <cstddef> +#include <cstdbool> +#include <cstdint> +#else /* __cplusplus */ +#include <stddef.h> +#include <stdbool.h> +#include <stdint.h> +#endif /* __cplusplus */ +#endif /* __ASSEMBLY__ */ #ifdef __cplusplus extern "C" @@ -61,7 +72,6 @@ extern "C" #define ALT_CAST(type, ptr) ((type) (ptr)) #endif /* __ASSEMBLY__ */ - /*! * \addtogroup ALT_SOCAL_UTIL_RW_FUNC SoCAL Memory Read/Write Utilities * @@ -239,117 +249,8 @@ extern "C" */ #define alt_replbits_dword(dest, msk, src) (alt_write_dword(dest,(alt_read_dword(dest) & ~(msk)) | ((src) & (msk)))) - - /*! @} */ -/*! - * \addtogroup ALT_SOCAL_TYPE_IND_FUNC SoCAL Indirect (pointer-based) Utilities - * - * This section implements two other useful forms of the alt_write_*() macros above that - * are preferable to use in some situations. These use an intermediate pointer (defined - * in the containing compile unit) to move data in an indirect manner. These compile to very - * tight ARM code, equivalent to the above versions. - * - * @{ - */ - -/*! Write the 8 bit byte to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to byte data - * \param src - 8 bit data value to write to memory - */ -#define alt_indwrite_byte(dest, tmptr, src) {(tmptr)=ALT_CAST(uint8_t*,(dest));(*ALT_CAST(volatile uint8_t*,(tmptr))=(src));} - -/*! Write the 8 bit byte to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to byte data - * \param src - Read destination pointer address - */ -#define alt_indread_byte(dest, tmptr, src) {(tmptr)=ALT_CAST(uint8_t*,(src));(*ALT_CAST(volatile uint8_t*,(dest))=*(tmptr));} - -/*! Write the 16 bit halfword to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to halfword data - * \param src - 16 bit data value to write to memory - */ -#define alt_indwrite_hword(dest, tmptr, src) {(tmptr)=ALT_CAST(uint16_t*,(dest));(*ALT_CAST(volatile uint16_t*,(tmptr))=(src));} - -/*! Write the 16 bit halfword to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to halfword data - * \param src - Read destination pointer address - */ -#define alt_indread_hword(dest, tmptr, src) {(tmptr)=ALT_CAST(uint16_t*,(src));(*ALT_CAST(volatile uint16_t*,(dest))=*(tmptr));} - -/*! Write the 32 bit word to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to word data - * \param src - 32 bit data value to write to memory - */ -#define alt_indwrite_word(dest, tmptr, src) {(tmptr)=ALT_CAST(uint32_t*,(dest));(*ALT_CAST(volatile uint32_t*,(tmptr))=(src));} - -/*! Write the 32 bit word to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to word data - * \param src - Read destination pointer address - */ -#define alt_indread_word(dest, tmptr, src) {(tmptr)=ALT_CAST(uint32_t*,(src));(*ALT_CAST(volatile uint32_t*,(dest))=*(tmptr));} - -/*! Write the 64 bit dword to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to double-word data - * \param src - 64 bit data value to write to memory - */ -#define alt_indwrite_dword(dest, tmptr, src) {(tmptr)=ALT_CAST(uint64_t*,(dest));(*ALT_CAST(volatile uint64_t*,(tmptr))=(src));} - -/*! Write the 64 bit dword to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to double-word data - * \param src - Read destination pointer address - */ -#define alt_indread_dword(dest, tmptr, src) {(tmptr)=ALT_CAST(uint64_t*,(src));(*ALT_CAST(volatile uint64_t*,(dest))=*(tmptr));} - - -/*! @} */ - -/*! - * \addtogroup ALT_SOCAL_CMPL_ASRT_FUNC SoCAL Compile Assert Utilities - * - * This section implements an assert-type functionality in the compiler rather than in the - * debug run-time code. Additional macros can be built on the basic structure and defined - * to test various conditions and throw a compile-time error if necessary. - * - * @{ - */ - -/*! alt_cat_compile_assert_text() concatenates text. - * \param txta - The first text fragment to be joined - * \param txtb - The second text fragment to be joined - */ -#define alt_cat_compile_assert_text(txta, txtb) txta##txtb - -/*! alt_form_compile_assert_line() is the basis of other functions that check various - * conditions and possibly throw a compile-time error in response, giving an - * assert equivalent that operates at compile time rather than at run-time. - * \param test - Any valid boolean expression - * \param file - The filename where this expression is located (ASCII string) - * \param line - The line number where this expression is located - */ -#define alt_form_compile_assert_line(test, file, line) \ -typedef char alt_cat_compile_assert_text(assertion_at_##file##_line_, line)[2*!!(test)-1] - -/*! alt_check_struct_size() throws a compile-time error if the structure size (a) is - * larger than the size of the reference (b). \n - * alt_check_struct_size() works with groups of bitfields up to much larger - * structure sizes. - * \param a - Structure to be evaluated - * \param b - Reference size - */ -#define alt_check_struct_size(a, b) RTEMS_STATIC_ASSERT((sizeof(a) <= sizeof(b)), Invalid_stuct_size) - - -/*! @} */ /*! @} */ #ifdef __cplusplus diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_address_space.c b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_address_space.c index 43d7576232..93b7f8866d 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_address_space.c +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_address_space.c @@ -1,45 +1,49 @@ - /****************************************************************************** -* -* alt_address_space.c - API for the Altera SoC FPGA address space. -* -******************************************************************************/ + * + * alt_address_space.c - API for the Altera SoC FPGA address space. + * + ******************************************************************************/ /****************************************************************************** -* -* Copyright 2013 Altera Corporation. All Rights Reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of the author may not be used to endorse or promote products -* derived from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -* OF SUCH DAMAGE. -* -******************************************************************************/ + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ #include <stddef.h> #include "alt_address_space.h" #include "socal/alt_l3.h" #include "socal/socal.h" +#include "socal/alt_acpidmap.h" +#include "hwlib.h" + +#define ALT_ACP_ID_MAX_INPUT_ID 7 +#define ALT_ACP_ID_MAX_OUTPUT_ID 4096 /******************************************************************************/ ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr, @@ -154,7 +158,7 @@ ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start, { // Address filtering start and end values must be 1 MB aligned. if ( (addr_filt_start & ~L2_CACHE_ADDR_FILTERING_START_ADDR_MASK) - || (addr_filt_end & ~L2_CACHE_ADDR_FILTERING_END_ADDR_MASK) ) + || (addr_filt_end & ~L2_CACHE_ADDR_FILTERING_END_ADDR_MASK) ) { return ALT_E_ARG_RANGE; } @@ -181,4 +185,325 @@ ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start, } /******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_fixed_read_set(const uint32_t input_id, + const uint32_t output_id, + const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t aruser) +{ + if (input_id > ALT_ACP_ID_OUT_DYNAM_ID_7 || output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + alt_write_word(ALT_ACPIDMAP_VID2RD_ADDR, + ALT_ACPIDMAP_VID2RD_MID_SET(input_id) + | ALT_ACPIDMAP_VID2RD_PAGE_SET(page) + | ALT_ACPIDMAP_VID2RD_USER_SET(aruser) + | ALT_ACPIDMAP_VID2RD_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + alt_write_word(ALT_ACPIDMAP_VID3RD_ADDR, + ALT_ACPIDMAP_VID3RD_MID_SET(input_id) + | ALT_ACPIDMAP_VID3RD_PAGE_SET(page) + | ALT_ACPIDMAP_VID3RD_USER_SET(aruser) + | ALT_ACPIDMAP_VID3RD_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + alt_write_word(ALT_ACPIDMAP_VID4RD_ADDR, + ALT_ACPIDMAP_VID4RD_MID_SET(input_id) + | ALT_ACPIDMAP_VID4RD_PAGE_SET(page) + | ALT_ACPIDMAP_VID4RD_USER_SET(aruser) + | ALT_ACPIDMAP_VID4RD_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + alt_write_word(ALT_ACPIDMAP_VID5RD_ADDR, + ALT_ACPIDMAP_VID5RD_MID_SET(input_id) + | ALT_ACPIDMAP_VID5RD_PAGE_SET(page) + | ALT_ACPIDMAP_VID5RD_USER_SET(aruser) + | ALT_ACPIDMAP_VID5RD_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + alt_write_word(ALT_ACPIDMAP_VID6RD_ADDR, + ALT_ACPIDMAP_VID6RD_MID_SET(input_id) + | ALT_ACPIDMAP_VID6RD_PAGE_SET(page) + | ALT_ACPIDMAP_VID6RD_USER_SET(aruser) + | ALT_ACPIDMAP_VID6RD_FORCE_SET(1UL)); + break; + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_fixed_write_set(const uint32_t input_id, + const uint32_t output_id, + const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t awuser) +{ + if (input_id > ALT_ACP_ID_OUT_DYNAM_ID_7 || output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + alt_write_word(ALT_ACPIDMAP_VID2WR_ADDR, + ALT_ACPIDMAP_VID2WR_MID_SET(input_id) + | ALT_ACPIDMAP_VID2WR_PAGE_SET(page) + | ALT_ACPIDMAP_VID2WR_USER_SET(awuser) + | ALT_ACPIDMAP_VID2WR_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + alt_write_word(ALT_ACPIDMAP_VID3WR_ADDR, + ALT_ACPIDMAP_VID3WR_MID_SET(input_id) + | ALT_ACPIDMAP_VID3WR_PAGE_SET(page) + | ALT_ACPIDMAP_VID3WR_USER_SET(awuser) + | ALT_ACPIDMAP_VID3WR_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + alt_write_word(ALT_ACPIDMAP_VID4WR_ADDR, + ALT_ACPIDMAP_VID4WR_MID_SET(input_id) + | ALT_ACPIDMAP_VID4WR_PAGE_SET(page) + | ALT_ACPIDMAP_VID4WR_USER_SET(awuser) + | ALT_ACPIDMAP_VID4WR_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + alt_write_word(ALT_ACPIDMAP_VID5WR_ADDR, + ALT_ACPIDMAP_VID5WR_MID_SET(input_id) + | ALT_ACPIDMAP_VID5WR_PAGE_SET(page) + | ALT_ACPIDMAP_VID5WR_USER_SET(awuser) + | ALT_ACPIDMAP_VID5WR_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + alt_write_word(ALT_ACPIDMAP_VID6WR_ADDR, + ALT_ACPIDMAP_VID6WR_MID_SET(input_id) + | ALT_ACPIDMAP_VID6WR_PAGE_SET(page) + | ALT_ACPIDMAP_VID6WR_USER_SET(awuser) + | ALT_ACPIDMAP_VID6WR_FORCE_SET(1UL) + ); + break; + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_dynamic_read_set(const uint32_t output_id) +{ + if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + uint32_t aruser, page; + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + aruser = ALT_ACPIDMAP_VID2RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_ADDR)); + page = ALT_ACPIDMAP_VID2RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + aruser = ALT_ACPIDMAP_VID3RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_ADDR)); + page = ALT_ACPIDMAP_VID3RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + aruser = ALT_ACPIDMAP_VID4RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_ADDR)); + page = ALT_ACPIDMAP_VID4RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + aruser = ALT_ACPIDMAP_VID5RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_ADDR)); + page = ALT_ACPIDMAP_VID5RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + aruser = ALT_ACPIDMAP_VID6RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_ADDR)); + page = ALT_ACPIDMAP_VID6RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_ADDR)); + break; + default: + return ALT_E_BAD_ARG; + } + + alt_write_word(ALT_ACPIDMAP_DYNRD_ADDR, + ALT_ACPIDMAP_DYNRD_PAGE_SET(page) + | ALT_ACPIDMAP_DYNRD_USER_SET(aruser)); + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id) +{ + if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + uint32_t awuser, page; + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + awuser = ALT_ACPIDMAP_VID2WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR)); + page = ALT_ACPIDMAP_VID2WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + awuser = ALT_ACPIDMAP_VID3WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR)); + page = ALT_ACPIDMAP_VID3WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + awuser = ALT_ACPIDMAP_VID4WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR)); + page = ALT_ACPIDMAP_VID4WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + awuser = ALT_ACPIDMAP_VID5WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR)); + page = ALT_ACPIDMAP_VID5WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + awuser = ALT_ACPIDMAP_VID6WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR)); + page = ALT_ACPIDMAP_VID6WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR)); + break; + default: + return ALT_E_BAD_ARG; + } + + alt_write_word(ALT_ACPIDMAP_DYNWR_ADDR, + ALT_ACPIDMAP_DYNWR_PAGE_SET(page) + | ALT_ACPIDMAP_DYNWR_USER_SET(awuser)); + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_dynamic_read_options_set(const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t aruser) +{ + alt_write_word(ALT_ACPIDMAP_DYNRD_ADDR, + ALT_ACPIDMAP_DYNRD_PAGE_SET(page) + | ALT_ACPIDMAP_DYNRD_USER_SET(aruser)); + return ALT_E_SUCCESS; +} + /******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_dynamic_write_options_set(const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t awuser) +{ + alt_write_word(ALT_ACPIDMAP_DYNWR_ADDR, + ALT_ACPIDMAP_DYNWR_PAGE_SET(page) + | ALT_ACPIDMAP_DYNWR_USER_SET(awuser)); + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_read_options_get(const uint32_t output_id, + bool * fixed, + uint32_t * input_id, + ALT_ACP_ID_MAP_PAGE_t * page, + uint32_t * aruser) +{ + if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + *aruser = ALT_ACPIDMAP_VID2RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID2RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID2RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID2RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + *aruser = ALT_ACPIDMAP_VID3RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID3RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID3RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID3RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + *aruser = ALT_ACPIDMAP_VID4RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID4RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID4RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID4RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + *aruser = ALT_ACPIDMAP_VID5RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID5RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID5RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID5RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + *aruser = ALT_ACPIDMAP_VID6RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID6RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID6RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID6RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_7: + *aruser = ALT_ACPIDMAP_DYNRD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_DYNRD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_DYNRD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_DYNRD_S_ADDR)); + break; + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id, + bool * fixed, + uint32_t * input_id, + ALT_ACP_ID_MAP_PAGE_t * page, + uint32_t * awuser) +{ + if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + *awuser = ALT_ACPIDMAP_VID2WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID2WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID2WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID2WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + *awuser = ALT_ACPIDMAP_VID3WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID3WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID3WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID3WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + *awuser = ALT_ACPIDMAP_VID4WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID4WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID4WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID4WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + *awuser = ALT_ACPIDMAP_VID5WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID5WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID5WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID5WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + *awuser = ALT_ACPIDMAP_VID6WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID6WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID6WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID6WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_7: + *awuser = ALT_ACPIDMAP_DYNWR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_DYNWR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR)); + break; + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; +} diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_clock_manager.c b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_clock_manager.c index c731ad36bb..12912437c6 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_clock_manager.c +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_clock_manager.c @@ -1,46 +1,44 @@ /****************************************************************************** -* -* Copyright 2013 Altera Corporation. All Rights Reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of the author may not be used to endorse or promote products -* derived from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -* OF SUCH DAMAGE. -* -******************************************************************************/ - - -#include <stdint.h> -#include <stdlib.h> -#include <stdbool.h> -#include <string.h> -#include <assert.h> - -#include "socal/hps.h" -#include "socal/socal.h" -#include "socal/alt_sysmgr.h" -#include "hwlib.h" -#include "alt_clock_manager.h" -#include "alt_mpu_registers.h" + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include <stdint.h> +#include <stdlib.h> +#include <stdbool.h> +#include <stdio.h> + +#include "socal/hps.h" +#include "socal/socal.h" +#include "socal/alt_sysmgr.h" +#include "hwlib.h" +#include "alt_clock_manager.h" +#include "alt_mpu_registers.h" #define UINT12_MAX (4096) @@ -77,10 +75,13 @@ typedef struct ALT_EXT_CLK_PARAMBLOK_s /* contains the current activity state of the clock, 1=active, 0=inactive. */ /* Values taken from Section 2.3 and Section 2.7.1 of the HHP HPS-Clocking */ /* NPP specification. */ -static ALT_EXT_CLK_PARAMBLOK_t alt_ext_clk_paramblok = {{25000000, 10000000, 50000000, 0, 1}, - {25000000, 10000000, 50000000, 0, 1}, - {0, 10000000, 50000000, 0, 1}, - {0, 10000000, 50000000, 0, 1}}; +static ALT_EXT_CLK_PARAMBLOK_t alt_ext_clk_paramblok = +{ + { 25000000, 10000000, 50000000, 0, 1 }, + { 25000000, 10000000, 50000000, 0, 1 }, + { 0, 10000000, 50000000, 0, 1 }, + { 0, 10000000, 50000000, 0, 1 } +}; /* PLL frequency limits */ @@ -104,12 +105,15 @@ typedef struct ALT_PLL_CLK_PARAMBLOK_s #define ALT_ORIGINAL_GUARDBAND_VAL 20 #define ALT_GUARDBAND_LIMIT 20 -static ALT_PLL_CLK_PARAMBLOK_t alt_pll_clk_paramblok = {{0, 320000000, 1200000000, ALT_ORIGINAL_GUARDBAND_VAL, 0}, - {0, 320000000, 900000000, ALT_ORIGINAL_GUARDBAND_VAL, 0}, - {0, 320000000, 800000000, ALT_ORIGINAL_GUARDBAND_VAL, 0}, - {0, 320000000, 1600000000, ALT_ORIGINAL_GUARDBAND_VAL, 1}, - {0, 320000000, 1250000000, ALT_ORIGINAL_GUARDBAND_VAL, 1}, - {0, 320000000, 1066000000, ALT_ORIGINAL_GUARDBAND_VAL, 1}}; +static ALT_PLL_CLK_PARAMBLOK_t alt_pll_clk_paramblok = +{ + { 0, 320000000, 1200000000, ALT_ORIGINAL_GUARDBAND_VAL, 0 }, + { 0, 320000000, 900000000, ALT_ORIGINAL_GUARDBAND_VAL, 0 }, + { 0, 320000000, 800000000, ALT_ORIGINAL_GUARDBAND_VAL, 0 }, + { 0, 320000000, 1600000000, ALT_ORIGINAL_GUARDBAND_VAL, 1 }, + { 0, 320000000, 1250000000, ALT_ORIGINAL_GUARDBAND_VAL, 1 }, + { 0, 320000000, 1066000000, ALT_ORIGINAL_GUARDBAND_VAL, 1 } +}; /* PLL counter frequency limits */ @@ -133,25 +137,69 @@ typedef struct ALT_PLL_CNTR_FREQMAX_s alt_freq_t SDRAMPLL_C5; // SDRAM PLL Counter 5 parameter block } ALT_PLL_CNTR_FREQMAX_t; +// +// The following pll max frequency array statically defined must be recalculated each time +// when powering up, by calling alt_clk_clkmgr_init() +// +// for 14.1 uboot preloader, the following values are calculated dynamically. +// +// Arrial 5 +// alt_pll_cntr_maxfreq.MainPLL_C0 = 1050000000 +// alt_pll_cntr_maxfreq.MainPLL_C1 = 350000000 +// alt_pll_cntr_maxfreq.MainPLL_C2 = 262500000 +// alt_pll_cntr_maxfreq.MainPLL_C3 = 350000000 +// alt_pll_cntr_maxfreq.MainPLL_C4 = 2050781 +// alt_pll_cntr_maxfreq.MainPLL_C5 = 116666666 +// alt_pll_cntr_maxfreq.PeriphPLL_C0 = 1953125 +// alt_pll_cntr_maxfreq.PeriphPLL_C1 = 250000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C2 = 1953125 +// alt_pll_cntr_maxfreq.PeriphPLL_C3 = 200000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C4 = 200000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C5 = 1953125 +// alt_pll_cntr_maxfreq.SDRAMPLL_C0 = 533333333 +// alt_pll_cntr_maxfreq.SDRAMPLL_C1 = 1066666666 +// alt_pll_cntr_maxfreq.SDRAMPLL_C2 = 533333333 +// alt_pll_cntr_maxfreq.SDRAMPLL_C5 = 177777777 + +// Cyclone V +// alt_pll_cntr_maxfreq.MainPLL_C0 = 925000000 +// alt_pll_cntr_maxfreq.MainPLL_C1 = 370000000 +// alt_pll_cntr_maxfreq.MainPLL_C2 = 462500000 +// alt_pll_cntr_maxfreq.MainPLL_C3 = 370000000 +// alt_pll_cntr_maxfreq.MainPLL_C4 = 3613281 +// alt_pll_cntr_maxfreq.MainPLL_C5 = 123333333 +// alt_pll_cntr_maxfreq.PeriphPLL_C0 = 1953125 +// alt_pll_cntr_maxfreq.PeriphPLL_C1 = 250000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C2 = 1953125 +// alt_pll_cntr_maxfreq.PeriphPLL_C3 = 200000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C4 = 200000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C5 = 1953125 +// alt_pll_cntr_maxfreq.SDRAMPLL_C0 = 400000000 +// alt_pll_cntr_maxfreq.SDRAMPLL_C1 = 800000000 +// alt_pll_cntr_maxfreq.SDRAMPLL_C2 = 400000000 +// alt_pll_cntr_maxfreq.SDRAMPLL_C5 = 133333333 /* Initializes the PLL Counter output maximum frequency block */ -static ALT_PLL_CNTR_FREQMAX_t alt_pll_cntr_maxfreq = {800000000, /* Main PLL Outputs */ - 400000000, - 400000000, - 432000000, - 250000000, - 125000000, - 250000000, /* Peripheral PLL Outputs */ - 250000000, - 432000000, - 250000000, - 200000000, - 100000000, /* SDRAM PLL Outputs */ - 533000000, - 1066000000, - 533000000, - 200000000 }; +static ALT_PLL_CNTR_FREQMAX_t alt_pll_cntr_maxfreq = +{ + 800000000, /* Main PLL Outputs */ + 400000000, + 400000000, + 432000000, + 250000000, + 125000000, + 250000000, /* Peripheral PLL Outputs */ + 250000000, + 432000000, + 250000000, + 200000000, + 100000000, /* SDRAM PLL Outputs */ + 533000000, + 1066000000, + 533000000, + 200000000 +}; @@ -181,6 +229,18 @@ static ALT_PLL_CNTR_FREQMAX_t alt_pll_cntr_maxfreq = {800000000, /* Main PLL & ALT_CLKMGR_INTREN_SDRPLLLOST_CLR_MSK) +// Undocumented register which determines clock dividers for main PLL C0, C1, and C2. These should be considered RO. +#define ALT_CLKMGR_ALTERA_OFST 0xe0 +#define ALT_CLKMGR_ALTERA_MPUCLK_OFST 0x0 +#define ALT_CLKMGR_ALTERA_MAINCLK_OFST 0x4 +#define ALT_CLKMGR_ALTERA_DBGATCLK_OFST 0x8 +#define ALT_CLKMGR_ALTERA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_ALTERA_OFST)) +#define ALT_CLKMGR_ALTERA_MPUCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ALTERA_ADDR) + ALT_CLKMGR_ALTERA_MPUCLK_OFST)) +#define ALT_CLKMGR_ALTERA_MAINCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ALTERA_ADDR) + ALT_CLKMGR_ALTERA_MAINCLK_OFST)) +#define ALT_CLKMGR_ALTERA_DBGATCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ALTERA_ADDR) + ALT_CLKMGR_ALTERA_DBGATCLK_OFST)) +#define ALT_CLKMGR_ALTERA_MPUCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +#define ALT_CLKMGR_ALTERA_MAINCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +#define ALT_CLKMGR_ALTERA_DBGATCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Utility functions ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ @@ -199,7 +259,7 @@ static ALT_PLL_CNTR_FREQMAX_t alt_pll_cntr_maxfreq = {800000000, /* Main PLL /* minimum osc1 clock cycle delay. */ /****************************************************************************************/ -static void inline alt_clk_mgr_wait(void* reg, uint32_t cnt) +inline static void alt_clk_mgr_wait(void* reg, uint32_t cnt) { for (; cnt ; cnt--) { @@ -207,7 +267,6 @@ static void inline alt_clk_mgr_wait(void* reg, uint32_t cnt) } } - /* Wait time constants */ /* These values came from Section 4.9.4 of the HHP HPS-Clocking NPP document */ #define ALT_SW_MANAGED_CLK_WAIT_CTRDIV 30 /* 30 or more MPU clock cycles */ @@ -224,8 +283,7 @@ static void inline alt_clk_mgr_wait(void* reg, uint32_t cnt) // how many loops to wait for the SDRAM clock to come around // to zero and allow for writing a new divisor ratio to it - -static ALT_STATUS_CODE alt_clk_plls_settle_wait(void) +ALT_STATUS_CODE alt_clk_plls_settle_wait(void) { int32_t i = ALT_BYPASS_TIMEOUT_CNT; bool nofini; @@ -238,26 +296,30 @@ static ALT_STATUS_CODE alt_clk_plls_settle_wait(void) return (i > 0) ? ALT_E_SUCCESS : ALT_E_ERROR; } - - -static ALT_STATUS_CODE alt_clk_pll_lock_wait(ALT_CLK_t pll, uint32_t cnt) +static ALT_STATUS_CODE alt_clk_pll_lock_wait(ALT_CLK_t pll, uint32_t timeout) { - ALT_STATUS_CODE ret = ALT_E_ERROR; - uint32_t temp; - uint32_t mask = 0; + uint32_t locked_mask = 0; + + if (pll == ALT_CLK_MAIN_PLL) { locked_mask = ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK; } + else if (pll == ALT_CLK_PERIPHERAL_PLL) { locked_mask = ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK; } + else if (pll == ALT_CLK_SDRAM_PLL) { locked_mask = ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK; } + else + { + return ALT_E_BAD_ARG; + } - if (pll == ALT_CLK_MAIN_PLL) { mask = ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK; } - else if (pll == ALT_CLK_PERIPHERAL_PLL) { mask = ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK; } - else if (pll == ALT_CLK_SDRAM_PLL) { mask = ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK; } - else { return ret; } do { - temp = alt_read_word(ALT_CLKMGR_INTER_ADDR); - } while (!(temp & mask) && --cnt); - if (cnt > 0) { ret = ALT_E_SUCCESS; } - return ret; -} + uint32_t int_status = alt_read_word(ALT_CLKMGR_INTER_ADDR); + if (int_status & locked_mask) + { + return ALT_E_SUCCESS; + } + + } while (timeout--); + return ALT_E_TMO; +} /* Useful utility macro for checking if two values */ /* are within a certain percentage of each other */ @@ -321,25 +383,23 @@ static void alt_clk_pllcounter_write(void* vcoaddr, void* stataddr, void* cntrad /* conditions. */ /****************************************************************************************/ - ALT_STATUS_CODE alt_clk_lock_status_clear(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask) +ALT_STATUS_CODE alt_clk_lock_status_clear(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask) { - ALT_STATUS_CODE ret; - - if (lock_stat_mask & (ALT_CLKMGR_INTER_MAINPLLACHIEVED_CLR_MSK - & ALT_CLKMGR_INTER_PERPLLACHIEVED_CLR_MSK - & ALT_CLKMGR_INTER_SDRPLLACHIEVED_CLR_MSK - & ALT_CLKMGR_INTER_MAINPLLLOST_CLR_MSK - & ALT_CLKMGR_INTER_PERPLLLOST_CLR_MSK - & ALT_CLKMGR_INTER_SDRPLLLOST_CLR_MSK)) + if (lock_stat_mask & ( ALT_CLKMGR_INTER_MAINPLLACHIEVED_CLR_MSK + & ALT_CLKMGR_INTER_PERPLLACHIEVED_CLR_MSK + & ALT_CLKMGR_INTER_SDRPLLACHIEVED_CLR_MSK + & ALT_CLKMGR_INTER_MAINPLLLOST_CLR_MSK + & ALT_CLKMGR_INTER_PERPLLLOST_CLR_MSK + & ALT_CLKMGR_INTER_SDRPLLLOST_CLR_MSK) + ) { - ret = ALT_E_BAD_ARG; + return ALT_E_BAD_ARG; } else { alt_setbits_word(ALT_CLKMGR_INTER_ADDR, lock_stat_mask); - ret = ALT_E_SUCCESS; + return ALT_E_SUCCESS; } - return ret; } @@ -349,15 +409,15 @@ static void alt_clk_pllcounter_write(void* vcoaddr, void* stataddr, void* cntrad uint32_t alt_clk_lock_status_get(void) { - return alt_read_word(ALT_CLKMGR_INTER_ADDR) & (ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET_MSK - | ALT_CLKMGR_INTER_PERPLLACHIEVED_SET_MSK - | ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET_MSK - | ALT_CLKMGR_INTER_MAINPLLLOST_SET_MSK - | ALT_CLKMGR_INTER_PERPLLLOST_SET_MSK - | ALT_CLKMGR_INTER_SDRPLLLOST_SET_MSK - | ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK - | ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK - | ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK ); + return alt_read_word(ALT_CLKMGR_INTER_ADDR) & ( ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET_MSK + | ALT_CLKMGR_INTER_PERPLLACHIEVED_SET_MSK + | ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET_MSK + | ALT_CLKMGR_INTER_MAINPLLLOST_SET_MSK + | ALT_CLKMGR_INTER_PERPLLLOST_SET_MSK + | ALT_CLKMGR_INTER_SDRPLLLOST_SET_MSK + | ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK + | ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK + | ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK ); } @@ -368,24 +428,24 @@ uint32_t alt_clk_lock_status_get(void) ALT_STATUS_CODE alt_clk_pll_is_locked(ALT_CLK_t pll) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + ALT_STATUS_CODE status = ALT_E_BAD_ARG; if (pll == ALT_CLK_MAIN_PLL) { - ret = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK) + status = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK) ? ALT_E_TRUE : ALT_E_FALSE; } else if (pll == ALT_CLK_PERIPHERAL_PLL) { - ret = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK) + status = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK) ? ALT_E_TRUE : ALT_E_FALSE; } else if (pll == ALT_CLK_SDRAM_PLL) { - ret = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK) + status = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK) ? ALT_E_TRUE : ALT_E_FALSE; } - return ret; + return status; } @@ -396,7 +456,7 @@ ALT_STATUS_CODE alt_clk_pll_is_locked(ALT_CLK_t pll) ALT_STATUS_CODE alt_clk_safe_mode_clear(void) { - ALT_STATUS_CODE ret = ALT_E_ERROR; + ALT_STATUS_CODE status = ALT_E_ERROR; #if ALT_PREVENT_GLITCH_EXSAFE uint32_t temp; @@ -407,7 +467,7 @@ ALT_STATUS_CODE alt_clk_safe_mode_clear(void) alt_setbits_word(ALT_CLKMGR_CTL_ADDR, ALT_CLKMGR_CTL_SAFEMOD_SET_MSK); // clear safe mode bit - ret = alt_clk_plls_settle_wait(); + status = alt_clk_plls_settle_wait(); alt_replbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK | ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK, temp); @@ -416,10 +476,10 @@ ALT_STATUS_CODE alt_clk_safe_mode_clear(void) #else alt_setbits_word(ALT_CLKMGR_CTL_ADDR, ALT_CLKMGR_CTL_SAFEMOD_SET_MSK); // clear safe mode bit - ret = alt_clk_plls_settle_wait(); + status = alt_clk_plls_settle_wait(); #endif - return ret; + return status; } @@ -463,12 +523,12 @@ bool alt_clk_is_in_safe_mode(ALT_CLK_SAFE_DOMAIN_t clk_domain) ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - uint32_t temp; + ALT_STATUS_CODE status = ALT_E_BAD_ARG; + uint32_t temp; #if ALT_PREVENT_GLITCH_BYP - uint32_t temp1; - bool restore_0 = false; - bool restore_1 = false; + uint32_t temp1; + bool restore_0 = false; + bool restore_1 = false; #endif // this function should only be called after the selected PLL is locked @@ -479,20 +539,20 @@ ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll) #if ALT_PREVENT_GLITCH_BYP // if L4MP or L4SP source is set to Main PLL C1, gate it off before changing // bypass state, then gate clock back on. FogBugz #63778 - temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); + temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK))) { - restore_0 = true; + restore_0 = true; } if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK))) { - restore_1 = true; + restore_1 = true; } temp = temp1; - if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } - if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } + if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); } #endif @@ -507,7 +567,7 @@ ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll) // remove bypass alt_clrbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK); - ret = alt_clk_plls_settle_wait(); + status = alt_clk_plls_settle_wait(); #if ALT_PREVENT_GLITCH_BYP if (restore_0 || restore_1) @@ -551,7 +611,7 @@ ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll) // remove bypass - don't think that there's any need to touch the bypass clock source alt_clrbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_PERPLL_SET_MSK); - ret = alt_clk_plls_settle_wait(); + status = alt_clk_plls_settle_wait(); #if ALT_PREVENT_GLITCH_BYP if (restore_0 || restore_1) @@ -575,12 +635,15 @@ ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll) // remove bypass - don't think that there's any need to touch the bypass clock source alt_clrbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_SDRPLLSRC_SET_MSK); - ret = alt_clk_plls_settle_wait(); + status = alt_clk_plls_settle_wait(); } } - else { ret = ALT_E_ERROR; } + else + { + status = ALT_E_ERROR; + } - return ret; + return status; } @@ -590,12 +653,12 @@ ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll) ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, bool use_input_mux) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - uint32_t temp; + ALT_STATUS_CODE status = ALT_E_BAD_ARG; + uint32_t temp; #ifdef ALT_PREVENT_GLITCH_BYP - uint32_t temp1; - bool restore_0 = false; - bool restore_1 = false; + uint32_t temp1; + bool restore_0 = false; + bool restore_1 = false; #endif if (pll == ALT_CLK_MAIN_PLL) @@ -605,59 +668,61 @@ ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, bool use_input_mux) #ifdef ALT_PREVENT_GLITCH_BYP // if L4MP or L4SP source is set to Main PLL C1, gate it off before changing // bypass state, then gate clock back on. FogBugz #63778 - temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); + temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK))) { - restore_0 = true; + restore_0 = true; } if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK))) { - restore_1 = true; + restore_1 = true; } temp = temp1; - if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } - if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } + if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); } alt_setbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK); // no input mux select on main PLL - ret = alt_clk_plls_settle_wait(); + status = alt_clk_plls_settle_wait(); // wait before reenabling the L4MP and L4SP clocks if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp1); } #else alt_setbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK); // no input mux select on main PLL - ret = alt_clk_plls_settle_wait(); + status = alt_clk_plls_settle_wait(); #endif - ret = ALT_E_SUCCESS; + status = ALT_E_SUCCESS; + } + else + { + status = ALT_E_BAD_ARG; } - else { ret = ALT_E_BAD_ARG; } } - else if (pll == ALT_CLK_PERIPHERAL_PLL) { #ifdef ALT_PREVENT_GLITCH_BYP // if L4MP or L4SP source is set to Peripheral PLL C1, gate it off before changing // bypass state, then gate clock back on. FogBugz #63778 - temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); + temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK)) { - restore_0 = true; + restore_0 = true; } if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK)) { - restore_1 = true; + restore_1 = true; } temp = temp1; - if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } - if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } + if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); } temp = alt_read_word(ALT_CLKMGR_BYPASS_ADDR) & @@ -678,7 +743,7 @@ ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, bool use_input_mux) ALT_CLKMGR_BYPASS_PERPLLSRC_SET_MSK : ALT_CLKMGR_BYPASS_PERPLL_SET_MSK; // set bypass bit and optionally the source select bit #endif - ret = ALT_E_SUCCESS; + status = ALT_E_SUCCESS; } else if (pll == ALT_CLK_SDRAM_PLL) @@ -689,9 +754,9 @@ ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, bool use_input_mux) ALT_CLKMGR_BYPASS_SDRPLLSRC_SET_MSK : ALT_CLKMGR_BYPASS_SDRPLL_SET_MSK; // set bypass bit and optionally the source select bit alt_write_word(ALT_CLKMGR_BYPASS_ADDR, temp); - ret = ALT_E_SUCCESS; + status = ALT_E_SUCCESS; } - return ret; + return status; } @@ -706,27 +771,27 @@ ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, bool use_input_mux) ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + ALT_STATUS_CODE status = ALT_E_BAD_ARG; if (pll == ALT_CLK_MAIN_PLL) { - ret = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR)) + status = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR)) || ALT_CLKMGR_BYPASS_MAINPLL_GET(alt_read_word(ALT_CLKMGR_BYPASS_ADDR))) ? ALT_E_TRUE : ALT_E_FALSE; } else if (pll == ALT_CLK_PERIPHERAL_PLL) { - ret = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR)) + status = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR)) || ALT_CLKMGR_BYPASS_PERPLL_GET(alt_read_word(ALT_CLKMGR_BYPASS_ADDR))) ? ALT_E_TRUE : ALT_E_FALSE; } else if (pll == ALT_CLK_SDRAM_PLL) { - ret = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR)) + status = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR)) || ALT_CLKMGR_BYPASS_SDRPLL_GET(alt_read_word(ALT_CLKMGR_BYPASS_ADDR))) ? ALT_E_TRUE : ALT_E_FALSE; } - return ret; + return status; } @@ -734,9 +799,9 @@ ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll) /* alt_clk_pll_source_get() returns the current input of the specified PLL. */ /****************************************************************************************/ -static ALT_CLK_t alt_clk_pll_source_get(ALT_CLK_t pll) +ALT_CLK_t alt_clk_pll_source_get(ALT_CLK_t pll) { - ALT_CLK_t ret = ALT_CLK_UNKNOWN; + ALT_CLK_t ret = ALT_CLK_UNKNOWN; uint32_t temp; @@ -777,962 +842,920 @@ static ALT_CLK_t alt_clk_pll_source_get(ALT_CLK_t pll) { ret = ALT_CLK_F2H_SDRAM_REF; } - } + } return ret; } - -/****************************************************************************************/ -/* alt_clk_clock_disable() disables the specified clock. Once the clock is disabled, */ -/* its clock signal does not propagate to its clocked elements. */ -/****************************************************************************************/ - +// +// alt_clk_clock_disable() disables the specified clock. Once the clock is disabled, +// its clock signal does not propagate to its clocked elements. +// ALT_STATUS_CODE alt_clk_clock_disable(ALT_CLK_t clk) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + ALT_STATUS_CODE status = ALT_E_SUCCESS; switch (clk) { - /* For PLLs, put them in bypass mode */ - case (ALT_CLK_MAIN_PLL): - case (ALT_CLK_PERIPHERAL_PLL): - case (ALT_CLK_SDRAM_PLL): - ret = alt_clk_pll_bypass_enable(clk, false); - break; - - /* Clocks that originate at the Main PLL */ - case (ALT_CLK_L4_MAIN): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_L3_MP): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_L4_MP): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_L4_SP): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG_AT): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG_TRACE): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG_TIMER): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_CFG): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_H2F_USER0): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - - /* Clocks that originate at the Peripheral PLL */ - case (ALT_CLK_EMAC0): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_EMAC1): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_USB_MP): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_SPI_M): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_CAN0): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_CAN1): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_GPIO_DB): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_H2F_USER1): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_SDMMC): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_NAND_X): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); - // gate nand_clk off before nand_x_clk - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_NAND): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); - ret = ALT_E_SUCCESS; + // For PLLs, put them in bypass mode. + case ALT_CLK_MAIN_PLL: + case ALT_CLK_PERIPHERAL_PLL: + case ALT_CLK_SDRAM_PLL: + status = alt_clk_pll_bypass_enable(clk, false); break; - case (ALT_CLK_QSPI): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - - /* Clocks that originate at the SDRAM PLL */ - case (ALT_CLK_DDR_DQS): - alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DDR_2X_DQS): - alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - - case (ALT_CLK_DDR_DQ): - alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; + // Clocks that originate at the Main PLL. + case ALT_CLK_L4_MAIN: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK); + break; + case ALT_CLK_L3_MP: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK); + break; + case ALT_CLK_L4_MP: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK); + break; + case ALT_CLK_L4_SP: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK); + break; + case ALT_CLK_DBG_AT: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK); + break; + case ALT_CLK_DBG: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK); + break; + case ALT_CLK_DBG_TRACE: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK); + break; + case ALT_CLK_DBG_TIMER: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK); + break; + case ALT_CLK_CFG: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER0: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK); + break; - case (ALT_CLK_H2F_USER2): - alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; + // Clocks that originate at the Peripheral PLL. + case ALT_CLK_EMAC0: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK); + break; + case ALT_CLK_EMAC1: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK); + break; + case ALT_CLK_USB_MP: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK); + break; + case ALT_CLK_SPI_M: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK); + break; + case ALT_CLK_CAN0: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK); + break; + case ALT_CLK_CAN1: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK); + break; + case ALT_CLK_GPIO_DB: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER1: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK); + break; + case ALT_CLK_SDMMC: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK); + break; + case ALT_CLK_NAND_X: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); + // gate nand_clk off before nand_x_clk. + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); + break; + case ALT_CLK_NAND: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); + break; + case ALT_CLK_QSPI: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + break; - default: - break; + // Clocks that originate at the SDRAM PLL. + case ALT_CLK_DDR_DQS: + alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK); + break; + case ALT_CLK_DDR_2X_DQS: + alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK); + break; + case ALT_CLK_DDR_DQ: + alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER2: + alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK); + break; + default: + status = ALT_E_BAD_ARG; + break; } - return ret; -} - -/****************************************************************************************/ -/* alt_clk_clock_enable() enables the specified clock. Once the clock is enabled, its */ -/* clock signal propagates to its elements. */ -/****************************************************************************************/ + return status; +} +// +// alt_clk_clock_enable() enables the specified clock. Once the clock is enabled, its +// clock signal propagates to its elements. +// ALT_STATUS_CODE alt_clk_clock_enable(ALT_CLK_t clk) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + ALT_STATUS_CODE status = ALT_E_SUCCESS; switch (clk) { - /* For PLLs, take them out of bypass mode */ - case (ALT_CLK_MAIN_PLL): - case (ALT_CLK_PERIPHERAL_PLL): - case (ALT_CLK_SDRAM_PLL): - ret = alt_clk_pll_bypass_disable(clk); - break; - - - /* Clocks that originate at the Main PLL */ - case (ALT_CLK_L4_MAIN): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_L3_MP): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_L4_MP): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_L4_SP): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG_AT): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG_TRACE): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG_TIMER): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_CFG): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_H2F_USER0): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - - /* Clocks that originate at the Peripheral PLL */ - case (ALT_CLK_EMAC0): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_EMAC1): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_USB_MP): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_SPI_M): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_CAN0): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_CAN1): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_GPIO_DB): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_H2F_USER1): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_SDMMC): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_NAND_X): - // implementation detail - should ALK_CLK_NAND be gated off here before enabling ALT_CLK_NAND_X? - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); - // implementation detail - should this wait be enforced here? - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_NAND): - // enabling ALT_CLK_NAND always implies enabling ALT_CLK_NAND_X first - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); - // gate nand_x_clk on at least 8 MCU clocks before nand_clk - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_QSPI): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; + // For PLLs, take them out of bypass mode. + case ALT_CLK_MAIN_PLL: + case ALT_CLK_PERIPHERAL_PLL: + case ALT_CLK_SDRAM_PLL: + status = alt_clk_pll_bypass_disable(clk); + break; - /* Clocks that originate at the SDRAM PLL */ - case (ALT_CLK_DDR_DQS): - alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; + // Clocks that originate at the Main PLL. + case ALT_CLK_L4_MAIN: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK); + break; + case ALT_CLK_L3_MP: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK); + break; + case ALT_CLK_L4_MP: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK); + break; + case ALT_CLK_L4_SP: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK); + break; + case ALT_CLK_DBG_AT: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK); + break; + case ALT_CLK_DBG: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK); + break; + case ALT_CLK_DBG_TRACE: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK); + break; + case ALT_CLK_DBG_TIMER: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK); + break; + case ALT_CLK_CFG: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER0: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK); + break; - case (ALT_CLK_DDR_2X_DQS): - alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; + // Clocks that originate at the Peripheral PLL. + case ALT_CLK_EMAC0: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK); + break; + case ALT_CLK_EMAC1: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK); + break; + case ALT_CLK_USB_MP: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK); + break; + case ALT_CLK_SPI_M: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK); + break; + case ALT_CLK_CAN0: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK); + break; + case ALT_CLK_CAN1: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK); + break; + case ALT_CLK_GPIO_DB: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER1: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK); + break; + case ALT_CLK_SDMMC: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK); + break; + case ALT_CLK_NAND_X: + // implementation detail - should ALK_CLK_NAND be gated off here before enabling ALT_CLK_NAND_X? + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); + // implementation detail - should this wait be enforced here? + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); + break; + case ALT_CLK_NAND: + // enabling ALT_CLK_NAND always implies enabling ALT_CLK_NAND_X first + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); + // gate nand_x_clk on at least 8 MCU clocks before nand_clk + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); + break; + case ALT_CLK_QSPI: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + break; - case (ALT_CLK_DDR_DQ): - alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; + // Clocks that originate at the SDRAM PLL. + case ALT_CLK_DDR_DQS: + alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK); + break; + case ALT_CLK_DDR_2X_DQS: + alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK); + break; + case ALT_CLK_DDR_DQ: + alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER2: + alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK); + break; - case (ALT_CLK_H2F_USER2): - alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; + default: + status = ALT_E_BAD_ARG; + break; + } - default: break; - } - return ret; + return status; } - -/****************************************************************************************/ -/* alt_clk_is_enabled() returns whether the specified clock is enabled or not. */ -/****************************************************************************************/ - +// +// alt_clk_is_enabled() returns whether the specified clock is enabled or not. +// ALT_STATUS_CODE alt_clk_is_enabled(ALT_CLK_t clk) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - - switch (clk) // this should be more than enough cases to cause - { // the compiler to use a jump table implementation + ALT_STATUS_CODE status = ALT_E_BAD_ARG; - /* For PLLs, this function checks if the PLL is bypassed or not */ - case (ALT_CLK_MAIN_PLL): - case (ALT_CLK_PERIPHERAL_PLL): - case (ALT_CLK_SDRAM_PLL): - ret = (alt_clk_pll_is_bypassed(clk) != ALT_E_TRUE); - break; + switch (clk) + { + // For PLLs, this function checks if the PLL is bypassed or not. + case ALT_CLK_MAIN_PLL: + case ALT_CLK_PERIPHERAL_PLL: + case ALT_CLK_SDRAM_PLL: + status = (alt_clk_pll_is_bypassed(clk) != ALT_E_TRUE); + break; - /* These clocks are not gated, so must return a ALT_E_BAD_ARG type error */ - case (ALT_CLK_MAIN_PLL_C0): - case (ALT_CLK_MAIN_PLL_C1): - case (ALT_CLK_MAIN_PLL_C2): - case (ALT_CLK_MAIN_PLL_C3): - case (ALT_CLK_MAIN_PLL_C4): - case (ALT_CLK_MAIN_PLL_C5): - case (ALT_CLK_MPU): - case (ALT_CLK_MPU_L2_RAM): - case (ALT_CLK_MPU_PERIPH): - case (ALT_CLK_L3_MAIN): - case (ALT_CLK_L3_SP): - case (ALT_CLK_DBG_BASE): - case (ALT_CLK_MAIN_QSPI): - case (ALT_CLK_MAIN_NAND_SDMMC): - case (ALT_CLK_PERIPHERAL_PLL_C0): - case (ALT_CLK_PERIPHERAL_PLL_C1): - case (ALT_CLK_PERIPHERAL_PLL_C2): - case (ALT_CLK_PERIPHERAL_PLL_C3): - case (ALT_CLK_PERIPHERAL_PLL_C4): - case (ALT_CLK_PERIPHERAL_PLL_C5): - case (ALT_CLK_SDRAM_PLL_C0): - case (ALT_CLK_SDRAM_PLL_C1): - case (ALT_CLK_SDRAM_PLL_C2): - case (ALT_CLK_SDRAM_PLL_C5): - ret = ALT_E_BAD_ARG; - break; + // These clocks are not gated, so must return a ALT_E_BAD_ARG type error. + case ALT_CLK_MAIN_PLL_C0: + case ALT_CLK_MAIN_PLL_C1: + case ALT_CLK_MAIN_PLL_C2: + case ALT_CLK_MAIN_PLL_C3: + case ALT_CLK_MAIN_PLL_C4: + case ALT_CLK_MAIN_PLL_C5: + case ALT_CLK_MPU: + case ALT_CLK_MPU_L2_RAM: + case ALT_CLK_MPU_PERIPH: + case ALT_CLK_L3_MAIN: + case ALT_CLK_L3_SP: + case ALT_CLK_DBG_BASE: + case ALT_CLK_MAIN_QSPI: + case ALT_CLK_MAIN_NAND_SDMMC: + case ALT_CLK_PERIPHERAL_PLL_C0: + case ALT_CLK_PERIPHERAL_PLL_C1: + case ALT_CLK_PERIPHERAL_PLL_C2: + case ALT_CLK_PERIPHERAL_PLL_C3: + case ALT_CLK_PERIPHERAL_PLL_C4: + case ALT_CLK_PERIPHERAL_PLL_C5: + case ALT_CLK_SDRAM_PLL_C0: + case ALT_CLK_SDRAM_PLL_C1: + case ALT_CLK_SDRAM_PLL_C2: + case ALT_CLK_SDRAM_PLL_C5: + status = ALT_E_BAD_ARG; + break; - /* Clocks that originate at the Main PLL */ - case (ALT_CLK_L4_MAIN): - ret = (ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_L3_MP): - ret = (ALT_CLKMGR_MAINPLL_EN_L3MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_L4_MP): - ret = (ALT_CLKMGR_MAINPLL_EN_L4MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_L4_SP): - ret = (ALT_CLKMGR_MAINPLL_EN_L4SPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_DBG_AT): - ret = (ALT_CLKMGR_MAINPLL_EN_DBGATCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_DBG): - ret = (ALT_CLKMGR_MAINPLL_EN_DBGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_DBG_TRACE): - ret = (ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_DBG_TIMER): - ret = (ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_CFG): - ret = (ALT_CLKMGR_MAINPLL_EN_CFGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_H2F_USER0): - ret = (ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; + // Clocks that originate at the Main PLL. + case ALT_CLK_L4_MAIN: + status = (ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_L3_MP: + status = (ALT_CLKMGR_MAINPLL_EN_L3MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_L4_MP: + status = (ALT_CLKMGR_MAINPLL_EN_L4MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_L4_SP: + status = (ALT_CLKMGR_MAINPLL_EN_L4SPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DBG_AT: + status = (ALT_CLKMGR_MAINPLL_EN_DBGATCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DBG: + status = (ALT_CLKMGR_MAINPLL_EN_DBGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DBG_TRACE: + status = (ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DBG_TIMER: + status = (ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_CFG: + status = (ALT_CLKMGR_MAINPLL_EN_CFGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_H2F_USER0: + status = (ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; - /* Clocks that originate at the Peripheral PLL */ - case (ALT_CLK_EMAC0): - ret = (ALT_CLKMGR_PERPLL_EN_EMAC0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_EMAC1): - ret = (ALT_CLKMGR_PERPLL_EN_EMAC1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_USB_MP): - ret = (ALT_CLKMGR_PERPLL_EN_USBCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_SPI_M): - ret = (ALT_CLKMGR_PERPLL_EN_SPIMCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_CAN0): - ret = (ALT_CLKMGR_PERPLL_EN_CAN0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_CAN1): - ret = (ALT_CLKMGR_PERPLL_EN_CAN1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_GPIO_DB): - ret = (ALT_CLKMGR_PERPLL_EN_GPIOCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_H2F_USER1): - ret = (ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; + // Clocks that originate at the Peripheral PLL. + case ALT_CLK_EMAC0: + status = (ALT_CLKMGR_PERPLL_EN_EMAC0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_EMAC1: + status = (ALT_CLKMGR_PERPLL_EN_EMAC1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_USB_MP: + status = (ALT_CLKMGR_PERPLL_EN_USBCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_SPI_M: + status = (ALT_CLKMGR_PERPLL_EN_SPIMCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_CAN0: + status = (ALT_CLKMGR_PERPLL_EN_CAN0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_CAN1: + status = (ALT_CLKMGR_PERPLL_EN_CAN1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_GPIO_DB: + status = (ALT_CLKMGR_PERPLL_EN_GPIOCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_H2F_USER1: + status = (ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; - /* Clocks that may originate at the Main PLL, the Peripheral PLL, or the FPGA */ - case (ALT_CLK_SDMMC): - ret = (ALT_CLKMGR_PERPLL_EN_SDMMCCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_NAND_X): - ret = (ALT_CLKMGR_PERPLL_EN_NANDXCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_NAND): - ret = (ALT_CLKMGR_PERPLL_EN_NANDCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_QSPI): - ret = (ALT_CLKMGR_PERPLL_EN_QSPICLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; + // Clocks that may originate at the Main PLL, the Peripheral PLL, or the FPGA. + case ALT_CLK_SDMMC: + status = (ALT_CLKMGR_PERPLL_EN_SDMMCCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_NAND_X: + status = (ALT_CLKMGR_PERPLL_EN_NANDXCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_NAND: + status = (ALT_CLKMGR_PERPLL_EN_NANDCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_QSPI: + status = (ALT_CLKMGR_PERPLL_EN_QSPICLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; - /* Clocks that originate at the SDRAM PLL */ - case (ALT_CLK_DDR_DQS): - ret = (ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_DDR_2X_DQS): - ret = (ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_DDR_DQ): - ret = (ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_H2F_USER2): - ret = (ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; + // Clocks that originate at the SDRAM PLL. + case ALT_CLK_DDR_DQS: + status = (ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DDR_2X_DQS: + status = (ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DDR_DQ: + status = (ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_H2F_USER2: + status = (ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; - default: - break; + default: + status = ALT_E_BAD_ARG; + break; } - return ret; -} - -/****************************************************************************************/ -/* alt_clk_source_get() gets the input reference clock source selection value for the */ -/* specified clock or PLL. */ -/****************************************************************************************/ + return status; +} +// +// alt_clk_source_get() gets the input reference clock source selection value for the +// specified clock or PLL. +// ALT_CLK_t alt_clk_source_get(ALT_CLK_t clk) { - ALT_CLK_t ret = ALT_CLK_UNKNOWN; - uint32_t temp; + ALT_CLK_t ret = ALT_CLK_UNKNOWN; + uint32_t temp; switch (clk) { - /* Potential external clock sources */ - case ALT_CLK_IN_PIN_OSC1: - case ALT_CLK_IN_PIN_OSC2: - case ALT_CLK_F2H_PERIPH_REF: - case ALT_CLK_F2H_SDRAM_REF: - case ALT_CLK_IN_PIN_JTAG: - case ALT_CLK_IN_PIN_ULPI0: - case ALT_CLK_IN_PIN_ULPI1: - case ALT_CLK_IN_PIN_EMAC0_RX: - case ALT_CLK_IN_PIN_EMAC1_RX: - ret = clk; - break; // these clock entities are their own source - - /* Phase-Locked Loops */ - case ALT_CLK_MAIN_PLL: - case ALT_CLK_OSC1: - ret = ALT_CLK_IN_PIN_OSC1; - break; - case ALT_CLK_PERIPHERAL_PLL: - ret = alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL); - break; - case ALT_CLK_SDRAM_PLL: - ret = alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL); - break; + // Potential external clock sources. + // these clock entities are their own source + case ALT_CLK_IN_PIN_OSC1: + case ALT_CLK_IN_PIN_OSC2: + case ALT_CLK_F2H_PERIPH_REF: + case ALT_CLK_F2H_SDRAM_REF: + case ALT_CLK_IN_PIN_JTAG: + case ALT_CLK_IN_PIN_ULPI0: + case ALT_CLK_IN_PIN_ULPI1: + case ALT_CLK_IN_PIN_EMAC0_RX: + case ALT_CLK_IN_PIN_EMAC1_RX: + ret = clk; + break; - /* Main Clock Group */ - case ALT_CLK_MAIN_PLL_C0: - case ALT_CLK_MAIN_PLL_C1: - case ALT_CLK_MAIN_PLL_C2: - case ALT_CLK_MAIN_PLL_C3: - case ALT_CLK_MAIN_PLL_C4: - case ALT_CLK_MAIN_PLL_C5: - // check bypass, return either osc1 or PLL ID - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL; - break; + // Phase-Locked Loops. + case ALT_CLK_MAIN_PLL: + case ALT_CLK_OSC1: + ret = ALT_CLK_IN_PIN_OSC1; + break; + case ALT_CLK_PERIPHERAL_PLL: + ret = alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL); + break; + case ALT_CLK_SDRAM_PLL: + ret = alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL); + break; + + // Main Clock Group. + case ALT_CLK_MAIN_PLL_C0: + case ALT_CLK_MAIN_PLL_C1: + case ALT_CLK_MAIN_PLL_C2: + case ALT_CLK_MAIN_PLL_C3: + case ALT_CLK_MAIN_PLL_C4: + case ALT_CLK_MAIN_PLL_C5: + // check bypass, return either osc1 or PLL ID + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL; + break; + + case ALT_CLK_MPU_PERIPH: + case ALT_CLK_MPU_L2_RAM: + case ALT_CLK_MPU: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C0; + break; + + case ALT_CLK_L4_MAIN: + case ALT_CLK_L3_MAIN: + case ALT_CLK_L3_MP: + case ALT_CLK_L3_SP: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1; + break; - case ALT_CLK_MPU_PERIPH: - case ALT_CLK_MPU_L2_RAM: - case ALT_CLK_MPU: + case ALT_CLK_L4_MP: + // read the state of the L4_mp source bit + if ((ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR))) + == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL) + { ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C0; - break; + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1; + } + else + { + // if the clock comes from periph_base_clk + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4; + } + break; - case ALT_CLK_L4_MAIN: - case ALT_CLK_L3_MAIN: - case ALT_CLK_L3_MP: - case ALT_CLK_L3_SP: + case ALT_CLK_L4_SP: + // read the state of the source bit + if ((ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR))) + == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL) + { ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1; - break; + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1; + } + else + { + // if the clock comes from periph_base_clk + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4; + } + break; - case ALT_CLK_L4_MP: - // read the state of the L4_mp source bit - if ((ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR))) - == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1; - } - else - { - // if the clock comes from periph_base_clk - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4; - } - break; + case ALT_CLK_DBG_BASE: + case ALT_CLK_DBG_AT: + case ALT_CLK_DBG_TRACE: + case ALT_CLK_DBG_TIMER: + case ALT_CLK_DBG: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C2; + break; + case ALT_CLK_MAIN_QSPI: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C3; + break; + case ALT_CLK_MAIN_NAND_SDMMC: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C4; + break; + case ALT_CLK_CFG: + case ALT_CLK_H2F_USER0: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C5; + break; - case ALT_CLK_L4_SP: - // read the state of the source bit - if ((ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR))) - == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1; - } - else - { - // if the clock comes from periph_base_clk - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4; - } - break; + // Peripherals Clock Group + case ALT_CLK_PERIPHERAL_PLL_C0: + case ALT_CLK_PERIPHERAL_PLL_C1: + case ALT_CLK_PERIPHERAL_PLL_C2: + case ALT_CLK_PERIPHERAL_PLL_C3: + case ALT_CLK_PERIPHERAL_PLL_C4: + case ALT_CLK_PERIPHERAL_PLL_C5: + // if the clock comes from periph_base_clk + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL; + break; - case ALT_CLK_DBG_BASE: - case ALT_CLK_DBG_AT: - case ALT_CLK_DBG_TRACE: - case ALT_CLK_DBG_TIMER: - case ALT_CLK_DBG: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C2; - break; - case ALT_CLK_MAIN_QSPI: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C3; - break; - case ALT_CLK_MAIN_NAND_SDMMC: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C4; - break; - case ALT_CLK_CFG: - case ALT_CLK_H2F_USER0: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C5; - break; + case ALT_CLK_EMAC0: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C0; + break; - /* Peripherals Clock Group */ - case ALT_CLK_PERIPHERAL_PLL_C0: - case ALT_CLK_PERIPHERAL_PLL_C1: - case ALT_CLK_PERIPHERAL_PLL_C2: - case ALT_CLK_PERIPHERAL_PLL_C3: - case ALT_CLK_PERIPHERAL_PLL_C4: - case ALT_CLK_PERIPHERAL_PLL_C5: - // if the clock comes from periph_base_clk - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL; - break; + case ALT_CLK_EMAC1: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C1; + break; - case ALT_CLK_EMAC0: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C0; - break; + case ALT_CLK_USB_MP: + case ALT_CLK_SPI_M: + case ALT_CLK_CAN0: + case ALT_CLK_CAN1: + case ALT_CLK_GPIO_DB: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4; + break; - case ALT_CLK_EMAC1: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C1; - break; + case ALT_CLK_H2F_USER1: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C5; + break; - case ALT_CLK_USB_MP: - case ALT_CLK_SPI_M: - case ALT_CLK_CAN0: - case ALT_CLK_CAN1: - case ALT_CLK_GPIO_DB: + case ALT_CLK_SDMMC: + temp = ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK) + { + ret = ALT_CLK_F2H_PERIPH_REF; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK) + { + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C4; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK) + { ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4; - break; + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C3; + } + break; - case ALT_CLK_H2F_USER1: + case ALT_CLK_NAND_X: + case ALT_CLK_NAND: + temp = ALT_CLKMGR_PERPLL_SRC_NAND_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK) + { + ret = ALT_CLK_F2H_PERIPH_REF; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK) + { + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C4; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK) + { ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C5; - break; - - case ALT_CLK_SDMMC: - temp = ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK) - { - ret = ALT_CLK_F2H_PERIPH_REF; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C4; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C3; - } - break; + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C3; + } + break; - case ALT_CLK_NAND_X: - case ALT_CLK_NAND: - temp = ALT_CLKMGR_PERPLL_SRC_NAND_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK) - { - ret = ALT_CLK_F2H_PERIPH_REF; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C4; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C3; - } - break; + case ALT_CLK_QSPI: + temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK) + { + ret = ALT_CLK_F2H_PERIPH_REF; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) + { + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C3; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) + { + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C2; + } + break; - case ALT_CLK_QSPI: - temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK) - { - ret = ALT_CLK_F2H_PERIPH_REF; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C3; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C2; - } - break; + // SDRAM Clock Group + case ALT_CLK_SDRAM_PLL_C0: + case ALT_CLK_SDRAM_PLL_C1: + case ALT_CLK_SDRAM_PLL_C2: + case ALT_CLK_SDRAM_PLL_C3: + case ALT_CLK_SDRAM_PLL_C4: + case ALT_CLK_SDRAM_PLL_C5: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL; + break; + case ALT_CLK_DDR_DQS: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C0; + break; + case ALT_CLK_DDR_2X_DQS: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C1; + break; + case ALT_CLK_DDR_DQ: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C2; + break; + case ALT_CLK_H2F_USER2: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C5; + break; - /* SDRAM Clock Group */ - case ALT_CLK_SDRAM_PLL_C0: - case ALT_CLK_SDRAM_PLL_C1: - case ALT_CLK_SDRAM_PLL_C2: - case ALT_CLK_SDRAM_PLL_C3: - case ALT_CLK_SDRAM_PLL_C4: - case ALT_CLK_SDRAM_PLL_C5: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL; - break; - case ALT_CLK_DDR_DQS: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C0; - break; - case ALT_CLK_DDR_2X_DQS: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C1; - break; - case ALT_CLK_DDR_DQ: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C2; - break; - case ALT_CLK_H2F_USER2: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C5; - break; + // Clock Output Pins + case ALT_CLK_OUT_PIN_EMAC0_TX: + case ALT_CLK_OUT_PIN_EMAC1_TX: + case ALT_CLK_OUT_PIN_SDMMC: + case ALT_CLK_OUT_PIN_I2C0_SCL: + case ALT_CLK_OUT_PIN_I2C1_SCL: + case ALT_CLK_OUT_PIN_I2C2_SCL: + case ALT_CLK_OUT_PIN_I2C3_SCL: + case ALT_CLK_OUT_PIN_SPIM0: + case ALT_CLK_OUT_PIN_SPIM1: + case ALT_CLK_OUT_PIN_QSPI: + ret = ALT_CLK_UNKNOWN; + break; - /* Clock Output Pins */ - case ALT_CLK_OUT_PIN_EMAC0_TX: - case ALT_CLK_OUT_PIN_EMAC1_TX: - case ALT_CLK_OUT_PIN_SDMMC: - case ALT_CLK_OUT_PIN_I2C0_SCL: - case ALT_CLK_OUT_PIN_I2C1_SCL: - case ALT_CLK_OUT_PIN_I2C2_SCL: - case ALT_CLK_OUT_PIN_I2C3_SCL: - case ALT_CLK_OUT_PIN_SPIM0: - case ALT_CLK_OUT_PIN_SPIM1: - case ALT_CLK_OUT_PIN_QSPI: - ret = ALT_CLK_UNKNOWN; - break; + default: + ret = ALT_CLK_UNKNOWN; + break; + } - default: - break; - } /* end big switch/case construct */ return ret; } - -/****************************************************************************************/ -/* alt_clk_source_set() sets the specified clock's input reference clock source */ -/* selection to the specified input. It does not handle gating the specified clock */ -/* off and back on, those are covered in other functions in this API, but it does */ -/* verify that the clock is off before changing the divider or PLL. Note that the PLL */ -/* must have regained phase-lock before being the bypass is disabled. */ -/****************************************************************************************/ - -ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk, ALT_CLK_t ref_clk) +// +// alt_clk_source_set() sets the specified clock's input reference clock source +// selection to the specified input. It does not handle gating the specified clock +// off and back on, those are covered in other functions in this API, but it does +// verify that the clock is off before changing the divider or PLL. Note that the PLL +// must have regained phase-lock before being the bypass is disabled. +// +ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk, ALT_CLK_t ref_clk) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - uint32_t temp; + ALT_STATUS_CODE status = ALT_E_SUCCESS; + uint32_t temp; if (ALT_CLK_MAIN_PLL == clk) { - if ((ref_clk == ALT_CLK_IN_PIN_OSC1) || (ref_clk == ALT_CLK_OSC1)) { ret = ALT_E_SUCCESS; } + if ((ref_clk == ALT_CLK_IN_PIN_OSC1) || (ref_clk == ALT_CLK_OSC1)) + { + // ret = ALT_E_SUCCESS; + } + else + { + status = ALT_E_BAD_ARG; + } } else if (ALT_CLK_PERIPHERAL_PLL == clk) { - // the PLL must be bypassed before getting here - temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + // the PLL must be bypassed before getting here + temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); temp &= ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK; + if ((ref_clk == ALT_CLK_IN_PIN_OSC1) || (ref_clk == ALT_CLK_OSC1)) { temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1); alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_IN_PIN_OSC2) { temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2); alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_F2H_PERIPH_REF) { temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF); alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp); - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_INV_OPTION; } + else + { + status = ALT_E_INV_OPTION; + } } - else if ( ALT_CLK_SDRAM_PLL == clk) + else if (ALT_CLK_SDRAM_PLL == clk) { - temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); + temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); temp &= ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK; + if ((ref_clk == ALT_CLK_IN_PIN_OSC1) || (ref_clk == ALT_CLK_OSC1)) { temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1); alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_IN_PIN_OSC2) { temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2); alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_F2H_SDRAM_REF) { temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF); alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp); - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_INV_OPTION; } + else + { + status = ALT_E_INV_OPTION; + } } - else if ( ALT_CLK_L4_MP == clk) { - // clock is gated off + // clock is gated off if (ref_clk == ALT_CLK_MAIN_PLL_C1) { alt_clrbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C4) { alt_setbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK); - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_INV_OPTION; } + else + { + status = ALT_E_INV_OPTION; + } } - else if ( ALT_CLK_L4_SP == clk) { if (ref_clk == ALT_CLK_MAIN_PLL_C1) { alt_clrbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C4) { alt_setbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK); - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_INV_OPTION; } + else + { + status = ALT_E_INV_OPTION; + } } - - else if ( ALT_CLK_SDMMC == clk) + else if (ALT_CLK_SDMMC == clk) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); + temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); temp &= ALT_CLKMGR_PERPLL_SRC_SDMMC_CLR_MSK; + if (ref_clk == ALT_CLK_F2H_PERIPH_REF) { temp |= ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } else if ((ref_clk == ALT_CLK_MAIN_PLL_C4) || (ref_clk == ALT_CLK_MAIN_NAND_SDMMC)) { temp |= ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C3) { temp |= ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_INV_OPTION; } + else + { + status = ALT_E_INV_OPTION; + } } - - else if (( ALT_CLK_NAND_X == clk) || ( ALT_CLK_NAND == clk)) + else if ((ALT_CLK_NAND_X == clk) || ( ALT_CLK_NAND == clk)) { temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); temp &= ALT_CLKMGR_PERPLL_SRC_NAND_CLR_MSK; + if (ref_clk == ALT_CLK_F2H_PERIPH_REF) { temp |= ALT_CLKMGR_PERPLL_SRC_NAND_SET(ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } else if ((ref_clk == ALT_CLK_MAIN_PLL_C4) || (ref_clk == ALT_CLK_MAIN_NAND_SDMMC)) { temp |= ALT_CLKMGR_PERPLL_SRC_NAND_SET(ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C3) { temp |= ALT_CLKMGR_PERPLL_SRC_NAND_SET(ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_INV_OPTION; } + else + { + status = ALT_E_INV_OPTION; + } } - - else if ( ALT_CLK_QSPI == clk) + else if (ALT_CLK_QSPI == clk) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); + temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); temp &= ALT_CLKMGR_PERPLL_SRC_QSPI_CLR_MSK; + if (ref_clk == ALT_CLK_F2H_PERIPH_REF) { temp |= ALT_CLKMGR_PERPLL_SRC_QSPI_SET(ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } else if ((ref_clk == ALT_CLK_MAIN_PLL_C3) || (ref_clk == ALT_CLK_MAIN_QSPI)) { temp |= ALT_CLKMGR_PERPLL_SRC_QSPI_SET(ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C2) { temp |= ALT_CLKMGR_PERPLL_SRC_QSPI_SET(ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_INV_OPTION; } + else + { + status = ALT_E_INV_OPTION; + } } - return ret; -} - - -/****************************************************************************************/ -/* alt_clk_ext_clk_freq_set() specifies the frequency of the external clock source as */ -/* a measure of Hz. This value is stored in a static array and used for calculations. */ -/* The supplied frequency should be within the Fmin and Fmax values allowed for the */ -/* external clock source. */ -/****************************************************************************************/ + return status; +} +// +// alt_clk_ext_clk_freq_set() specifies the frequency of the external clock source as +// a measure of Hz. This value is stored in a static array and used for calculations. +// The supplied frequency should be within the Fmin and Fmax values allowed for the +// external clock source. +// ALT_STATUS_CODE alt_clk_ext_clk_freq_set(ALT_CLK_t clk, alt_freq_t freq) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + ALT_STATUS_CODE status = ALT_E_BAD_ARG; if ((clk == ALT_CLK_IN_PIN_OSC1) || (clk == ALT_CLK_OSC1)) // two names for one input { if ((freq >= alt_ext_clk_paramblok.clkosc1.freqmin) && (freq <= alt_ext_clk_paramblok.clkosc1.freqmax)) { alt_ext_clk_paramblok.clkosc1.freqcur = freq; - ret = ALT_E_SUCCESS; + status = ALT_E_SUCCESS; + } + else + { + status = ALT_E_ARG_RANGE; } - else { ret = ALT_E_ARG_RANGE; } } - else if (clk == ALT_CLK_IN_PIN_OSC2) // the other clock input pin { if ((freq >= alt_ext_clk_paramblok.clkosc2.freqmin) && (freq <= alt_ext_clk_paramblok.clkosc2.freqmax)) { alt_ext_clk_paramblok.clkosc2.freqcur = freq; - ret = ALT_E_SUCCESS; + status = ALT_E_SUCCESS; + } + else + { + status = ALT_E_ARG_RANGE; } - else { ret = ALT_E_ARG_RANGE; } } - else if (clk == ALT_CLK_F2H_PERIPH_REF) // clock from the FPGA { if ((freq >= alt_ext_clk_paramblok.periph.freqmin) && (freq <= alt_ext_clk_paramblok.periph.freqmax)) { alt_ext_clk_paramblok.periph.freqcur = freq; - ret = ALT_E_SUCCESS; + status = ALT_E_SUCCESS; + } + else + { + status = ALT_E_ARG_RANGE; } - else { ret = ALT_E_ARG_RANGE; } } - else if (clk == ALT_CLK_F2H_SDRAM_REF) // clock from the FPGA SDRAM { if ((freq >= alt_ext_clk_paramblok.sdram.freqmin) && (freq <= alt_ext_clk_paramblok.sdram.freqmax)) { alt_ext_clk_paramblok.sdram.freqcur = freq; - ret = ALT_E_SUCCESS; + status = ALT_E_SUCCESS; + } + else + { + status = ALT_E_ARG_RANGE; } - else { ret = ALT_E_ARG_RANGE; } } - return ret; -} - + else + { + status = ALT_E_BAD_ARG; + } -/****************************************************************************************/ -/* alt_clk_ext_clk_freq_get returns the frequency of the external clock source as */ -/* a measure of Hz. This value is stored in a static array. */ -/****************************************************************************************/ + return status; +} +// +// alt_clk_ext_clk_freq_get returns the frequency of the external clock source as +// a measure of Hz. This value is stored in a static array. +// alt_freq_t alt_clk_ext_clk_freq_get(ALT_CLK_t clk) { - uint32_t ret = 0; + uint32_t ret = 0; if ((clk == ALT_CLK_IN_PIN_OSC1) || (clk == ALT_CLK_OSC1)) // two names for one input { @@ -1754,323 +1777,341 @@ alt_freq_t alt_clk_ext_clk_freq_get(ALT_CLK_t clk) } -/****************************************************************************************/ -/* alt_clk_pll_cfg_get() returns the current PLL configuration. */ -/****************************************************************************************/ +// +// alt_clk_pll_cfg_get() returns the current PLL configuration. +// +ALT_STATUS_CODE alt_clk_pll_cfg_get(ALT_CLK_t pll, ALT_CLK_PLL_CFG_t * pll_cfg) +{ + ALT_STATUS_CODE ret = ALT_E_ERROR; // return value + uint32_t temp; // temp variable + + if (pll_cfg == NULL) + { + ret = ALT_E_BAD_ARG; + return ret; + } + if (pll == ALT_CLK_MAIN_PLL) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); + pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1; + pll_cfg->mult = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp); + pll_cfg->div = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp); -ALT_STATUS_CODE alt_clk_pll_cfg_get(ALT_CLK_t pll, ALT_CLK_PLL_CFG_t* pll_cfg) -{ - ALT_STATUS_CODE ret = ALT_E_ERROR; // return value - uint32_t temp; // temp variable - - if (pll_cfg != NULL) - { - if (pll == ALT_CLK_MAIN_PLL) - { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); - pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1; - pll_cfg->mult = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp); - pll_cfg->div = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp); - - // Get the C0-C5 divider values: - pll_cfg->cntrs[0] = ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR)); - // C0 - mpu_clk - - pll_cfg->cntrs[1] = ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR)); - // C1 - main_clk - - pll_cfg->cntrs[2] = ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR)); - // C2 - dbg_base_clk - - pll_cfg->cntrs[3] = ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR)); - // C3 - main_qspi_clk - - pll_cfg->cntrs[4] = ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR)); - // C4 - main_nand_sdmmc_clk - - pll_cfg->cntrs[5] = ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR)); - // C5 - cfg_s2f_user0_clk aka cfg_h2f_user0_clk - - // The Main PLL C0-C5 outputs have no phase shift capabilities : - pll_cfg->pshift[0] = pll_cfg->pshift[1] = pll_cfg->pshift[2] = - pll_cfg->pshift[3] = pll_cfg->pshift[4] = pll_cfg->pshift[5] = 0; - ret = ALT_E_SUCCESS; - } - else if (pll == ALT_CLK_PERIPHERAL_PLL) - { - temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR)); - if (temp <= 2) - { - if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) - { - pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1; - } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) - { - pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC2; - } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) - { - pll_cfg->ref_clk = ALT_CLK_F2H_PERIPH_REF; - } - - temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); - pll_cfg->mult = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp); - pll_cfg->div = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp); - - // Get the C0-C5 divider values: - pll_cfg->cntrs[0] = ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR)); - // C0 - emac0_clk - - pll_cfg->cntrs[1] = ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR)); - // C1 - emac1_clk - - pll_cfg->cntrs[2] = ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR)); - // C2 - periph_qspi_clk - - pll_cfg->cntrs[3] = ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR)); - // C3 - periph_nand_sdmmc_clk - - pll_cfg->cntrs[4] = ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR)); - // C4 - periph_base_clk - - pll_cfg->cntrs[5] = ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR)); - // C5 - s2f_user1_clk - - // The Peripheral PLL C0-C5 outputs have no phase shift capabilities : - pll_cfg->pshift[0] = pll_cfg->pshift[1] = pll_cfg->pshift[2] = - pll_cfg->pshift[3] = pll_cfg->pshift[4] = pll_cfg->pshift[5] = 0; - ret = ALT_E_SUCCESS; - } - } - else if (pll == ALT_CLK_SDRAM_PLL) - { - temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); - if (temp <= 2) - { - if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) - { - pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1; - } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) - { - pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC2; - } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) - { - pll_cfg->ref_clk = ALT_CLK_F2H_SDRAM_REF; - } - - pll_cfg->mult = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); - pll_cfg->div = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); - - // Get the C0-C5 divider values: - pll_cfg->cntrs[0] = ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR)); - pll_cfg->pshift[0] = ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR)); - // C0 - ddr_dqs_clk - - pll_cfg->cntrs[1] = ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR)); - pll_cfg->pshift[1] = ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR)); - // C1 - ddr_2x_dqs_clk - - pll_cfg->cntrs[2] = ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR)); - pll_cfg->pshift[2] = ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR)); - // C2 - ddr_dq_clk - - pll_cfg->cntrs[3] = pll_cfg->cntrs[4] = pll_cfg->pshift[3] = pll_cfg->pshift[4] = 0; - // C3 & C4 outputs don't exist on the SDRAM PLL - - pll_cfg->cntrs[5] = ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR)); - pll_cfg->pshift[5] = ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR)); - // C5 - s2f_user2_clk or h2f_user2_clk - - ret = ALT_E_SUCCESS; - } - } - } - return ret; -} + // Get the C0-C5 divider values: + pll_cfg->cntrs[0] = ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MPUCLK_ADDR)); + // C0 - mpu_clk + pll_cfg->cntrs[1] = ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MAINCLK_ADDR)); + // C1 - main_clk -/****************************************************************************************/ -/* alt_clk_pll_cfg_set() sets the PLL configuration using the configuration parameters */ -/* specified in pll_cfg. */ -/****************************************************************************************/ + pll_cfg->cntrs[2] = ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR)); + // C2 - dbg_base_clk -ALT_STATUS_CODE alt_clk_pll_cfg_set(ALT_CLK_t pll, const ALT_CLK_PLL_CFG_t* pll_cfg) -{ - ALT_STATUS_CODE ret = ALT_E_ERROR; - uint32_t temp; + pll_cfg->cntrs[3] = ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR)); + // C3 - main_qspi_clk + + pll_cfg->cntrs[4] = ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR)); + // C4 - main_nand_sdmmc_clk - if (pll_cfg != NULL) + pll_cfg->cntrs[5] = ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR)); + // C5 - cfg_s2f_user0_clk aka cfg_h2f_user0_clk + + // The Main PLL C0-C5 outputs have no phase shift capabilities : + pll_cfg->pshift[0] = pll_cfg->pshift[1] = pll_cfg->pshift[2] = + pll_cfg->pshift[3] = pll_cfg->pshift[4] = pll_cfg->pshift[5] = 0; + ret = ALT_E_SUCCESS; + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) { - if (alt_clk_pll_is_bypassed(pll) == ALT_E_TRUE) // safe to write the PLL registers? + temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR)); + if (temp <= 2) { - if (pll == ALT_CLK_MAIN_PLL) + if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) { - temp = (ALT_CLKMGR_MAINPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_MAINPLL_VCO_DENOM_CLR_MSK) - & alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); - temp |= ALT_CLKMGR_MAINPLL_VCO_NUMER_SET(pll_cfg->mult) | - ALT_CLKMGR_MAINPLL_VCO_DENOM_SET(pll_cfg->div); - alt_write_word(ALT_CLKMGR_MAINPLL_VCO_ADDR, temp); - alt_write_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR, pll_cfg->cntrs[0]); - alt_write_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, pll_cfg->cntrs[1]); - alt_write_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR, pll_cfg->cntrs[2]); - alt_write_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, pll_cfg->cntrs[3]); - alt_write_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, pll_cfg->cntrs[4]); - alt_write_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, pll_cfg->cntrs[5]); - ret = ALT_E_SUCCESS; + pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1; } - else if (pll == ALT_CLK_PERIPHERAL_PLL) + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) { - temp = ALT_CLKMGR_PERPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_PERPLL_VCO_DENOM_CLR_MSK - & ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK; - temp &= alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); - temp |= ALT_CLKMGR_PERPLL_VCO_NUMER_SET(pll_cfg->mult) - | ALT_CLKMGR_PERPLL_VCO_DENOM_SET(pll_cfg->div); - if ((pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC1) || (pll_cfg->ref_clk == ALT_CLK_OSC1)) - { - temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1); - } - else if (pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC2) - { - temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2); - } - else if (pll_cfg->ref_clk == ALT_CLK_F2H_PERIPH_REF) - { - temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF); - } - else { return ret; } - - alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp); - alt_write_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, pll_cfg->cntrs[0]); - alt_write_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, pll_cfg->cntrs[1]); - alt_write_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, pll_cfg->cntrs[2]); - alt_write_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, pll_cfg->cntrs[3]); - alt_write_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, pll_cfg->cntrs[4]); - alt_write_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR, pll_cfg->cntrs[5]); - ret = ALT_E_SUCCESS; + pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC2; } - else if (pll == ALT_CLK_SDRAM_PLL) + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) { - // write the SDRAM PLL VCO Counter ----------------------------- - temp = ALT_CLKMGR_SDRPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_SDRPLL_VCO_DENOM_CLR_MSK - & ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK; // make a mask - temp &= alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); - temp |= ALT_CLKMGR_SDRPLL_VCO_NUMER_SET(pll_cfg->mult) - | ALT_CLKMGR_SDRPLL_VCO_DENOM_SET(pll_cfg->div) - | ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK; - // setting this bit aligns the output phase of the counters and prevents - // glitches and too-short clock periods when restarting. - // this bit is cleared at the end of this routine - - if ((pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC1) || (pll_cfg->ref_clk == ALT_CLK_OSC1)) - { - temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1); - } - else if (pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC2) - { - temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2); - } - else if (pll_cfg->ref_clk == ALT_CLK_F2H_PERIPH_REF) - { - temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF); - } - else { return ret; } - alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp); + pll_cfg->ref_clk = ALT_CLK_F2H_PERIPH_REF; + } - // write the SDRAM PLL C0 Divide Counter ----------------------------- - temp = ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET(pll_cfg->cntrs[0]) - | ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET(pll_cfg->pshift[0]); + temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + pll_cfg->mult = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp); + pll_cfg->div = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp); - alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, - ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR, temp, - ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET_MSK, - ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB); + // Get the C0-C5 divider values: + pll_cfg->cntrs[0] = ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR)); + // C0 - emac0_clk - // write the SDRAM PLL C1 Divide Counter ----------------------------- - if (ret == ALT_E_SUCCESS) - { - temp = ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET(pll_cfg->cntrs[1]) - | ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET(pll_cfg->pshift[1]); - alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, - ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR, temp, - ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET_MSK, - ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_LSB); - } + pll_cfg->cntrs[1] = ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR)); + // C1 - emac1_clk - // write the SDRAM PLL C2 Divide Counter ----------------------------- - if (ret == ALT_E_SUCCESS) - { - temp = ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET(pll_cfg->cntrs[2]) - | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET(pll_cfg->pshift[2]); - alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, - ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR, temp, - ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET_MSK, - ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_LSB); - } + pll_cfg->cntrs[2] = ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR)); + // C2 - periph_qspi_clk - // write the SDRAM PLL C5 Divide Counter ----------------------------- - if (ret == ALT_E_SUCCESS) - { - temp = ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET(pll_cfg->cntrs[2]) - | ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET(pll_cfg->pshift[2]); - alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, - ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR, temp, - ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET_MSK, - ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_LSB); - } + pll_cfg->cntrs[3] = ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR)); + // C3 - periph_nand_sdmmc_clk - if (ret == ALT_E_SUCCESS) - { - alt_clrbits_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK); - // allow the phase multiplexer and output counter to leave reset - } + pll_cfg->cntrs[4] = ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR)); + // C4 - periph_base_clk + + pll_cfg->cntrs[5] = ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR)); + // C5 - s2f_user1_clk + + // The Peripheral PLL C0-C5 outputs have no phase shift capabilities : + pll_cfg->pshift[0] = pll_cfg->pshift[1] = pll_cfg->pshift[2] = + pll_cfg->pshift[3] = pll_cfg->pshift[4] = pll_cfg->pshift[5] = 0; + ret = ALT_E_SUCCESS; + } + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); + if (temp <= 2) + { + if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) + { + pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1; } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) + { + pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC2; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) + { + pll_cfg->ref_clk = ALT_CLK_F2H_SDRAM_REF; + } + + pll_cfg->mult = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); + pll_cfg->div = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); + + // Get the C0-C5 divider values: + pll_cfg->cntrs[0] = ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR)); + pll_cfg->pshift[0] = ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR)); + // C0 - ddr_dqs_clk + + pll_cfg->cntrs[1] = ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR)); + pll_cfg->pshift[1] = ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR)); + // C1 - ddr_2x_dqs_clk + + pll_cfg->cntrs[2] = ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR)); + pll_cfg->pshift[2] = ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR)); + // C2 - ddr_dq_clk + + pll_cfg->cntrs[3] = pll_cfg->cntrs[4] = pll_cfg->pshift[3] = pll_cfg->pshift[4] = 0; + // C3 & C4 outputs don't exist on the SDRAM PLL + + pll_cfg->cntrs[5] = ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR)); + pll_cfg->pshift[5] = ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR)); + // C5 - s2f_user2_clk or h2f_user2_clk + + ret = ALT_E_SUCCESS; } } + return ret; } -/****************************************************************************************/ -/* alt_clk_pll_vco_cfg_get() returns the current PLL VCO frequency configuration. */ -/****************************************************************************************/ - -ALT_STATUS_CODE alt_clk_pll_vco_cfg_get(ALT_CLK_t pll, uint32_t* mult, uint32_t* div) +// +// alt_clk_pll_cfg_set() sets the PLL configuration using the configuration parameters +// specified in pll_cfg. +// +ALT_STATUS_CODE alt_clk_pll_cfg_set(ALT_CLK_t pll, const ALT_CLK_PLL_CFG_t * pll_cfg) { - ALT_STATUS_CODE ret = ALT_E_ERROR; - uint32_t temp; + if (pll_cfg == NULL) + { + return ALT_E_BAD_ARG; + } - if ((mult != NULL) && (div != NULL)) + if (alt_clk_pll_is_bypassed(pll) != ALT_E_TRUE) // safe to write the PLL registers? { - if (pll == ALT_CLK_MAIN_PLL) + return ALT_E_ERROR; + } + + ALT_STATUS_CODE ret = ALT_E_ERROR; + uint32_t temp; + + if (pll == ALT_CLK_MAIN_PLL) + { + temp = (ALT_CLKMGR_MAINPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_MAINPLL_VCO_DENOM_CLR_MSK) + & alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); + temp |= ALT_CLKMGR_MAINPLL_VCO_NUMER_SET(pll_cfg->mult) | + ALT_CLKMGR_MAINPLL_VCO_DENOM_SET(pll_cfg->div); + + alt_write_word(ALT_CLKMGR_MAINPLL_VCO_ADDR, temp); + alt_write_word(ALT_CLKMGR_ALTERA_MPUCLK_ADDR, pll_cfg->cntrs[0]); + alt_write_word(ALT_CLKMGR_ALTERA_MAINCLK_ADDR, pll_cfg->cntrs[1]); + alt_write_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR, pll_cfg->cntrs[2]); + alt_write_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, pll_cfg->cntrs[3]); + alt_write_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, pll_cfg->cntrs[4]); + alt_write_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, pll_cfg->cntrs[5]); + ret = ALT_E_SUCCESS; + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + temp = ALT_CLKMGR_PERPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_PERPLL_VCO_DENOM_CLR_MSK + & ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK; + temp &= alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + temp |= ALT_CLKMGR_PERPLL_VCO_NUMER_SET(pll_cfg->mult) + | ALT_CLKMGR_PERPLL_VCO_DENOM_SET(pll_cfg->div); + + if ((pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC1) || (pll_cfg->ref_clk == ALT_CLK_OSC1)) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); - *mult = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp) + 1; - *div = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp) + 1; - ret = ALT_E_SUCCESS; + temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1); } - else if (pll == ALT_CLK_PERIPHERAL_PLL) + else if (pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC2) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); - *mult = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp) + 1; - *div = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp) + 1; - ret = ALT_E_SUCCESS; + temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2); } - else if (pll == ALT_CLK_SDRAM_PLL) + else if (pll_cfg->ref_clk == ALT_CLK_F2H_PERIPH_REF) { - temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); - *mult = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(temp) + 1; - *div = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(temp) + 1; - ret = ALT_E_SUCCESS; + temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF); + } + else + { + return ret; + } + + alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp); + alt_write_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, pll_cfg->cntrs[0]); + alt_write_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, pll_cfg->cntrs[1]); + alt_write_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, pll_cfg->cntrs[2]); + alt_write_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, pll_cfg->cntrs[3]); + alt_write_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, pll_cfg->cntrs[4]); + alt_write_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR, pll_cfg->cntrs[5]); + ret = ALT_E_SUCCESS; + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + // write the SDRAM PLL VCO Counter ----------------------------- + temp = ALT_CLKMGR_SDRPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_SDRPLL_VCO_DENOM_CLR_MSK + & ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK; // make a mask + temp &= alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); + temp |= ALT_CLKMGR_SDRPLL_VCO_NUMER_SET(pll_cfg->mult) + | ALT_CLKMGR_SDRPLL_VCO_DENOM_SET(pll_cfg->div) + | ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK; + // setting this bit aligns the output phase of the counters and prevents + // glitches and too-short clock periods when restarting. + // this bit is cleared at the end of this routine + + if ((pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC1) || (pll_cfg->ref_clk == ALT_CLK_OSC1)) + { + temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1); + } + else if (pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC2) + { + temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2); + } + else if (pll_cfg->ref_clk == ALT_CLK_F2H_PERIPH_REF) + { + temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF); + } + else + { + return ret; + } + + alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp); + + // write the SDRAM PLL C0 Divide Counter ----------------------------- + temp = ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET(pll_cfg->cntrs[0]) + | ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET(pll_cfg->pshift[0]); + + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR, temp, + ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET_MSK, + ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB); + + // write the SDRAM PLL C1 Divide Counter ----------------------------- + if (ret == ALT_E_SUCCESS) + { + temp = ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET(pll_cfg->cntrs[1]) + | ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET(pll_cfg->pshift[1]); + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR, temp, + ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET_MSK, + ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_LSB); + } + + // write the SDRAM PLL C2 Divide Counter ----------------------------- + if (ret == ALT_E_SUCCESS) + { + temp = ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET(pll_cfg->cntrs[2]) + | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET(pll_cfg->pshift[2]); + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR, temp, + ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET_MSK, + ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_LSB); + } + + // write the SDRAM PLL C5 Divide Counter ----------------------------- + if (ret == ALT_E_SUCCESS) + { + temp = ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET(pll_cfg->cntrs[2]) + | ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET(pll_cfg->pshift[2]); + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, + ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR, temp, + ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET_MSK, + ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_LSB); + } + + if (ret == ALT_E_SUCCESS) + { + alt_clrbits_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK); + // allow the phase multiplexer and output counter to leave reset } } + return ret; } +// +// alt_clk_pll_vco_cfg_get() returns the current PLL VCO frequency configuration. +// +ALT_STATUS_CODE alt_clk_pll_vco_cfg_get(ALT_CLK_t pll, uint32_t * mult, uint32_t * div) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + uint32_t temp; + + if ( (mult == NULL) || (div == NULL) ) + { + return ALT_E_BAD_ARG; + } + + if (pll == ALT_CLK_MAIN_PLL) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); + *mult = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp) + 1; + *div = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp) + 1; + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + *mult = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp) + 1; + *div = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp) + 1; + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); + *mult = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(temp) + 1; + *div = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(temp) + 1; + } + else + { + status = ALT_E_ERROR; + } + + return status; +} + + /****************************************************************************************/ /* This enum enumerates a set of possible change methods that are available for use by */ /* alt_clk_pll_vco_cfg_set() to change VCO parameter settings. */ @@ -2123,10 +2164,20 @@ static ALT_CLK_PLL_VCO_CHG_METHOD_t alt_clk_pll_vco_chg_methods_get(ALT_CLK_t pl uint32_t mult, uint32_t div ) { #if ALT_CLK_PLL_VCO_CHG_METHOD_TEST_MODE + // used for testing - return ALT_VCO_CHG_NOCHANGE; + return ALT_VCO_CHG_NOCHANGE; + +#else + + // check PLL max value limits + if ( (mult == 0) || (mult > ALT_CLK_PLL_MULT_MAX) + || (div == 0) || (div > ALT_CLK_PLL_DIV_MAX) + ) + { + return ALT_VCO_CHG_NONE_VALID; + } -#endif ALT_CLK_PLL_VCO_CHG_METHOD_t ret = ALT_VCO_CHG_NONE_VALID; uint32_t temp; uint32_t numer; @@ -2139,124 +2190,148 @@ static ALT_CLK_PLL_VCO_CHG_METHOD_t alt_clk_pll_vco_chg_methods_get(ALT_CLK_t pl bool denomchg = false; bool within_gb; - if ((mult > 0) && (mult <= ALT_CLK_PLL_MULT_MAX) && (div > 0) - && (div <= ALT_CLK_PLL_DIV_MAX)) // check PLL max value limits + // gather data values according to PLL + if (pll == ALT_CLK_MAIN_PLL) { - // gather data values according to PLL - if (pll == ALT_CLK_MAIN_PLL) + temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); + + numer = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp); + + freqmax = alt_pll_clk_paramblok.MainPLL_800.freqmax; + freqmin = alt_pll_clk_paramblok.MainPLL_800.freqmin; + guardband = alt_pll_clk_paramblok.MainPLL_800.guardband; + + inputfreq = alt_ext_clk_paramblok.clkosc1.freqcur; + } + + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + + numer = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp); + + freqmax = alt_pll_clk_paramblok.PeriphPLL_800.freqmax; + freqmin = alt_pll_clk_paramblok.PeriphPLL_800.freqmin; + guardband = alt_pll_clk_paramblok.PeriphPLL_800.guardband; + + temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(temp); + if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); - numer = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp); - denom = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp); - freqmax = alt_pll_clk_paramblok.MainPLL_800.freqmax; - freqmin = alt_pll_clk_paramblok.MainPLL_800.freqmin; - guardband = alt_pll_clk_paramblok.MainPLL_800.guardband; inputfreq = alt_ext_clk_paramblok.clkosc1.freqcur; } - - else if (pll == ALT_CLK_PERIPHERAL_PLL) + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); - numer = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp); - denom = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp); - temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(temp); - freqmax = alt_pll_clk_paramblok.PeriphPLL_800.freqmax; - freqmin = alt_pll_clk_paramblok.PeriphPLL_800.freqmin; - guardband = alt_pll_clk_paramblok.PeriphPLL_800.guardband; - if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) - { - inputfreq = alt_ext_clk_paramblok.clkosc1.freqcur; - } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) - { - inputfreq = alt_ext_clk_paramblok.clkosc2.freqcur; - } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) - { - inputfreq = alt_ext_clk_paramblok.periph.freqcur; - } - else { return ret; } + inputfreq = alt_ext_clk_paramblok.clkosc2.freqcur; } - - else if (pll == ALT_CLK_SDRAM_PLL) + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) { - temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); - numer = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(temp); - denom = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(temp); - temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(temp); - freqmax = alt_pll_clk_paramblok.SDRAMPLL_800.freqmax; - freqmin = alt_pll_clk_paramblok.SDRAMPLL_800.freqmin; - guardband = alt_pll_clk_paramblok.SDRAMPLL_800.guardband; - if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) - { - inputfreq = alt_ext_clk_paramblok.clkosc1.freqcur; - } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) - { - inputfreq = alt_ext_clk_paramblok.clkosc2.freqcur; - } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) - { - inputfreq = alt_ext_clk_paramblok.sdram.freqcur; - } - else { return ret; } + inputfreq = alt_ext_clk_paramblok.periph.freqcur; } - else { return ret; } + else + { + return ret; + } + } - temp = (mult * inputfreq) / div; - if ((temp <= freqmax) && (temp >= freqmin)) // are the final values within frequency limits? + else if (pll == ALT_CLK_SDRAM_PLL) + { + temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); + + numer = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(temp); + + freqmax = alt_pll_clk_paramblok.SDRAMPLL_800.freqmax; + freqmin = alt_pll_clk_paramblok.SDRAMPLL_800.freqmin; + guardband = alt_pll_clk_paramblok.SDRAMPLL_800.guardband; + + temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(temp); + if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) { - numer++; - denom++; - numerchg = (mult != numer); - denomchg = (div != denom); + inputfreq = alt_ext_clk_paramblok.clkosc1.freqcur; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) + { + inputfreq = alt_ext_clk_paramblok.clkosc2.freqcur; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) + { + inputfreq = alt_ext_clk_paramblok.sdram.freqcur; + } + else + { + return ret; + } + } + else + { + return ret; + } - if (!numerchg && !denomchg) + temp = mult * (inputfreq / div); + if ((temp <= freqmax) && (temp >= freqmin)) // are the final values within frequency limits? + { + numer++; + denom++; + numerchg = (mult != numer); + denomchg = (div != denom); + + if (!numerchg && !denomchg) + { + ret = ALT_VCO_CHG_NOCHANGE; + } + else if (numerchg && !denomchg) + { + within_gb = alt_within_delta(numer, mult, guardband); + // check if change is within the guardband limits + temp = mult * (inputfreq / denom); + if ((temp <= freqmax) && (temp >= freqmin)) { - ret = ALT_VCO_CHG_NOCHANGE; + ret = ALT_VCO_CHG_NUM; + if (!within_gb) ret |= ALT_VCO_CHG_NUM_BYP; } - else if (numerchg && !denomchg) + } + else if (!numerchg && denomchg) + { + within_gb = alt_within_delta(denom, div, guardband); + temp = numer * (inputfreq / div); + if ((temp <= freqmax) && (temp >= freqmin)) { - within_gb = alt_within_delta(numer, mult, guardband); - // check if change is within the guardband limits - temp = (mult * inputfreq) / denom; - if ((temp <= freqmax) && (temp >= freqmin)) + ret = ALT_VCO_CHG_DENOM; + if (!within_gb) { - ret = ALT_VCO_CHG_NUM; - if (!within_gb) ret |= ALT_VCO_CHG_NUM_BYP; + ret |= ALT_VCO_CHG_DENOM_BYP; } } - else if (!numerchg && denomchg) + } + else //numerchg && denomchg + { + within_gb = alt_within_delta(numer, mult, guardband); + temp = mult * (inputfreq / denom); + if ((temp <= freqmax) && (temp >= freqmin)) { - within_gb = alt_within_delta(denom, div, guardband); - temp = (numer * inputfreq) / div; - if ((temp <= freqmax) && (temp >= freqmin)) + ret = ALT_VCO_CHG_NUM_DENOM; + if (!within_gb) { - ret = ALT_VCO_CHG_DENOM; - if (!within_gb) ret |= ALT_VCO_CHG_DENOM_BYP; + ret |= ALT_VCO_CHG_NUM_DENOM_BYP; } } - else //numerchg && denomchg + within_gb = alt_within_delta(denom, div, guardband); + temp = numer * (inputfreq / div); + if ((temp <= freqmax) && (temp >= freqmin)) { - within_gb = alt_within_delta(numer, mult, guardband); - temp = (mult * inputfreq) / denom; - if ((temp <= freqmax) && (temp >= freqmin)) + ret = ALT_VCO_CHG_DENOM_NUM; + if (!within_gb) { - ret = ALT_VCO_CHG_NUM_DENOM; - if (!within_gb) ret |= ALT_VCO_CHG_NUM_DENOM_BYP; - } - within_gb = alt_within_delta(denom, div, guardband); - temp = (numer * inputfreq) / div; - if ((temp <= freqmax) && (temp >= freqmin)) - { - ret = ALT_VCO_CHG_DENOM_NUM; - if (!within_gb) ret |= ALT_VCO_CHG_DENOM_NUM_BYP; + ret |= ALT_VCO_CHG_DENOM_NUM_BYP; } } } } return ret; +#endif } @@ -2387,15 +2462,13 @@ ALT_STATUS_CODE alt_clk_pll_vco_cfg_set(ALT_CLK_t pll, uint32_t mult, uint32_t d } -/****************************************************************************************/ -/* alt_clk_pll_vco_freq_get() gets the VCO frequency of the specified PLL. */ -/* Note that since there is at present no known way for software to obtain the speed */ -/* bin of the SoC or MPU that it is running on, the function below only deals with the */ -/* 800 MHz part. This may need to be revised in the future. */ -/****************************************************************************************/ - - -ALT_STATUS_CODE alt_clk_pll_vco_freq_get(ALT_CLK_t pll, alt_freq_t* freq) +// +// alt_clk_pll_vco_freq_get() gets the VCO frequency of the specified PLL. +// Note that since there is at present no known way for software to obtain the speed +// bin of the SoC or MPU that it is running on, the function below only deals with the +// 800 MHz part. This may need to be revised in the future. +// +ALT_STATUS_CODE alt_clk_pll_vco_freq_get(ALT_CLK_t pll, alt_freq_t * freq) { uint64_t temp1 = 0; uint32_t temp; @@ -2403,99 +2476,120 @@ ALT_STATUS_CODE alt_clk_pll_vco_freq_get(ALT_CLK_t pll, alt_freq_t* freq) uint32_t denom; ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - if (freq != NULL) + if (freq == NULL) { - if (pll == ALT_CLK_MAIN_PLL) + return ret; + } + + if (pll == ALT_CLK_MAIN_PLL) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); + numer = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp); + temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc1.freqcur; + temp1 *= (numer + 1); + temp1 /= (denom + 1); + + if (temp1 <= UINT32_MAX) + { + temp = (alt_freq_t) temp1; + alt_pll_clk_paramblok.MainPLL_800.freqcur = temp; + // store this value in the parameter block table + *freq = temp; + // should NOT check value against PLL frequency limits + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ERROR; + } + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + numer = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp); + temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(temp); + if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); - numer = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp); - denom = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp); temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc1.freqcur; + } + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) + { + temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc2.freqcur; + } + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) + { + temp1 = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; + } + + if (temp1 != 0) + { temp1 *= (numer + 1); temp1 /= (denom + 1); if (temp1 <= UINT32_MAX) { temp = (alt_freq_t) temp1; - alt_pll_clk_paramblok.MainPLL_800.freqcur = temp; - // store this value in the parameter block table + alt_pll_clk_paramblok.PeriphPLL_800.freqcur = temp; + // store this value in the parameter block table + *freq = temp; - // should NOT check value against PLL frequency limits ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ERROR; } + else + { + ret = ALT_E_ERROR; + } + } // this returns ALT_BAD_ARG if the source isn't known + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); + numer = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(temp); + temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(temp); + if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) + { + temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc1.freqcur; } - else if (pll == ALT_CLK_PERIPHERAL_PLL) + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); - numer = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp); - denom = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp); - temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(temp); - if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) - { temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc1.freqcur; } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) - { temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc2.freqcur; } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) - { temp1 = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; } - - if (temp1 != 0) - { - temp1 *= (numer + 1); - temp1 /= (denom + 1); - if (temp1 <= UINT32_MAX) - { - temp = (alt_freq_t) temp1; - alt_pll_clk_paramblok.PeriphPLL_800.freqcur = temp; - // store this value in the parameter block table - - *freq = temp; - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ERROR; } - } // this returns ALT_BAD_ARG if the source isn't known + temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc2.freqcur; } - else if (pll == ALT_CLK_SDRAM_PLL) + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) { - temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); - numer = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(temp); - denom = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(temp); - temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(temp); - if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) - { temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc1.freqcur; } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) - { temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc2.freqcur; } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) - { temp1 = (uint64_t) alt_ext_clk_paramblok.sdram.freqcur; } + temp1 = (uint64_t) alt_ext_clk_paramblok.sdram.freqcur; + } - if (temp1 != 0) + if (temp1 != 0) + { + temp1 *= (numer + 1); + temp1 /= (denom + 1); + if (temp1 <= UINT32_MAX) { - temp1 *= (numer + 1); - temp1 /= (denom + 1); - if (temp1 <= UINT32_MAX) - { - temp = (alt_freq_t) temp1; - alt_pll_clk_paramblok.SDRAMPLL_800.freqcur = temp; - // store this value in the parameter block table + temp = (alt_freq_t) temp1; + alt_pll_clk_paramblok.SDRAMPLL_800.freqcur = temp; + // store this value in the parameter block table - *freq = temp; - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ERROR; } + *freq = temp; + ret = ALT_E_SUCCESS; } - } // which returns ALT_BAD_ARG if the source isn't known - } + else + { + ret = ALT_E_ERROR; + } + } + } // which returns ALT_BAD_ARG if the source isn't known + return ret; } - -/****************************************************************************************/ -/* Returns the current guard band range in effect for the PLL. */ -/****************************************************************************************/ - - +// +// Returns the current guard band range in effect for the PLL. +// uint32_t alt_clk_pll_guard_band_get(ALT_CLK_t pll) { - int32_t ret = 0; + uint32_t ret = 0; if (pll == ALT_CLK_MAIN_PLL) { @@ -2512,297 +2606,315 @@ uint32_t alt_clk_pll_guard_band_get(ALT_CLK_t pll) return ret; } - -/****************************************************************************************/ -/* clk_mgr_pll_guard_band_set() changes the guard band from its current value to permit */ -/* a more lenient or stringent policy to be in effect for the implementation of the */ -/* functions configuring PLL VCO frequency. */ -/****************************************************************************************/ - +// +// clk_mgr_pll_guard_band_set() changes the guard band from its current value to permit +// a more lenient or stringent policy to be in effect for the implementation of the +// functions configuring PLL VCO frequency. +// ALT_STATUS_CODE alt_clk_pll_guard_band_set(ALT_CLK_t pll, uint32_t guard_band) { - ALT_STATUS_CODE ret = ALT_E_ERROR; - - if ((guard_band <= UINT12_MAX) && (guard_band > 0) && (guard_band <= ALT_GUARDBAND_LIMIT)) + if ( (guard_band > UINT12_MAX) || (guard_band <= 0) + || (guard_band > ALT_GUARDBAND_LIMIT) + ) { - if (pll == ALT_CLK_MAIN_PLL) - { - alt_pll_clk_paramblok.MainPLL_800.guardband = guard_band; - //alt_pll_clk_paramblok.MainPLL_600.guardband = guard_band; - // ??? Don't know how to check the MPU speed bin yet, so only 800 MHz struct is used - ret = ALT_E_SUCCESS; - } - else if (pll == ALT_CLK_PERIPHERAL_PLL) - { - alt_pll_clk_paramblok.PeriphPLL_800.guardband = guard_band; - //alt_pll_clk_paramblok.PeriphPLL_600.guardband = guard_band; - ret = ALT_E_SUCCESS; - } - else if (pll == ALT_CLK_SDRAM_PLL) - { - alt_pll_clk_paramblok.SDRAMPLL_800.guardband = guard_band; - //alt_pll_clk_paramblok.SDRAMPLL_600.guardband = guard_band; - ret = ALT_E_SUCCESS; - } + return ALT_E_ARG_RANGE; } - else { ret = ALT_E_ARG_RANGE; } - return ret; -} + ALT_STATUS_CODE status = ALT_E_SUCCESS; -/****************************************************************************************/ -/* alt_clk_divider_get() gets configured divider value for the specified clock. */ -/****************************************************************************************/ + if (pll == ALT_CLK_MAIN_PLL) + { + alt_pll_clk_paramblok.MainPLL_800.guardband = guard_band; + //alt_pll_clk_paramblok.MainPLL_600.guardband = guard_band; + // ??? Don't know how to check the MPU speed bin yet, so only 800 MHz struct is used + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + alt_pll_clk_paramblok.PeriphPLL_800.guardband = guard_band; + //alt_pll_clk_paramblok.PeriphPLL_600.guardband = guard_band; + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + alt_pll_clk_paramblok.SDRAMPLL_800.guardband = guard_band; + //alt_pll_clk_paramblok.SDRAMPLL_600.guardband = guard_band; + } + else + { + status = ALT_E_ERROR; + } + + return status; +} -ALT_STATUS_CODE alt_clk_divider_get(ALT_CLK_t clk, uint32_t* div) +// +// alt_clk_divider_get() gets configured divider value for the specified clock. +// +ALT_STATUS_CODE alt_clk_divider_get(ALT_CLK_t clk, uint32_t * div) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - uint32_t temp; + ALT_STATUS_CODE status = ALT_E_SUCCESS; + uint32_t temp; - if (div != NULL) + if (div == NULL) { - switch (clk) - { - /* Main PLL outputs */ - case ALT_CLK_MAIN_PLL_C0: - case ALT_CLK_MPU: - *div = (ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR)) + 1) << 1; - // adjust for the additional divide-by-2 internal counter on C0 - ret = ALT_E_SUCCESS; - break; + return ALT_E_BAD_ARG; + } - case ALT_CLK_MAIN_PLL_C1: - case ALT_CLK_L4_MAIN: - case ALT_CLK_L3_MAIN: - *div = (ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR)) + 1) << 2; - // adjust for the additional divide-by-4 internal counter on C1 - ret = ALT_E_SUCCESS; - break; + switch (clk) + { + // Main PLL outputs + case ALT_CLK_MAIN_PLL_C0: + case ALT_CLK_MPU: + *div = (ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR)) + 1) * + (ALT_CLKMGR_ALTERA_MPUCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MPUCLK_ADDR)) + 1); + break; - case ALT_CLK_MAIN_PLL_C2: - case ALT_CLK_DBG_BASE: - case ALT_CLK_DBG_TIMER: - *div = (ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR)) + 1) << 2; - // adjust for the additional divide-by-4 internal counter on C2 - ret = ALT_E_SUCCESS; - break; + case ALT_CLK_MAIN_PLL_C1: + case ALT_CLK_L4_MAIN: + case ALT_CLK_L3_MAIN: + *div = (ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR)) + 1) * + (ALT_CLKMGR_ALTERA_MAINCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MAINCLK_ADDR)) + 1); + break; - case ALT_CLK_MAIN_PLL_C3: - case ALT_CLK_MAIN_QSPI: - *div = (ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; + case ALT_CLK_MAIN_PLL_C2: + case ALT_CLK_DBG_BASE: + case ALT_CLK_DBG_TIMER: + *div = (ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR)) + 1) * + (ALT_CLKMGR_ALTERA_DBGATCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_DBGATCLK_ADDR)) + 1); + break; - case ALT_CLK_MAIN_PLL_C4: - case ALT_CLK_MAIN_NAND_SDMMC: - *div = (ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; + case ALT_CLK_MAIN_PLL_C3: + case ALT_CLK_MAIN_QSPI: + *div = (ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR))) + 1; + break; - case ALT_CLK_MAIN_PLL_C5: - case ALT_CLK_CFG: - case ALT_CLK_H2F_USER0: - *div = (ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - - /* Peripheral PLL outputs */ - case ALT_CLK_PERIPHERAL_PLL_C0: - case ALT_CLK_EMAC0: - *div = (ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_PERIPHERAL_PLL_C1: - case ALT_CLK_EMAC1: - *div = (ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_PERIPHERAL_PLL_C2: - *div = (ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_PERIPHERAL_PLL_C3: - *div = (ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_PERIPHERAL_PLL_C4: - *div = (ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_PERIPHERAL_PLL_C5: - case ALT_CLK_H2F_USER1: - *div = (ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - - /* SDRAM PLL outputs */ - case ALT_CLK_SDRAM_PLL_C0: - case ALT_CLK_DDR_DQS: - *div = (ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_SDRAM_PLL_C1: - case ALT_CLK_DDR_2X_DQS: - *div = (ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_SDRAM_PLL_C2: - case ALT_CLK_DDR_DQ: - *div = (ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_SDRAM_PLL_C5: - case ALT_CLK_H2F_USER2: - *div = (ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - - /* Other clock dividers */ - case ALT_CLK_L3_MP: - temp = ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); - if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2) - { - *div = temp + 1; - ret = ALT_E_SUCCESS; - } - break; + case ALT_CLK_MAIN_PLL_C4: + case ALT_CLK_MAIN_NAND_SDMMC: + *div = (ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR))) + 1; + break; - case ALT_CLK_L3_SP: - temp = ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); - if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2) - { - *div = temp + 1; - ret = ALT_E_SUCCESS; - } - // note that this value does not include the additional effect - // of the L3_MP divider that is upchain from this one - break; + case ALT_CLK_MAIN_PLL_C5: + case ALT_CLK_CFG: + case ALT_CLK_H2F_USER0: + *div = (ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR))) + 1; + break; - case ALT_CLK_L4_MP: - temp = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); - if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + ///// - case ALT_CLK_L4_SP: - temp = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); - if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + // Peripheral PLL outputs + case ALT_CLK_PERIPHERAL_PLL_C0: + case ALT_CLK_EMAC0: + *div = (ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR))) + 1; + break; - case ALT_CLK_DBG_AT: - temp = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR)); - if (temp <= ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + case ALT_CLK_PERIPHERAL_PLL_C1: + case ALT_CLK_EMAC1: + *div = (ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR))) + 1; + break; - case ALT_CLK_DBG: - temp = ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR)); - if (temp <= ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - // note that this value does not include the value of the upstream dbg_at_clk divder - break; + case ALT_CLK_PERIPHERAL_PLL_C2: + *div = (ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR))) + 1; + break; - case ALT_CLK_DBG_TRACE: - temp = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR)); - if (temp <= ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + case ALT_CLK_PERIPHERAL_PLL_C3: + *div = (ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR))) + 1; + break; - case ALT_CLK_USB_MP: - temp = ALT_CLKMGR_PERPLL_DIV_USBCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); - if (temp <= ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + case ALT_CLK_PERIPHERAL_PLL_C4: + *div = (ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR))) + 1; + break; - case ALT_CLK_SPI_M: - temp = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); - if (temp <= ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + case ALT_CLK_PERIPHERAL_PLL_C5: + case ALT_CLK_H2F_USER1: + *div = (ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR))) + 1; + break; - case ALT_CLK_CAN0: - temp = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); - if (temp <= ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + ///// - case ALT_CLK_CAN1: - temp = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); - if (temp <= ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + // SDRAM PLL outputs + case ALT_CLK_SDRAM_PLL_C0: + case ALT_CLK_DDR_DQS: + *div = (ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR))) + 1; + break; - case ALT_CLK_GPIO_DB: - temp = ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR)); - *div = temp + 1; - ret = ALT_E_SUCCESS; - break; + case ALT_CLK_SDRAM_PLL_C1: + case ALT_CLK_DDR_2X_DQS: + *div = (ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR))) + 1; + break; - case ALT_CLK_MPU_PERIPH: - *div = 4; // set by hardware - ret = ALT_E_SUCCESS; - break; + case ALT_CLK_SDRAM_PLL_C2: + case ALT_CLK_DDR_DQ: + *div = (ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR))) + 1; + break; - case ALT_CLK_MPU_L2_RAM: - *div = 2; // set by hardware - ret = ALT_E_SUCCESS; - break; + case ALT_CLK_SDRAM_PLL_C5: + case ALT_CLK_H2F_USER2: + *div = (ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR))) + 1; + break; - case ALT_CLK_NAND: - *div = 4; // set by hardware - ret = ALT_E_SUCCESS; - break; + ///// - default: - break; - } - } - return ret; -} + // Other clock dividers + case ALT_CLK_L3_MP: + temp = ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2) + { + *div = temp + 1; + } + else + { + status = ALT_E_ERROR; + } + break; + case ALT_CLK_L3_SP: + temp = ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2) + { + *div = temp + 1; + } + else + { + status = ALT_E_ERROR; + } + // note that this value does not include the additional effect + // of the L3_MP divider that is upchain from this one + break; -/****************************************************************************************/ + case ALT_CLK_L4_MP: + temp = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; -/****************************************************************************************/ + case ALT_CLK_L4_SP: + temp = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_DBG_AT: + temp = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_DBG: + temp = ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + // note that this value does not include the value of the upstream dbg_at_clk divder + break; + + case ALT_CLK_DBG_TRACE: + temp = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_USB_MP: + temp = ALT_CLKMGR_PERPLL_DIV_USBCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); + if (temp <= ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_SPI_M: + temp = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); + if (temp <= ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_CAN0: + temp = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); + if (temp <= ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_CAN1: + temp = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); + if (temp <= ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_GPIO_DB: + temp = ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR)); + *div = temp + 1; + break; + + case ALT_CLK_MPU_PERIPH: + *div = 4; // set by hardware + break; + + case ALT_CLK_MPU_L2_RAM: + *div = 2; // set by hardware + break; + + case ALT_CLK_NAND: + *div = 4; // set by hardware + break; + + default: + status = ALT_E_BAD_ARG; + break; + } + + return status; +} + +///// #define ALT_CLK_WITHIN_FREQ_LIMITS_TEST_MODE false // used for testing writes to the the full range of counters without @@ -2811,143 +2923,156 @@ ALT_STATUS_CODE alt_clk_divider_get(ALT_CLK_t clk, uint32_t* div) static ALT_STATUS_CODE alt_clk_within_freq_limits(ALT_CLK_t clk, uint32_t div) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - uint32_t numer; - uint32_t hilimit; - uint32_t lolimit; - #if ALT_CLK_WITHIN_FREQ_LIMITS_TEST_MODE return ALT_E_TRUE; -#endif +#else - if (div != 0) + if (div == 0) { - if (!ALT_CLK_WITHIN_FREQ_LIMITS_TEST_MODE) - { - // Normal mode - do the frequency check + return ALT_E_BAD_ARG; + } - /* Counters of the Main PLL */ - if (clk == ALT_CLK_MAIN_PLL_C0) - { - hilimit = alt_pll_cntr_maxfreq.MainPLL_C0; - lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); - } - else if (clk == ALT_CLK_MAIN_PLL_C1) - { - hilimit = alt_pll_cntr_maxfreq.MainPLL_C1; - lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); - } - else if (clk == ALT_CLK_MAIN_PLL_C2) - { - hilimit = alt_pll_cntr_maxfreq.MainPLL_C2; - lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); - } - else if (clk == ALT_CLK_MAIN_PLL_C3) - { - hilimit = alt_pll_cntr_maxfreq.MainPLL_C3; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); - } - else if (clk == ALT_CLK_MAIN_PLL_C4) - { - hilimit = alt_pll_cntr_maxfreq.MainPLL_C4; - lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); - } - else if (clk == ALT_CLK_MAIN_PLL_C5) - { - hilimit = alt_pll_cntr_maxfreq.MainPLL_C5; - lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); - } + ALT_STATUS_CODE status = ALT_E_SUCCESS; + uint32_t numer = 0; + uint32_t hilimit; + uint32_t lolimit; - /* Counters of the Peripheral PLL */ - else if (clk == ALT_CLK_PERIPHERAL_PLL_C0) - { - hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C0; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); - } - else if (clk == ALT_CLK_PERIPHERAL_PLL_C1) - { - hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C1; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); - } - else if (clk == ALT_CLK_PERIPHERAL_PLL_C2) - { - hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C2; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); - } - else if (clk == ALT_CLK_PERIPHERAL_PLL_C3) - { - hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C3; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); - } - else if (clk == ALT_CLK_PERIPHERAL_PLL_C4) - { - hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C4; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); - } - else if (clk == ALT_CLK_PERIPHERAL_PLL_C5) - { - hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C5; - lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); - } + switch (clk) + { + // Counters of the Main PLL + case ALT_CLK_MAIN_PLL_C0: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C0; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; + case ALT_CLK_MAIN_PLL_C1: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C1; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; + case ALT_CLK_MAIN_PLL_C2: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C2; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; + case ALT_CLK_MAIN_PLL_C3: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C3; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; + case ALT_CLK_MAIN_PLL_C4: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C4; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; + case ALT_CLK_MAIN_PLL_C5: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C5; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; - /* Counters of the SDRAM PLL */ - else if (clk == ALT_CLK_SDRAM_PLL_C0) - { - hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C0; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); - } - else if (clk == ALT_CLK_SDRAM_PLL_C1) - { - hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C1; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); - } - else if (clk == ALT_CLK_SDRAM_PLL_C2) - { - hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C2; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); - } - else if (clk == ALT_CLK_SDRAM_PLL_C5) - { - hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C5; - lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); - } - else { return ret; } + // Counters of the Peripheral PLL + case ALT_CLK_PERIPHERAL_PLL_C0: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C0; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; + case ALT_CLK_PERIPHERAL_PLL_C1: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C1; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; + case ALT_CLK_PERIPHERAL_PLL_C2: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C2; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; + case ALT_CLK_PERIPHERAL_PLL_C3: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C3; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; + case ALT_CLK_PERIPHERAL_PLL_C4: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C4; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; + case ALT_CLK_PERIPHERAL_PLL_C5: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C5; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; - numer = numer / div; - if ((numer <= hilimit) && (numer >= lolimit)) - { - ret = ALT_E_TRUE; - } - else { ret = ALT_E_FALSE; } + // Counters of the SDRAM PLL + case ALT_CLK_SDRAM_PLL_C0: + hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C0; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); + break; + case ALT_CLK_SDRAM_PLL_C1: + hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C1; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); + break; + case ALT_CLK_SDRAM_PLL_C2: + hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C2; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); + break; + case ALT_CLK_SDRAM_PLL_C5: + hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C5; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); + break; + + default: + status = ALT_E_BAD_ARG; + break; + } + + if (status == ALT_E_SUCCESS) + { + numer = numer / div; + if ((numer <= hilimit) && (numer >= lolimit)) + { + status = ALT_E_TRUE; + } + else + { + status = ALT_E_FALSE; } } - return ret; -} + return status; +#endif +} -/****************************************************************************************/ -/* alt_clk_divider_set() sets the divider value for the specified clock. */ -/* */ -/* See pages 38, 44, 45, and 46 of the HPS-Clocking NPP for a map of the */ -/* HPS clocking architecture and hierarchy of connections. */ -/****************************************************************************************/ +static bool alt_clkmgr_is_val_modulo_n(uint32_t div, uint32_t mod) +{ + if (mod == 1) + { + return true; + } + else if (mod == 2) + { + return (div & 0x1) == 0; + } + else if (mod == 4) + { + return (div & 0x3) == 0; + } + else + { + return (div % mod) == 0; + } +} +// +// alt_clk_divider_set() sets the divider value for the specified clock. +// +// See pages 38, 44, 45, and 46 of the HPS-Clocking NPP for a map of the +// HPS clocking architecture and hierarchy of connections. +// ALT_STATUS_CODE alt_clk_divider_set(ALT_CLK_t clk, uint32_t div) { ALT_STATUS_CODE ret = ALT_E_BAD_ARG; @@ -2957,1974 +3082,2473 @@ ALT_STATUS_CODE alt_clk_divider_set(ALT_CLK_t clk, uint32_t div) bool restore_1 = false; bool restore_2 = false; - switch (clk) + switch (clk) { - /* ------------ Main PLL outputs ------------ */ - case ALT_CLK_MAIN_PLL_C0: - case ALT_CLK_MPU: - if ((div <= ((ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET_MSK << 1) + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C0, div) == ALT_E_TRUE)) - { - wrval = (div >> 1) + 1; // adjust for the automatic divide-by-two internal counter on C0 - // HW managed clock, change by writing to the external counter, no need to gate clock - // or match phase or wait for transistion time. No other field in the register to mask off either. - // The counter does have to be reset though, using a request-and-ack method. - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_MPUCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C0, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ARG_RANGE; } - break; - - case ALT_CLK_MAIN_PLL_C1: - case ALT_CLK_L3_MAIN: - if ((div <= ((ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET_MSK << 2) + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C1, div) == ALT_E_TRUE)) - { - // HW managed clock, change by writing to the external counter, no need to gate clock - // or match phase or wait for transistion time. No other field in the register to mask off either. - - wrval = (div >> 2) + 1; // adjust for the automatic divide-by-four internal counter on C1 -#if ALT_PREVENT_GLITCH_CHGC1 - // if L4MP or L4SP source is set to Main PLL C1, gate it off before changing - // bypass state, then gate clock back on. FogBugz #63778 - temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); - temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - - if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK))) - { - restore_0 = true; - } - if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK))) - { - restore_1 = true; - } - temp = temp1; - if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } - if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } - if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); } - - // The counter does have to be reset though, using a request-and-ack method. - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C1, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - // wait a bit before reenabling the L4MP and L4SP clocks - if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp1); } + // Main PLL outputs + case ALT_CLK_MAIN_PLL_C0: + case ALT_CLK_MPU: + { + uint32_t prediv = (ALT_CLKMGR_ALTERA_MPUCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MPUCLK_ADDR)) + 1); + if ( (div <= ((ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET_MSK + 1) * prediv)) + && alt_clkmgr_is_val_modulo_n(div, prediv) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C0, div) == ALT_E_TRUE) ) + { + wrval = (div / prediv) - 1; -#else - // The counter does have to be reset though, using a request-and-ack method. - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, - div >> 2, // adjust for the automatic divide-by-four internal counter on C1 - ALT_CLK_PLL_RST_BIT_C1, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); -#endif + // HW managed clock, change by writing to the external counter, no need to gate clock + // or match phase or wait for transistion time. No other field in the register to mask off either. + alt_write_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR, wrval); ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ARG_RANGE; } - break; - - case ALT_CLK_MAIN_PLL_C2: - case ALT_CLK_DBG_BASE: - if ((div <= ((ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET_MSK << 2) + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C2, div) == ALT_E_TRUE)) - { - wrval = (div >> 2) + 1; // adjust for the automatic divide-by-four internal counter on C2 - // HW managed clock, change by writing to the external counter, no need to gate clock - // or match phase or wait for transistion time. No other field in the register to mask off either. - // The counter does have to be reset though, using a request-and-ack method. - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C2, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ARG_RANGE; } - break; - - case ALT_CLK_MAIN_PLL_C3: - // The rest of the PLL outputs do not have external counters, but - // their internal counters are programmable rather than fixed - if ((div <= (ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C3, div) == ALT_E_TRUE)) + } + else { - if (ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)) - == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) - // if the main_qspi_clk input is selected for the qspi_clk - { - restore_0 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR) & ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK; - if (restore_0) // AND if the QSPI clock is enabled - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK); - // gate off the QSPI clock - } - - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C3, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - // if the QSPI clock was gated on (enabled) before, return it to that state - } - ret = ALT_E_SUCCESS; - } + ret = ALT_E_ARG_RANGE; } - else { ret = ALT_E_ARG_RANGE; } - break; + } + break; - case ALT_CLK_MAIN_PLL_C4: - case ALT_CLK_MAIN_NAND_SDMMC: - if ((div <= (ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C4, div) == ALT_E_TRUE)) + case ALT_CLK_MAIN_PLL_C1: + case ALT_CLK_L3_MAIN: + { + uint32_t prediv = (ALT_CLKMGR_ALTERA_MAINCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MAINCLK_ADDR)) + 1); + + if ( (div <= ((ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET_MSK + 1) * prediv)) + && alt_clkmgr_is_val_modulo_n(div, prediv) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C1, div) == ALT_E_TRUE) ) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); - temp1 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + // HW managed clock, change by writing to the external counter, no need to gate clock + // or match phase or wait for transistion time. No other field in the register to mask off either. - // do we need to gate off the SDMMC clock ? - if (ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(temp) == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK) - { - if (temp1 & ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK) { restore_0 = true; } - } + wrval = (div / prediv) - 1; - // do we need to gate off the NAND clock and/or the NANDX clock? - if (ALT_CLKMGR_PERPLL_SRC_NAND_GET(temp) == ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK) - { - if (temp1 & ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK) { restore_1 = true; } - if (temp1 & ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK) { restore_2 = true; } - } +#if ALT_PREVENT_GLITCH_CHGC1 + // if L4MP or L4SP source is set to Main PLL C1, gate it off before changing + // bypass state, then gate clock back on. FogBugz #63778 + temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); + temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - temp = temp1; - if (restore_1 && restore_2) + if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK))) { - temp &= ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK; - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); - // gate nand_clk off at least 8 MPU clock cycles before before nand_x_clk + restore_0 = true; } - - if (restore_0 || restore_1) + if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK))) { - if (restore_0) { temp &= ALT_CLKMGR_PERPLL_EN_SDMMCCLK_CLR_MSK; } - if (restore_1) { temp &= ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK; } - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - // gate off sdmmc_clk and/or nand_x_clk + restore_1 = true; } + temp = temp1; + if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } + if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); } - // now write the new divisor ratio - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C4, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - + alt_write_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, wrval); - if (restore_0 || restore_1) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1 & ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK); - // if the NANDX and/or SDMMC clock was gated on (enabled) before, return it to that state - if (restore_1 && restore_2) - { - // wait at least 8 clock cycles to turn the nand_clk on - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1); - } - } + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + // wait a bit before reenabling the L4MP and L4SP clocks + if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp1); } +#else + alt_write_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, wrval); +#endif ret = ALT_E_SUCCESS; } - else { ret = ALT_E_ARG_RANGE; } - break; - - case ALT_CLK_MAIN_PLL_C5: - case ALT_CLK_CFG: - case ALT_CLK_H2F_USER0: - if ((div <= (ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C5, div) == ALT_E_TRUE)) + else { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - restore_0 = ((temp & ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK) - || (temp & ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK)); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & (ALT_CLKMGR_MAINPLL_EN_CFGCLK_CLR_MSK - & ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_CLR_MSK)); // clear 'em both - } + ret = ALT_E_ARG_RANGE; + } + } + break; - // now write the new divisor ratio - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C5, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); + case ALT_CLK_MAIN_PLL_C2: + case ALT_CLK_DBG_BASE: + { + uint32_t prediv = (ALT_CLKMGR_ALTERA_DBGATCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_DBGATCLK_ADDR)) + 1); - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if ( (div <= ((ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET_MSK + 1) * prediv)) + && alt_clkmgr_is_val_modulo_n(div, prediv) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C2, div) == ALT_E_TRUE) ) + { + wrval = (div / prediv) - 1; + // HW managed clock, change by writing to the external counter, no need to gate clock + // or match phase or wait for transistion time. No other field in the register to mask off either. + alt_write_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR, wrval); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); - } ret = ALT_E_SUCCESS; } - else { ret = ALT_E_ARG_RANGE; } - break; - - - /* ------------ Peripheral PLL outputs ------------ */ - case ALT_CLK_PERIPHERAL_PLL_C0: - case ALT_CLK_EMAC0: - if ((div <= (ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C0, div) == ALT_E_TRUE)) + else { - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - restore_0 = temp & ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK; + ret = ALT_E_ARG_RANGE; + } + } + break; - if (restore_0) + case ALT_CLK_MAIN_PLL_C3: + // The rest of the PLL outputs do not have external counters, but + // their internal counters are programmable rather than fixed + if ( (div <= (ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C3, div) == ALT_E_TRUE) ) + { + // if the main_qspi_clk input is selected for the qspi_clk + if (ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)) == + ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) + { + restore_0 = (temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)) & ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK; + if (restore_0) // AND if the QSPI clock is currently enabled { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_EMAC0CLK_CLR_MSK); + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK); + // gate off the QSPI clock } - // now write the new divisor ratio wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_PERPLL_VCO_ADDR, - ALT_CLKMGR_PERPLL_STAT_ADDR, - ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C0, - ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + // the rest are software-managed clocks and require a reset sequence to write to + alt_clk_pllcounter_write(ALT_CLKMGR_MAINPLL_VCO_ADDR, + ALT_CLKMGR_MAINPLL_STAT_ADDR, + ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C3, + ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); if (restore_0) { alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + // if the QSPI clock was gated on (enabled) before, return it to that state } ret = ALT_E_SUCCESS; } - else { ret = ALT_E_ARG_RANGE; } - break; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_PERIPHERAL_PLL_C1: - case ALT_CLK_EMAC1: - if ((div <= (ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C1, div) == ALT_E_TRUE)) - { - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - restore_0 = temp & ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK; + case ALT_CLK_MAIN_PLL_C4: + case ALT_CLK_MAIN_NAND_SDMMC: + if ( (div <= (ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C4, div) == ALT_E_TRUE) ) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); + temp1 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_EMAC1CLK_CLR_MSK); - } - // now write the new divisor ratio - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_PERPLL_VCO_ADDR, - ALT_CLKMGR_PERPLL_STAT_ADDR, - ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C1, - ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - } - ret = ALT_E_SUCCESS; + // do we need to gate off the SDMMC clock ? + if (ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(temp) == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK) + { + if (temp1 & ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK) { restore_0 = true; } } - else { ret = ALT_E_ARG_RANGE; } - break; - case ALT_CLK_PERIPHERAL_PLL_C2: - if ((div <= (ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C2, div) == ALT_E_TRUE)) + // do we need to gate off the NAND clock and/or the NANDX clock? + if (ALT_CLKMGR_PERPLL_SRC_NAND_GET(temp) == ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK) { - temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) - { - // if qspi source is set to Peripheral PLL C2 - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - // and if qspi_clk is enabled - restore_0 = temp & ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK; - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK); - // gate it off - } - } - - // now write the new divisor ratio - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_PERPLL_VCO_ADDR, - ALT_CLKMGR_PERPLL_STAT_ADDR, - ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C2, - ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + if (temp1 & ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK) { restore_1 = true; } + if (temp1 & ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK) { restore_2 = true; } + } - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - // if the clock was gated on (enabled) before, return it to that state - } - ret = ALT_E_SUCCESS; + temp = temp1; + if (restore_1 && restore_2) + { + temp &= ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK; + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); + // gate nand_clk off at least 8 MPU clock cycles before before nand_x_clk } - else { ret = ALT_E_ARG_RANGE; } - break; - case ALT_CLK_PERIPHERAL_PLL_C3: - if ((div <= (ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C3, div) == ALT_E_TRUE)) + if (restore_0 || restore_1) { - // first, are the clock MUX input selections currently set to use the clock we want to change? - temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); - restore_0 = (ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(temp) == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK); - restore_1 = restore_2 = (ALT_CLKMGR_PERPLL_SRC_NAND_GET(temp) == ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK); - - // now AND those with the current state of the three gate enables - // to get the clocks which must be gated off and then back on - temp1 = temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - restore_0 = restore_0 && (temp & ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK); - restore_1 = restore_1 && (temp & ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); - restore_2 = restore_2 && (temp & ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); - - // gate off the clocks that depend on the clock divider that we want to change - if (restore_2) { temp &= ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK; } if (restore_0) { temp &= ALT_CLKMGR_PERPLL_EN_SDMMCCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK; } alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + // gate off sdmmc_clk and/or nand_x_clk + } - // the NAND clock must be gated off before the NANDX clock, - if (restore_1) - { - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); - temp &= ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK; - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - } - - // now write the new divisor ratio - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_PERPLL_VCO_ADDR, - ALT_CLKMGR_PERPLL_STAT_ADDR, - ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C3, - ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_MAINPLL_VCO_ADDR, + ALT_CLKMGR_MAINPLL_STAT_ADDR, + ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C4, + ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - // NAND clock and NAND_X clock cannot be written together, must be a set sequence with a delay + if (restore_0 || restore_1) + { alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1 & ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK); - if (restore_2) + // if the NANDX and/or SDMMC clock was gated on (enabled) before, return it to that state + if (restore_1 && restore_2) { - // the NANDX clock must be gated on before the NAND clock. - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK ); + // wait at least 8 clock cycles to turn the nand_clk on + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1); } - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_ARG_RANGE; } - break; + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_PERIPHERAL_PLL_C4: - if ((div <= (ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C4, div) == ALT_E_TRUE)) + case ALT_CLK_MAIN_PLL_C5: + case ALT_CLK_CFG: + case ALT_CLK_H2F_USER0: + if ( (div <= (ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C5, div) == ALT_E_TRUE) ) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + restore_0 = ((temp & ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK) || + (temp & ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK)); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & (ALT_CLKMGR_MAINPLL_EN_CFGCLK_CLR_MSK & + ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_CLR_MSK)); // clear both + } + + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_MAINPLL_VCO_ADDR, + ALT_CLKMGR_MAINPLL_STAT_ADDR, + ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C5, + ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + + if (restore_0) { - // look at the L4 set of clock gates first - temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); - restore_0 = (ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(temp1) == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL); - restore_1 = (ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(temp1) == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL); - temp1 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - restore_0 = restore_0 && (temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK); - restore_1 = restore_1 && (temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK); - - // if the l4_sp and l4_mp clocks are not set to use the periph_base_clk - // from the Peripheral PLL C4 clock divider output, or if they are - // not currently gated on, don't change their gates - temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } - if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - // now look at the C4 direct set of clock gates - // first, create a mask of the C4 direct set of clock gate enables - temp = (ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK - | ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK - | ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK - | ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK - | ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK); + ///// - // gate off all the C4 Direct set of clocks - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1 & ~temp); + // Peripheral PLL outputs + case ALT_CLK_PERIPHERAL_PLL_C0: + case ALT_CLK_EMAC0: + if ( (div <= (ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C0, div) == ALT_E_TRUE) ) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + restore_0 = temp & ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK; - // change the clock divider ratio - the reason we're here - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_PERPLL_VCO_ADDR, - ALT_CLKMGR_PERPLL_STAT_ADDR, - ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C4, - ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); - - // gate the affected clocks that were on before back on - both sets of gates - temp = (restore_0) ? ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK : 0; - if (restore_1) { temp |= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK; } - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1); - ret = ALT_E_SUCCESS; + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_EMAC0CLK_CLR_MSK); } - else { ret = ALT_E_ARG_RANGE; } - break; - case ALT_CLK_PERIPHERAL_PLL_C5: - case ALT_CLK_H2F_USER1: - if ((div <= (ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C5, div) == ALT_E_TRUE)) + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C0, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_PERIPHERAL_PLL_C1: + case ALT_CLK_EMAC1: + if ( (div <= (ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C1, div) == ALT_E_TRUE) ) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + restore_0 = temp & ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK; + + if (restore_0) { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_EMAC1CLK_CLR_MSK); + } + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C1, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_PERIPHERAL_PLL_C2: + if ( (div <= (ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C2, div) == ALT_E_TRUE) ) + { + temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) + { + // if qspi source is set to Peripheral PLL C2 temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - restore_0 = temp & ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK; + // and if qspi_clk is enabled + restore_0 = temp & ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK; if (restore_0) { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_CLR_MSK); + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK); + // gate it off } + } - // now write the new divisor ratio - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_PERPLL_VCO_ADDR, - ALT_CLKMGR_PERPLL_STAT_ADDR, - ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C5, - ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); - if (restore_0) { alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); } - ret = ALT_E_SUCCESS; + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C2, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + // if the clock was gated on (enabled) before, return it to that state } - else { ret = ALT_E_ARG_RANGE; } - break; + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + case ALT_CLK_PERIPHERAL_PLL_C3: + if ( (div <= (ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C3, div) == ALT_E_TRUE) ) + { + // first, are the clock MUX input selections currently set to use the clock we want to change? + temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); + restore_0 = (ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(temp) == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK); + restore_1 = restore_2 = (ALT_CLKMGR_PERPLL_SRC_NAND_GET(temp) == ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK); + + // now AND those with the current state of the three gate enables + // to get the clocks which must be gated off and then back on + temp1 = temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + restore_0 = restore_0 && (temp & ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK); + restore_1 = restore_1 && (temp & ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); + restore_2 = restore_2 && (temp & ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); + + // gate off the clocks that depend on the clock divider that we want to change + if (restore_2) { temp &= ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK; } + if (restore_0) { temp &= ALT_CLKMGR_PERPLL_EN_SDMMCCLK_CLR_MSK; } + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + + // the NAND clock must be gated off before the NANDX clock, + if (restore_1) + { + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); + temp &= ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK; + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } - /* ------------ SDRAM PLL outputs ------------ */ - case ALT_CLK_SDRAM_PLL_C0: - case ALT_CLK_DDR_DQS: - if ((div <= (ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C0, div) == ALT_E_TRUE)) - { - wrval = div - 1; - temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); - if (temp & ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_CLR_MSK); - restore_0 = true; - } - - alt_clk_pllcounter_write( ALT_CLKMGR_SDRPLL_VCO_ADDR, - ALT_CLKMGR_SDRPLL_STAT_ADDR, - ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C0, - ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set - } - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ARG_RANGE; } - break; + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C3, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); - case ALT_CLK_SDRAM_PLL_C1: - case ALT_CLK_DDR_2X_DQS: - if ((div <= (ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C1, div) == ALT_E_TRUE)) + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); + + // NAND clock and NAND_X clock cannot be written together, must be a set sequence with a delay + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1 & ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK); + if (restore_2) { - wrval = div - 1; - temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); - if (temp & ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_CLR_MSK); - restore_0 = true; - } + // the NANDX clock must be gated on before the NAND clock. + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK ); + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - alt_clk_pllcounter_write( ALT_CLKMGR_SDRPLL_VCO_ADDR, - ALT_CLKMGR_SDRPLL_STAT_ADDR, - ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C1, - ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set - } - ret = ALT_E_SUCCESS; + case ALT_CLK_PERIPHERAL_PLL_C4: + if ( (div <= (ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C4, div) == ALT_E_TRUE) ) + { + // look at the L4 set of clock gates first + temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); + restore_0 = (ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(temp1) == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL); + restore_1 = (ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(temp1) == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL); + temp1 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + restore_0 = restore_0 && (temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK); + restore_1 = restore_1 && (temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK); + + // if the l4_sp and l4_mp clocks are not set to use the periph_base_clk + // from the Peripheral PLL C4 clock divider output, or if they are + // not currently gated on, don't change their gates + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + + // now look at the C4 direct set of clock gates + // first, create a mask of the C4 direct set of clock gate enables + temp = ( ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK + | ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK + | ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK + | ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK + | ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK ); + + // gate off all the C4 Direct set of clocks + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1 & ~temp); + + // change the clock divider ratio - the reason we're here + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C4, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); + + // gate the affected clocks that were on before back on - both sets of gates + temp = (restore_0) ? ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK : 0; + if (restore_1) { temp |= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK; } + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1); + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_PERIPHERAL_PLL_C5: + case ALT_CLK_H2F_USER1: + if ( (div <= (ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C5, div) == ALT_E_TRUE) ) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + restore_0 = temp & ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK; + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_CLR_MSK); } - else { ret = ALT_E_ARG_RANGE; } - break; - case ALT_CLK_SDRAM_PLL_C2: - case ALT_CLK_DDR_DQ: - if ((div <= (ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C2, div) == ALT_E_TRUE)) + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C5, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); + if (restore_0) { alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + ///// + + // SDRAM PLL outputs + case ALT_CLK_SDRAM_PLL_C0: + case ALT_CLK_DDR_DQS: + if ( (div <= (ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C0, div) == ALT_E_TRUE) ) + { + wrval = div - 1; + temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); + if (temp & ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK) { - wrval = div - 1; - temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); - if (temp & ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_CLR_MSK); - restore_0 = true; - } + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_CLR_MSK); + restore_0 = true; + } - alt_clk_pllcounter_write( ALT_CLKMGR_SDRPLL_VCO_ADDR, - ALT_CLKMGR_SDRPLL_STAT_ADDR, - ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C2, - ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set - } - ret = ALT_E_SUCCESS; + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, + ALT_CLKMGR_SDRPLL_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C0, + ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set } - else { ret = ALT_E_ARG_RANGE; } - break; + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_SDRAM_PLL_C5: - case ALT_CLK_H2F_USER2: - if ((div <= (ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C5, div) == ALT_E_TRUE)) + case ALT_CLK_SDRAM_PLL_C1: + case ALT_CLK_DDR_2X_DQS: + if ( (div <= (ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C1, div) == ALT_E_TRUE) ) + { + wrval = div - 1; + temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); + if (temp & ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK) { - wrval = div - 1; - temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); - if (temp & ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_CLR_MSK); - restore_0 = true; - } + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_CLR_MSK); + restore_0 = true; + } + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, + ALT_CLKMGR_SDRPLL_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C1, + ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - alt_clk_pllcounter_write( ALT_CLKMGR_SDRPLL_VCO_ADDR, - ALT_CLKMGR_SDRPLL_STAT_ADDR, - ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C5, - ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set - } - ret = ALT_E_SUCCESS; + case ALT_CLK_SDRAM_PLL_C2: + case ALT_CLK_DDR_DQ: + if ( (div <= (ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C2, div) == ALT_E_TRUE) ) + { + wrval = div - 1; + temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); + if (temp & ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, + ALT_CLKMGR_SDRPLL_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C2, + ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - /* ------------ Other clock dividers ------------ */ - case ALT_CLK_L3_MP: - if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2; } + case ALT_CLK_SDRAM_PLL_C5: + case ALT_CLK_H2F_USER2: + if ( (div <= (ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C5, div) == ALT_E_TRUE) ) + { + wrval = div - 1; + temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); + if (temp & ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_CLR_MSK); + restore_0 = true; + } - if (wrval != UINT32_MAX) + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, + ALT_CLKMGR_SDRPLL_STAT_ADDR, + ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C5, + ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB); + if (restore_0) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - if (temp & ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_L3MPCLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET_MSK, - wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); // which has the enable bit set - } - ret = ALT_E_SUCCESS; + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set } - else { ret = ALT_E_ARG_RANGE; } - break; + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + ///// - case ALT_CLK_L3_SP: - // note that the L3MP divider is upstream from the L3SP divider - // and any changes to the former will affect the output of both - if ( div <= (ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2 + 1)) - { - if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2; } - - alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET_MSK, - wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_LSB); - // no clock gate to close and reopen - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ARG_RANGE; } - break; - - case ALT_CLK_L4_MP: - if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4; } - else if (div == 8) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8; } - else if (div == 16) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16; } - - if (wrval != UINT32_MAX) + // Other clock dividers + case ALT_CLK_L3_MP: + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2; } + + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (temp & ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - if (temp & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET_MSK, - wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); // which has the enable bit set - } - ret = ALT_E_SUCCESS; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_L3MPCLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); // which has the enable bit set + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_L4_SP: - if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4; } - else if (div == 8) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8; } - else if (div == 16) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16; } + case ALT_CLK_L3_SP: + // note that the L3MP divider is upstream from the L3SP divider + // and any changes to the former will affect the output of both + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2; } - if (wrval != UINT32_MAX) + if (wrval != UINT32_MAX) + { + alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_LSB); + // no clock gate to close and reopen + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_L4_MP: + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16; } + + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (temp & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - if (temp & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET_MSK, - wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); - } - ret = ALT_E_SUCCESS; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); // which has the enable bit set + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_DBG_AT: - if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4; } + case ALT_CLK_L4_SP: + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16; } - if (wrval != UINT32_MAX) + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (temp & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - if (temp & ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_DBGATCLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET_MSK, - wrval << ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); - } - ret = ALT_E_SUCCESS; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_DBG: - if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4; } - else + case ALT_CLK_DBG_AT: + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4; } + + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (temp & ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK) { - ret = ALT_E_ARG_RANGE; - break; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_DBGATCLK_CLR_MSK); + restore_0 = true; } + alt_replbits_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_DBG: + if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4; } + if (wrval != UINT32_MAX) + { temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); if (temp & ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK) { - // if clock is currently on, gate it off + // if clock is currently on, gate it off alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_DBGCLK_CLR_MSK); restore_0 = true; } alt_replbits_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET_MSK, - wrval << (ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_LSB - 1)); - // account for the fact that the divisor ratios are 2x the value + wrval << (ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_LSB - 1)); + // account for the fact that the divisor ratios are 2x the value alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); if (restore_0) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); } ret = ALT_E_SUCCESS; - break; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_DBG_TRACE: - if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4; } - else if (div == 8) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8; } - else if (div == 16) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16; } + case ALT_CLK_DBG_TRACE: + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16; } - if (wrval != UINT32_MAX) + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (temp & ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - if (temp & ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR, ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET_MSK, - wrval << ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); - } - ret = ALT_E_SUCCESS; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_replbits_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR, ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_USB_MP: - if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4; } - else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8; } - else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16; } + case ALT_CLK_USB_MP: + if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16; } - if (wrval != UINT32_MAX) + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + if (temp & ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - if (temp & ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_USBCLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_USBCLK_SET_MSK, - wrval << ALT_CLKMGR_PERPLL_DIV_USBCLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - } - ret = ALT_E_SUCCESS; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_USBCLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_USBCLK_SET_MSK, + wrval << ALT_CLKMGR_PERPLL_DIV_USBCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_SPI_M: - if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4; } - else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8; } - else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16; } + case ALT_CLK_SPI_M: + if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16; } - if (wrval != UINT32_MAX) + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + if (temp & ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - if (temp & ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_SPIMCLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET_MSK, - wrval << ALT_CLKMGR_PERPLL_DIV_SPIMCLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - } - ret = ALT_E_SUCCESS; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_SPIMCLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET_MSK, + wrval << ALT_CLKMGR_PERPLL_DIV_SPIMCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_CAN0: - if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4; } - else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8; } - else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16; } + case ALT_CLK_CAN0: + if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16; } - if (wrval != UINT32_MAX) + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + if (temp & ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - if (temp & ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_CAN0CLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET_MSK, - wrval << ALT_CLKMGR_PERPLL_DIV_CAN0CLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - } - ret = ALT_E_SUCCESS; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_CAN0CLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET_MSK, + wrval << ALT_CLKMGR_PERPLL_DIV_CAN0CLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_CAN1: - if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4; } - else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8; } - else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16; } + case ALT_CLK_CAN1: + if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16; } - if (wrval != UINT32_MAX) + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + if (temp & ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - if (temp & ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK) + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_CAN1CLK_CLR_MSK); + restore_0 = true; + } + alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET_MSK, + wrval << ALT_CLKMGR_PERPLL_DIV_CAN1CLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_GPIO_DB: // GPIO debounce clock + if (div <= ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + if (temp & ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_GPIOCLK_CLR_MSK); + restore_0 = true; + } + wrval = div - 1; + alt_replbits_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR, ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK, + wrval << ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_GPIODIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_MAIN_QSPI: + temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + // get the QSPI clock source + restore_0 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR) & ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK; + // and the current enable state + wrval = div - 1; + + if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) + { // if the main_qspi_clk (Main PLL C3 Ouput) input is selected + if (div <= ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK) + { + if (restore_0) { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_CAN1CLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET_MSK, - wrval << ALT_CLKMGR_PERPLL_DIV_CAN1CLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + } // gate off the QSPI clock + + alt_clk_pllcounter_write(ALT_CLKMGR_MAINPLL_VCO_ADDR, + ALT_CLKMGR_MAINPLL_STAT_ADDR, + ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C3, + ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); if (restore_0) { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + // if the QSPI clock was gated on (enabled) before, return it to that state } ret = ALT_E_SUCCESS; } - else { ret = ALT_E_ARG_RANGE; } - break; - - case ALT_CLK_GPIO_DB: // GPIO debounce clock - if ( div <= ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK) + else { - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - if (temp & ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK) + ret = ALT_E_ARG_RANGE; + } + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) + { + if (div <= ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK) + { + if (restore_0) { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_GPIOCLK_CLR_MSK); - restore_0 = true; - } - wrval = div - 1; - alt_replbits_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR, ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK, - wrval << ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_GPIODIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + } // gate off the QSPI clock + + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C2, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); if (restore_0) { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + // if the QSPI clock was gated on (enabled) before, return it to that state } ret = ALT_E_SUCCESS; } - else { ret = ALT_E_ARG_RANGE; } - break; + else + { + ret = ALT_E_ARG_RANGE; + } + } + break; - case ALT_CLK_MAIN_QSPI: - temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - // get the QSPI clock source - restore_0 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR) & ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK; - // and the current enable state - wrval = div - 1; - - if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) - { // if the main_qspi_clk (Main PLL C3 Ouput) input is selected - if (div <= ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK) - { - if (restore_0) - { - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); - } // gate off the QSPI clock - - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C3, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); - // if the QSPI clock was gated on (enabled) before, return it to that state - } - } - else { ret = ALT_E_ARG_RANGE; } - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) - { - if (div <= ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK) - { - if (restore_0) - { - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); - } // gate off the QSPI clock - - alt_clk_pllcounter_write( ALT_CLKMGR_PERPLL_VCO_ADDR, - ALT_CLKMGR_PERPLL_STAT_ADDR, - ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C2, - ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); - // if the QSPI clock was gated on (enabled) before, return it to that state - } - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ARG_RANGE; } - } - break; + ///// - default: - break; + default: + ret = ALT_E_BAD_ARG; + break; + } - } // end of switch-case construct return ret; -} // end of alt_clk_divider_set() - Hallelujah ! - - -/****************************************************************************************/ -/* alt_clk_freq_get() returns the output frequency of the specified clock. */ -/****************************************************************************************/ +} +// +// alt_clk_freq_get() returns the output frequency of the specified clock. +// ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk, alt_freq_t* freq) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - uint32_t temp; - uint64_t numer = 0; - uint64_t denom = 1; + ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + uint32_t temp = 0; + uint64_t numer = 0; + uint64_t denom = 1; + if (freq == NULL) + { + return ret; + } - if (freq != NULL) + switch (clk) { - switch (clk) + // External Inputs + case ALT_CLK_IN_PIN_OSC1: + case ALT_CLK_OSC1: + numer = alt_ext_clk_paramblok.clkosc1.freqcur; + // denom = 1 by default + ret = ALT_E_SUCCESS; + break; + + case ALT_CLK_IN_PIN_OSC2: + numer = alt_ext_clk_paramblok.clkosc2.freqcur; + // denom = 1 by default + ret = ALT_E_SUCCESS; + break; + + case ALT_CLK_F2H_PERIPH_REF: + numer = alt_ext_clk_paramblok.periph.freqcur; + // denom = 1 by default + ret = ALT_E_SUCCESS; + break; + + case ALT_CLK_F2H_SDRAM_REF: + numer = alt_ext_clk_paramblok.sdram.freqcur; + // denom = 1 by default + ret = ALT_E_SUCCESS; + break; + + ///// + + // PLLs + case ALT_CLK_MAIN_PLL: + if (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) { - /* External Inputs */ - case ALT_CLK_IN_PIN_OSC1: - case ALT_CLK_OSC1: - numer = alt_ext_clk_paramblok.clkosc1.freqcur; - // denom = 1 by default - ret = ALT_E_SUCCESS; - break; + temp = alt_ext_clk_paramblok.clkosc1.freqcur; + ret = ALT_E_SUCCESS; + } + else + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + } + numer = (uint64_t) temp; + // denom = 1 by default + break; - case ALT_CLK_IN_PIN_OSC2: - numer = alt_ext_clk_paramblok.clkosc2.freqcur; - // denom = 1 by default + case ALT_CLK_PERIPHERAL_PLL: + if (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) + { + temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) + { + temp = alt_ext_clk_paramblok.clkosc1.freqcur; ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_F2H_PERIPH_REF: - numer = alt_ext_clk_paramblok.periph.freqcur; - // denom = 1 by default + } + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) + { + temp = alt_ext_clk_paramblok.clkosc2.freqcur; ret = ALT_E_SUCCESS; - break; + } + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) + { + temp = alt_ext_clk_paramblok.periph.freqcur; + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ERROR; + } + } + else + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + } + numer = (uint64_t) temp; + // denom = 1 by default + break; - case ALT_CLK_F2H_SDRAM_REF: - numer = alt_ext_clk_paramblok.sdram.freqcur; - // denom = 1 by default + case ALT_CLK_SDRAM_PLL: + if (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) + { + temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); + if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) + { + temp = alt_ext_clk_paramblok.clkosc1.freqcur; + ret = ALT_E_SUCCESS; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) + { + temp = alt_ext_clk_paramblok.clkosc2.freqcur; + ret = ALT_E_SUCCESS; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) + { + temp = alt_ext_clk_paramblok.sdram.freqcur; ret = ALT_E_SUCCESS; - break; + } + else + { + ret = ALT_E_ERROR; + } + } + else + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); + } + numer = (uint64_t) temp; + // denom = 1 by default + break; - /* PLLs */ - case ALT_CLK_MAIN_PLL: - if (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) - { - temp = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = ALT_E_SUCCESS; - } - else - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - } - numer = (uint64_t) temp; - // denom = 1 by default - break; + ///// - case ALT_CLK_PERIPHERAL_PLL: - if (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) - { - temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) - { - temp = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) - { - temp = alt_ext_clk_paramblok.clkosc2.freqcur; - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) - { - temp = alt_ext_clk_paramblok.periph.freqcur; - ret = ALT_E_SUCCESS; - } - } - else - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - } - numer = (uint64_t) temp; - // denom = 1 by default - break; + // Main Clock Group + case ALT_CLK_MAIN_PLL_C0: + case ALT_CLK_MAIN_PLL_C1: + case ALT_CLK_MAIN_PLL_C2: + case ALT_CLK_MAIN_PLL_C3: + case ALT_CLK_MAIN_PLL_C4: + case ALT_CLK_MAIN_PLL_C5: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(clk, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_SDRAM_PLL: - if (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) - { - temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); - if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) - { - temp = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) - { - temp = alt_ext_clk_paramblok.clkosc2.freqcur; - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) - { - temp = alt_ext_clk_paramblok.sdram.freqcur; - ret = ALT_E_SUCCESS; - } - } - else - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); - } - numer = (uint64_t) temp; - // denom = 1 by default - break; - - /* Main Clock Group */ - case ALT_CLK_MAIN_PLL_C0: - case ALT_CLK_MAIN_PLL_C1: - case ALT_CLK_MAIN_PLL_C2: - case ALT_CLK_MAIN_PLL_C3: - case ALT_CLK_MAIN_PLL_C4: - case ALT_CLK_MAIN_PLL_C5: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(clk, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_MPU: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C0, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_MPU: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C0, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_MPU_PERIPH: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C0, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MPU_PERIPH, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_MPU_PERIPH: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C0, &temp); - if (ret == ALT_E_SUCCESS ) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MPU_PERIPH, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_MPU_L2_RAM: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C0, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MPU_L2_RAM, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_MPU_L2_RAM: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C0, &temp); - if (ret == ALT_E_SUCCESS ) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MPU_L2_RAM, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_L4_MAIN: + case ALT_CLK_L3_MAIN: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_L4_MAIN: - case ALT_CLK_L3_MAIN: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_L3_MP: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_L3_MP, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_L3_MP: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); - if (ret == ALT_E_SUCCESS ) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_L3_MP, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_L3_SP: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_L3_MP, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = denom * (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_L3_SP, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_L3_SP: + case ALT_CLK_L4_MP: + ret = alt_clk_divider_get(ALT_CLK_L4_MP, &temp); + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + temp = ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR)); + if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL) + { ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS ) + if (ret == ALT_E_SUCCESS) { numer = (uint64_t) temp; ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); - if (ret == ALT_E_SUCCESS ) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_L3_MP, &temp); - if (ret == ALT_E_SUCCESS ) - { - denom = denom * (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_L3_SP, &temp); - denom = denom * (uint64_t) temp; - } - } + denom = denom * (uint64_t) temp; // no real harm if temp is garbage data } - break; - - case ALT_CLK_L4_MP: - ret = alt_clk_divider_get(ALT_CLK_L4_MP, &temp); - if (ret == ALT_E_SUCCESS ) - { - denom = (uint64_t) temp; - temp = ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR)); - if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); - denom = denom * (uint64_t) temp; // no real harm if temp is garbage data - } - } - else if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); - denom = denom * (uint64_t) temp; - } - } - } - break; - - case ALT_CLK_L4_SP: - ret = alt_clk_divider_get(ALT_CLK_L4_SP, &temp); - if (ret == ALT_E_SUCCESS ) - { - denom = (uint64_t) temp; - temp = ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR)); - if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); - denom = denom * (uint64_t) temp; - } - } - else if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL) // periph_base_clk - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); - denom = denom * (uint64_t) temp; - } - } - } - break; - - case ALT_CLK_DBG_BASE: - case ALT_CLK_DBG_TIMER: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + } + else if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); if (ret == ALT_E_SUCCESS) { numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); - denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + denom = denom * (uint64_t) temp; } - break; + } + } + break; - case ALT_CLK_DBG_AT: + case ALT_CLK_L4_SP: + ret = alt_clk_divider_get(ALT_CLK_L4_SP, &temp); + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + temp = ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR)); + if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL) + { ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); if (ret == ALT_E_SUCCESS) { numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_DBG_AT, &temp); - denom = denom * (uint64_t) temp; - } + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); + denom = denom * (uint64_t) temp; } - break; - - case ALT_CLK_DBG: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + } + else if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL) // periph_base_clk + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); if (ret == ALT_E_SUCCESS) { numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_DBG_AT, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = denom * (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_DBG, &temp); - denom = denom * (uint64_t) temp; - } - } + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + denom = denom * (uint64_t) temp; } - break; + } + } + break; - case ALT_CLK_DBG_TRACE: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_DBG_TRACE, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_DBG_BASE: + case ALT_CLK_DBG_TIMER: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_MAIN_QSPI: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C3, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_DBG_AT: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_DBG_AT, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_MAIN_NAND_SDMMC: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C4, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_DBG: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_DBG_AT, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = denom * (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_DBG, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_CFG: - case ALT_CLK_H2F_USER0: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C5, &temp); - denom = (uint64_t) temp; - } - break; - - /* Peripheral Clock Group */ - case ALT_CLK_PERIPHERAL_PLL_C0: - case ALT_CLK_PERIPHERAL_PLL_C1: - case ALT_CLK_PERIPHERAL_PLL_C2: - case ALT_CLK_PERIPHERAL_PLL_C3: - case ALT_CLK_PERIPHERAL_PLL_C4: - case ALT_CLK_PERIPHERAL_PLL_C5: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(clk, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_DBG_TRACE: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_DBG_TRACE, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_EMAC0: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C0, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_MAIN_QSPI: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C3, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_EMAC1: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C1, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_MAIN_NAND_SDMMC: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C4, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_USB_MP: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_USB_MP, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_CFG: + case ALT_CLK_H2F_USER0: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C5, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_SPI_M: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_SPI_M, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + ///// - case ALT_CLK_CAN0: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_CAN0, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + // Peripheral Clock Group + case ALT_CLK_PERIPHERAL_PLL_C0: + case ALT_CLK_PERIPHERAL_PLL_C1: + case ALT_CLK_PERIPHERAL_PLL_C2: + case ALT_CLK_PERIPHERAL_PLL_C3: + case ALT_CLK_PERIPHERAL_PLL_C4: + case ALT_CLK_PERIPHERAL_PLL_C5: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(clk, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_CAN1: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_CAN1, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_EMAC0: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C0, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_GPIO_DB: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_GPIO_DB, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_EMAC1: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C1, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_H2F_USER1: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C5, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_USB_MP: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_USB_MP, &temp); + denom = denom * (uint64_t) temp; + } + } + break; - /* Clocks That Can Switch Between Different Clock Groups */ - case ALT_CLK_SDMMC: - temp = ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK) - { - numer = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; - // denom = 1 by default - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C4, &temp); - denom = (uint64_t) temp; - } - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C3, &temp); - denom = (uint64_t) temp; - } - } - break; + case ALT_CLK_SPI_M: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_SPI_M, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_NAND: - denom = 4; // the absence of a break statement here is not a mistake - case ALT_CLK_NAND_X: - temp = ALT_CLKMGR_PERPLL_SRC_NAND_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK) - { - numer = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; - // denom = 1 or 4 by default; - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C4, &temp); - denom = denom * (uint64_t) temp; - } - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C3, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_CAN0: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_CAN0, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_QSPI: - temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK) - { - numer = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; - // denom = 1 by default; - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C3, &temp); - denom = (uint64_t) temp; - } - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C2, &temp); - denom = (uint64_t) temp; - } - } - break; + case ALT_CLK_CAN1: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_CAN1, &temp); + denom = denom * (uint64_t) temp; + } + break; - /* SDRAM Clock Group */ - case ALT_CLK_SDRAM_PLL_C0: - case ALT_CLK_DDR_DQS: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C0, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_GPIO_DB: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_GPIO_DB, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_SDRAM_PLL_C1: - case ALT_CLK_DDR_2X_DQS: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C1, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_H2F_USER1: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C5, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_SDRAM_PLL_C2: - case ALT_CLK_DDR_DQ: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C2, &temp); - denom = (uint64_t) temp; - } - break; + /* Clocks That Can Switch Between Different Clock Groups */ + case ALT_CLK_SDMMC: + temp = ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK) + { + numer = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; + // denom = 1 by default + ret = ALT_E_SUCCESS; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C4, &temp); + denom = (uint64_t) temp; + } + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C3, &temp); + denom = (uint64_t) temp; + } + } + else + { + ret = ALT_E_ERROR; + } + break; - case ALT_CLK_SDRAM_PLL_C5: - case ALT_CLK_H2F_USER2: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C5, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_NAND: + denom = 4; + // the absence of a break statement here is not a mistake + case ALT_CLK_NAND_X: + temp = ALT_CLKMGR_PERPLL_SRC_NAND_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK) + { + numer = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; + // denom = 1 or 4 by default; + ret = ALT_E_SUCCESS; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C4, &temp); + denom = denom * (uint64_t) temp; + } + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C3, &temp); + denom = denom * (uint64_t) temp; + } + } + else + { + ret = ALT_E_ERROR; + } + break; - default: - break; + case ALT_CLK_QSPI: + temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK) + { + numer = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; + // denom = 1 by default; + ret = ALT_E_SUCCESS; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C3, &temp); + denom = (uint64_t) temp; + } + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C2, &temp); + denom = (uint64_t) temp; + } + } + else + { + ret = ALT_E_ERROR; + } + break; - } // end of switch-case construct + ///// + // SDRAM Clock Group + case ALT_CLK_SDRAM_PLL_C0: + case ALT_CLK_DDR_DQS: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); if (ret == ALT_E_SUCCESS) { - // will not get here if none of above cases match - if (denom > 0) + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C0, &temp); + denom = (uint64_t) temp; + } + break; + + case ALT_CLK_SDRAM_PLL_C1: + case ALT_CLK_DDR_2X_DQS: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C1, &temp); + denom = (uint64_t) temp; + } + break; + + case ALT_CLK_SDRAM_PLL_C2: + case ALT_CLK_DDR_DQ: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C2, &temp); + denom = (uint64_t) temp; + } + break; + + case ALT_CLK_SDRAM_PLL_C5: + case ALT_CLK_H2F_USER2: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C5, &temp); + denom = (uint64_t) temp; + } + break; + + default: + ret = ALT_E_BAD_ARG; + break; + + } // end of switch-case construct + + if (ret == ALT_E_SUCCESS) + { + // will not get here if none of above cases match + if (denom > 0) + { + numer /= denom; + if (numer <= UINT32_MAX) { - numer /= denom; - if (numer <= UINT32_MAX) - { - *freq = (uint32_t) numer; - } - else { ret = ALT_E_ERROR; } + *freq = (uint32_t) numer; + } + else + { + ret = ALT_E_ERROR; } - else { ret = ALT_E_ERROR; } + } + else + { + ret = ALT_E_ERROR; } } + return ret; } - -/****************************************************************************************/ -/* alt_clk_irq_disable() disables one or more of the lock status conditions as */ -/* contributors to the clkmgr_IRQ interrupt signal state. */ -/****************************************************************************************/ - +// +// alt_clk_irq_disable() disables one or more of the lock status conditions as +// contributors to the clkmgr_IRQ interrupt signal state. +// ALT_STATUS_CODE alt_clk_irq_disable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - if (!(lock_stat_mask & ALT_CLK_MGR_PLL_LOCK_BITS)) { alt_clrbits_word(ALT_CLKMGR_INTREN_ADDR, lock_stat_mask); - ret = ALT_E_SUCCESS; + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; } - return ret; } - -/****************************************************************************************/ -/* alt_clk_irq_enable() enables one or more of the lock status conditions as */ -/* contributors to the clkmgr_IRQ interrupt signal state. */ -/****************************************************************************************/ - - +// +// alt_clk_irq_enable() enables one or more of the lock status conditions as +// contributors to the clkmgr_IRQ interrupt signal state. +// ALT_STATUS_CODE alt_clk_irq_enable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - if (!(lock_stat_mask & ALT_CLK_MGR_PLL_LOCK_BITS)) { alt_setbits_word(ALT_CLKMGR_INTREN_ADDR, lock_stat_mask); - ret = ALT_E_SUCCESS; + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; } - return ret; } +///// -/****************************************************************************************/ -/* alt_clk_group_cfg_raw_get() gets the raw configuration state of the designated */ -/* clock group. */ -/****************************************************************************************/ - +// +// alt_clk_group_cfg_raw_get() gets the raw configuration state of the designated +// clock group. +// ALT_STATUS_CODE alt_clk_group_cfg_raw_get(ALT_CLK_GRP_t clk_group, - ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg) + ALT_CLK_GROUP_RAW_CFG_t * clk_group_raw_cfg) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - uint32_t *tmp; + clk_group_raw_cfg->verid = alt_read_word(ALT_SYSMGR_SILICONID1_ADDR); + clk_group_raw_cfg->siliid2 = alt_read_word(ALT_SYSMGR_SILICONID2_ADDR); + clk_group_raw_cfg->clkgrpsel = clk_group; - if (clk_group_raw_cfg != NULL) + if (clk_group == ALT_MAIN_PLL_CLK_GRP) { - alt_write_word(&clk_group_raw_cfg->verid, alt_read_word(ALT_SYSMGR_SILICONID1_ADDR)); - alt_write_word(&clk_group_raw_cfg->siliid2, alt_read_word(ALT_SYSMGR_SILICONID2_ADDR)); - alt_indwrite_word(&clk_group_raw_cfg->clkgrpsel, tmp, clk_group); + // Main PLL VCO register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.vco = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); - if (clk_group == ALT_MAIN_PLL_CLK_GRP) - { - /* Main PLL VCO register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.vco, uint32_t); // compile-time macro that - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.vco, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR)); + // Main PLL Misc register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.misc = alt_read_word(ALT_CLKMGR_MAINPLL_MISC_ADDR); - /* Main PLL Misc register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.misc, uint32_t); // disappears if size is OK - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.misc, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_MISC_ADDR)); + // Main PLL C0-C5 Counter registers + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mpuclk = alt_read_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR); + // doing these as 32-bit reads and writes avoids unnecessary masking operations - /* Main PLL C0-C5 Counter registers */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.mpuclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.mpuclk, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR)); - // doing these as 32-bit reads and writes avoids unnecessary masking operations + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainclk = alt_read_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR); + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.dbgatclk = alt_read_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR); + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainqspiclk = alt_read_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR); + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainnandsdmmcclk = alt_read_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR); + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.cfgs2fuser0clk = alt_read_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.mainclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.mainclk, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR)); + // Main PLL Enable register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.en = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.dbgatclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.dbgatclk, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR)); + // Main PLL Maindiv register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.maindiv = alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.mainqspiclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.mainqspiclk, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR)); + // Main PLL Debugdiv register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.dbgdiv = alt_read_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.mainnandsdmmcclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.mainnandsdmmcclk, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR)); + // Main PLL Tracediv register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.tracediv = alt_read_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.cfgs2fuser0clk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.cfgs2fuser0clk, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR)); + // Main PLL L4 Source register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.l4src = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); - /* Main PLL Enable register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.en, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.en, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR)); + // Main PLL Status register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.stat = alt_read_word(ALT_CLKMGR_MAINPLL_STAT_ADDR); + // clkgrp.mainpllgrp.stat.outresetack is defined in the ALT_CLKMGR_MAINPLL_STAT_s declaration + // as a const but alt_indwrite_word() overrides that restriction. - /* Main PLL Maindiv register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.maindiv, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.maindiv, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); + // padding ... + clk_group_raw_cfg->clkgrp.mainpllgrp.raw._pad_0x38_0x40[0] = 0; + clk_group_raw_cfg->clkgrp.mainpllgrp.raw._pad_0x38_0x40[1] = 0; - /* Main PLL Debugdiv register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.dbgdiv, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.dbgdiv, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR)); + return ALT_E_SUCCESS; + } + else if (clk_group == ALT_PERIPH_PLL_CLK_GRP) + { + // Peripheral PLL VCO register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.vco = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); - /* Main PLL Tracediv register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.tracediv, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.tracediv, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR)); + // Peripheral PLL Misc register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.misc = alt_read_word(ALT_CLKMGR_PERPLL_MISC_ADDR); - /* Main PLL L4 Source register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.l4src, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.l4src, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR)); + // Peripheral PLL C0-C5 Counters + clk_group_raw_cfg->clkgrp.perpllgrp.raw.emac0clk = alt_read_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR); + // doing these as 32-bit reads and writes avoids unnecessary masking operations - /* Main PLL Status register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.stat, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.stat, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_STAT_ADDR)); - // clkgrp.mainpllgrp.stat.outresetack is defined in the ALT_CLKMGR_MAINPLL_STAT_s declaration - // as a const but alt_indwrite_word() overrides that restriction. + clk_group_raw_cfg->clkgrp.perpllgrp.raw.emac1clk = alt_read_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR); + clk_group_raw_cfg->clkgrp.perpllgrp.raw.perqspiclk = alt_read_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR); + clk_group_raw_cfg->clkgrp.perpllgrp.raw.pernandsdmmcclk = alt_read_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR); + clk_group_raw_cfg->clkgrp.perpllgrp.raw.perbaseclk = alt_read_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR); + clk_group_raw_cfg->clkgrp.perpllgrp.raw.s2fuser1clk = alt_read_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR); - /* padding....... */ - clk_group_raw_cfg->clkgrp.mainpllgrp._pad_0x38_0x40[0] = 0; - clk_group_raw_cfg->clkgrp.mainpllgrp._pad_0x38_0x40[1] = 0; - ret = ALT_E_SUCCESS; - } + // Peripheral PLL Enable register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.en = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - else if (clk_group == ALT_PERIPH_PLL_CLK_GRP) - { - /* Peripheral PLL VCO register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.vco, uint32_t); // compile-time macro - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.vco, tmp, alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR)); + // Peripheral PLL Divider register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.div = alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR); - /* Peripheral PLL Misc register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.misc, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.misc, tmp, alt_read_word(ALT_CLKMGR_PERPLL_MISC_ADDR)); + // Peripheral PLL GPIO Divider register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.gpiodiv = alt_read_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR); - /* Peripheral PLL C0-C5 Counters */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.emac0clk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.emac0clk, tmp, alt_read_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR)); - // doing these as 32-bit reads and writes avoids unnecessary masking operations + // Peripheral PLL Source register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.src = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.emac1clk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.emac1clk, tmp, alt_read_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR)); + // Peripheral PLL Status register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.stat = alt_read_word(ALT_CLKMGR_PERPLL_STAT_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.perqspiclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.perqspiclk, tmp, alt_read_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR)); + // padding ... + clk_group_raw_cfg->clkgrp.perpllgrp.raw._pad_0x34_0x40[0] = 0; + clk_group_raw_cfg->clkgrp.perpllgrp.raw._pad_0x34_0x40[1] = 0; + clk_group_raw_cfg->clkgrp.perpllgrp.raw._pad_0x34_0x40[2] = 0; - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.pernandsdmmcclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.pernandsdmmcclk, tmp, alt_read_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR)); + return ALT_E_SUCCESS; + } + else if (clk_group == ALT_SDRAM_PLL_CLK_GRP) + { + // SDRAM PLL VCO register + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.vco = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.perbaseclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.perbaseclk, tmp, alt_read_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR)); + // SDRAM PLL Control register + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ctrl = alt_read_word(ALT_CLKMGR_SDRPLL_CTL_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.s2fuser1clk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.s2fuser1clk, tmp, alt_read_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR)); + // SDRAM PLL C0-C2 & C5 Counters + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddrdqsclk = alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR); + // doing these as 32-bit reads and writes avoids unnecessary masking operations - /* Peripheral PLL Enable register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.en, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.en, tmp, alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)); + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddr2xdqsclk = alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR); + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddrdqclk = alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR); + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.s2fuser2clk = alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR); - /* Peripheral PLL Divider register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.div, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.div, tmp, alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); + // SDRAM PLL Enable register + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.en = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); - /* Peripheral PLL GPIO Divider register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.gpiodiv, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.gpiodiv, tmp, alt_read_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR)); + // SDRAM PLL Status register + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.stat = alt_read_word(ALT_CLKMGR_SDRPLL_STAT_ADDR); - /* Peripheral PLL Source register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.src, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.src, tmp, alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; + } +} - /* Peripheral PLL Status register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.stat, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.stat, tmp, alt_read_word(ALT_CLKMGR_PERPLL_STAT_ADDR)); +// +// alt_clk_group_cfg_raw_set() sets the clock group configuration. +// +ALT_STATUS_CODE alt_clk_group_cfg_raw_set(const ALT_CLK_GROUP_RAW_CFG_t * clk_group_raw_cfg) +{ + // test for matching silicon ID, but not for matching silicon revision number + if (ALT_SYSMGR_SILICONID1_ID_GET(alt_read_word(ALT_SYSMGR_SILICONID1_ADDR)) != + ALT_SYSMGR_SILICONID1_ID_GET(clk_group_raw_cfg->verid)) + { + return ALT_E_BAD_VERSION; + } - /* padding....... */ - clk_group_raw_cfg->clkgrp.perpllgrp._pad_0x34_0x40[0] = 0; - clk_group_raw_cfg->clkgrp.perpllgrp._pad_0x34_0x40[1] = 0; - clk_group_raw_cfg->clkgrp.perpllgrp._pad_0x34_0x40[2] = 0; - ret = ALT_E_SUCCESS; - } + // get the PLL ID + ALT_CLK_GRP_t clk_group = clk_group_raw_cfg->clkgrpsel; + ALT_CLK_t pll; - else if (clk_group == ALT_SDRAM_PLL_CLK_GRP) + if (clk_group == ALT_MAIN_PLL_CLK_GRP) { pll = ALT_CLK_MAIN_PLL; } + else if (clk_group == ALT_PERIPH_PLL_CLK_GRP) { pll = ALT_CLK_PERIPHERAL_PLL; } + else if (clk_group == ALT_SDRAM_PLL_CLK_GRP) { pll = ALT_CLK_SDRAM_PLL; } + else + { + return ALT_E_ERROR; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // if the PLL isn't in bypass mode, put it in bypass mode + bool byp = false; + if (alt_clk_pll_is_bypassed(pll) == ALT_E_FALSE) + { + status = alt_clk_pll_bypass_enable(pll, false); + if (status != ALT_E_SUCCESS) { - /* SDRAM PLL VCO register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.vco, uint32_t); // compile-time macro - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.vco, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); + return status; + } - /* SDRAM PLL Control register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.ctrl, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.ctrl, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_CTL_ADDR)); + byp = true; + } - /* SDRAM PLL C0-C2 & C5 Counters */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.ddrdqsclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.ddrdqsclk, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR)); - // doing these as 32-bit reads and writes avoids unnecessary masking operations + // now write the values in the ALT_CLK_GROUP_RAW_CFG_t structure to the registers + if (clk_group == ALT_MAIN_PLL_CLK_GRP) + { + // Main PLL VCO register + alt_write_word(ALT_CLKMGR_MAINPLL_VCO_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.vco & + ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_CLR_MSK & ALT_CLKMGR_MAINPLL_VCO_OUTRST_CLR_MSK); + // the outreset and outresetall bits were probably clear when the + // state was saved, but make sure they're clear now - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.ddr2xdqsclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.ddr2xdqsclk, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR)); + // Main PLL Misc register + alt_write_word(ALT_CLKMGR_MAINPLL_MISC_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.misc); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.ddrdqclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.ddrdqclk, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR)); + // Main PLL C0-C5 Counter registers + alt_write_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mpuclk); + alt_write_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainclk); + alt_write_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.dbgatclk); + alt_write_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainqspiclk); + alt_write_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainnandsdmmcclk); + alt_write_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.cfgs2fuser0clk); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.s2fuser2clk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.s2fuser2clk, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR)); + // Main PLL Counter Enable register + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.en); - /* SDRAM PLL Enable register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.en, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.en, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR)); + // Main PLL Maindiv register + alt_write_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.maindiv); - /* SDRAM PLL Status register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.stat, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.stat, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_STAT_ADDR)); + // Main PLL Debugdiv register + alt_write_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.dbgdiv); - ret = ALT_E_SUCCESS; - } - } - return ret; -} + // Main PLL Tracediv register + alt_write_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.tracediv); + // Main PLL L4 Source register + alt_write_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.l4src); + } + else if (clk_group == ALT_PERIPH_PLL_CLK_GRP) + { + // Peripheral PLL VCO register + alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.vco & + ALT_CLKMGR_PERPLL_VCO_OUTRST_CLR_MSK & ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_CLR_MSK); + // the outreset and outresetall bits were probably clear when the + // state was saved, but make sure they're clear now + + // Peripheral PLL Misc register + alt_write_word(ALT_CLKMGR_PERPLL_MISC_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.misc); + + // Peripheral PLL C0-C5 Counters + alt_write_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.emac0clk); + alt_write_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.emac1clk); + alt_write_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.perqspiclk); + alt_write_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.pernandsdmmcclk); + alt_write_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.perbaseclk); + alt_write_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.s2fuser1clk); + + // Peripheral PLL Counter Enable register + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.en); + + // Peripheral PLL Divider register + alt_write_word(ALT_CLKMGR_PERPLL_DIV_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.div); + + // Peripheral PLL GPIO Divider register + alt_write_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.gpiodiv); + + // Peripheral PLL Source register + alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.src); + } + else if (clk_group == ALT_SDRAM_PLL_CLK_GRP) + { + // SDRAM PLL VCO register + alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.vco & + ALT_CLKMGR_SDRPLL_VCO_OUTRST_CLR_MSK & ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_CLR_MSK); + // the outreset and outresetall bits were probably clear when the + // state was saved, but make sure they're clear now + + // SDRAM PLL Control register + alt_write_word(ALT_CLKMGR_SDRPLL_CTL_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ctrl); + + // SDRAM PLL C0-C2 & C5 Counters + alt_write_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddrdqsclk); + alt_write_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddr2xdqsclk); + alt_write_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddrdqclk); + alt_write_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.s2fuser2clk); + + // SDRAM PLL Counter Enable register + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.en); + } -/****************************************************************************************/ -/* alt_clk_group_cfg_raw_set() sets the clock group configuration. */ -/****************************************************************************************/ + // if PLL was not bypassed before, restore that state + if (byp) + { + status = alt_clk_pll_bypass_disable(pll); + } -ALT_STATUS_CODE alt_clk_group_cfg_raw_set(const ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg) -{ - ALT_STATUS_CODE ret = ALT_E_ERROR; - ALT_CLK_GRP_t clk_group; - ALT_CLK_t pll = ALT_CLK_UNKNOWN; - bool byp = false; - uint32_t *tmp; + return status; +} +// +// alt_clk_id_to_string() converts a clock ID to a text string. +// +ALT_STATUS_CODE alt_clk_id_to_string(ALT_CLK_t clk_id, char * output, size_t size) +{ + char * name = NULL; - if (clk_group_raw_cfg != NULL) + switch (clk_id) { - // test for matching silicon ID, but not for matching silicon revision number - if (ALT_SYSMGR_SILICONID1_ID_GET(alt_read_word(ALT_SYSMGR_SILICONID1_ADDR)) == - ALT_SYSMGR_SILICONID1_ID_GET(clk_group_raw_cfg->verid)) - { - // get the PLL ID - clk_group = clk_group_raw_cfg->clkgrpsel; - if (clk_group == ALT_MAIN_PLL_CLK_GRP) { pll = ALT_CLK_MAIN_PLL; } - else if (clk_group == ALT_PERIPH_PLL_CLK_GRP) { pll = ALT_CLK_PERIPHERAL_PLL; } - else if (clk_group == ALT_SDRAM_PLL_CLK_GRP) { pll = ALT_CLK_SDRAM_PLL; } - else { return ret; } - if (pll == ALT_CLK_UNKNOWN) { return ret; } - - // if the PLL isn't in bypass mode, put it in bypass mode - ret = alt_clk_pll_is_bypassed(pll); - if (ret == ALT_E_FALSE) - { - ret = alt_clk_pll_bypass_enable(pll, false); - byp = true; - } + case ALT_CLK_IN_PIN_OSC1: + name = "IN_PIN_OSC1"; + break; + case ALT_CLK_IN_PIN_OSC2: + name = "IN_PIN_OSC2"; + break; + // FPGA Clock Sources External to HPS + case ALT_CLK_F2H_PERIPH_REF: + name = "F2H_PERIPH_REF"; + break; + case ALT_CLK_F2H_SDRAM_REF: + name = "F2H_SDRAM_REF"; + break; - // now write the values in the ALT_CLK_GROUP_RAW_CFG_t structure to the registers - if (clk_group == ALT_MAIN_PLL_CLK_GRP) - { - /* Main PLL VCO register */ - tmp = (uint32_t *) &clk_group_raw_cfg->clkgrp.mainpllgrp.vco; - alt_write_word(ALT_CLKMGR_MAINPLL_VCO_ADDR, *tmp & - (ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_CLR_MSK & ALT_CLKMGR_MAINPLL_VCO_OUTRST_CLR_MSK)); - // the outreset and outresetall bits were probably clear when the - // state was saved, but make sure they're clear now - - /* Main PLL Misc register */ - alt_indread_word(ALT_CLKMGR_MAINPLL_MISC_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.misc); - - /* Main PLL C0-C5 Counter registers */ - alt_indread_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.mpuclk); - alt_indread_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.mainclk); - alt_indread_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.dbgatclk); - alt_indread_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.mainqspiclk); - alt_indread_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.mainnandsdmmcclk); - alt_indread_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.cfgs2fuser0clk); - - /* Main PLL Counter Enable register */ - alt_indread_word(ALT_CLKMGR_MAINPLL_EN_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.en); - /* Main PLL Maindiv register */ - alt_indread_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.maindiv); - /* Main PLL Debugdiv register */ - alt_indread_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.dbgdiv); - /* Main PLL Tracediv register */ - alt_indread_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.tracediv); - /* Main PLL L4 Source register */ - alt_indread_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.l4src); - - // remove bypass - ret = ALT_E_SUCCESS; - } + // Other Clock Sources External to HPS + case ALT_CLK_IN_PIN_JTAG: + name = "IN_PIN_JTAG"; + break; + case ALT_CLK_IN_PIN_ULPI0: + name = "IN_PIN_ULPI0"; + break; + case ALT_CLK_IN_PIN_ULPI1: + name = "IN_PIN_ULPI1"; + break; + case ALT_CLK_IN_PIN_EMAC0_RX: + name = "IN_PIN_EMAC0_RX"; + break; + case ALT_CLK_IN_PIN_EMAC1_RX: + name = "IN_PIN_EMAC1_RX"; + break; - else if (clk_group == ALT_PERIPH_PLL_CLK_GRP) - { - /* Peripheral PLL VCO register */ - tmp = (uint32_t *) &clk_group_raw_cfg->clkgrp.perpllgrp.vco; - alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, *tmp & (ALT_CLKMGR_PERPLL_VCO_OUTRST_CLR_MSK & ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_CLR_MSK)); - // the outreset and outresetall bits were probably clear when the - // state was saved, but make sure they're clear now + // PLLs + case ALT_CLK_MAIN_PLL: + name = "MAIN_PLL"; + break; + case ALT_CLK_PERIPHERAL_PLL: + name = "PERIPHERAL_PLL"; + break; + case ALT_CLK_SDRAM_PLL: + name = "SDRAM_PLL"; + break; - /* Peripheral PLL Misc register */ - alt_indread_word(ALT_CLKMGR_PERPLL_MISC_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.misc); + // OSC1 Clock Group - The OSC1 clock group contains those clocks which are derived + // directly from the osc_clk_1_HPS pin + case ALT_CLK_OSC1: + name = "OSC1"; + break; - /* Peripheral PLL C0-C5 Counters */ - alt_indread_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.emac0clk); - alt_indread_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.emac1clk); - alt_indread_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.perqspiclk); - alt_indread_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.pernandsdmmcclk); - alt_indread_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.perbaseclk); - alt_indread_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.s2fuser1clk); + // Main Clock Group - The following clocks are derived from the Main PLL. + case ALT_CLK_MAIN_PLL_C0: + name = "MAIN_PLL_C0"; + break; + case ALT_CLK_MAIN_PLL_C1: + name = "MAIN_PLL_C1"; + break; + case ALT_CLK_MAIN_PLL_C2: + name = "MAIN_PLL_C2"; + break; + case ALT_CLK_MAIN_PLL_C3: + name = "MAIN_PLL_C3"; + break; + case ALT_CLK_MAIN_PLL_C4: + name = "MAIN_PLL_C4"; + break; + case ALT_CLK_MAIN_PLL_C5: + name = "MAIN_PLL_C5"; + break; + case ALT_CLK_MPU: + name = "MPU"; + break; + case ALT_CLK_MPU_L2_RAM: + name = "MPU_L2_RAM"; + break; + case ALT_CLK_MPU_PERIPH: + name = "MPU_PERIPH"; + break; + case ALT_CLK_L3_MAIN: + name = "L3_MAIN"; + break; + case ALT_CLK_L3_MP: + name = "L3_MP"; + break; + case ALT_CLK_L3_SP: + name = "L3_SP"; + break; + case ALT_CLK_L4_MAIN: + name = "L4_MAIN"; + break; + case ALT_CLK_L4_MP: + name = "L4_MP"; + break; + case ALT_CLK_L4_SP: + name = "L4_SP"; + break; + case ALT_CLK_DBG_BASE: + name = "DBG_BASE"; + break; + case ALT_CLK_DBG_AT: + name = "DBG_AT"; + break; + case ALT_CLK_DBG_TRACE: + name = "DBG_TRACE"; + break; + case ALT_CLK_DBG_TIMER: + name = "DBG_TIMER"; + break; + case ALT_CLK_DBG: + name = "DBG"; + break; + case ALT_CLK_MAIN_QSPI: + name = "MAIN_QSPI"; + break; + case ALT_CLK_MAIN_NAND_SDMMC: + name = "MAIN_NAND_SDMMC"; + break; + case ALT_CLK_CFG: + name = "CFG"; + break; + case ALT_CLK_H2F_USER0: + name = "H2F_USER0"; + break; - /* Peripheral PLL Counter Enable register */ - alt_indread_word(ALT_CLKMGR_PERPLL_EN_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.en); + // Peripherals Clock Group - The following clocks are derived from the Peripheral PLL. + case ALT_CLK_PERIPHERAL_PLL_C0: + name = "PERIPHERAL_PLL_C0"; + break; + case ALT_CLK_PERIPHERAL_PLL_C1: + name = "PERIPHERAL_PLL_C1"; + break; + case ALT_CLK_PERIPHERAL_PLL_C2: + name = "PERIPHERAL_PLL_C2"; + break; + case ALT_CLK_PERIPHERAL_PLL_C3: + name = "PERIPHERAL_PLL_C3"; + break; + case ALT_CLK_PERIPHERAL_PLL_C4: + name = "PERIPHERAL_PLL_C4"; + break; + case ALT_CLK_PERIPHERAL_PLL_C5: + name = "PERIPHERAL_PLL_C5"; + break; + case ALT_CLK_USB_MP: + name = "USB_MP"; + break; + case ALT_CLK_SPI_M: + name = "SPI_M"; + break; + case ALT_CLK_QSPI: + name = "QSPI"; + break; + case ALT_CLK_NAND_X: + name = "NAND_X"; + break; + case ALT_CLK_NAND: + name = "NAND"; + break; + case ALT_CLK_SDMMC: + name = "SDMMC"; + break; + case ALT_CLK_EMAC0: + name = "EMAC0"; + break; + case ALT_CLK_EMAC1: + name = "EMAC1"; + break; + case ALT_CLK_CAN0: + name = "CAN0"; + break; + case ALT_CLK_CAN1: + name = "CAN1"; + break; + case ALT_CLK_GPIO_DB: + name = "GPIO_DB"; + break; + case ALT_CLK_H2F_USER1: + name = "H2F_USER1"; + break; - /* Peripheral PLL Divider register */ - alt_indread_word(ALT_CLKMGR_PERPLL_DIV_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.div); + // SDRAM Clock Group - The following clocks are derived from the SDRAM PLL. + case ALT_CLK_SDRAM_PLL_C0: + name = "SDRAM_PLL_C0"; + break; + case ALT_CLK_SDRAM_PLL_C1: + name = "SDRAM_PLL_C1"; + break; + case ALT_CLK_SDRAM_PLL_C2: + name = "SDRAM_PLL_C2"; + break; + case ALT_CLK_SDRAM_PLL_C3: + name = "SDRAM_PLL_C3"; + break; + case ALT_CLK_SDRAM_PLL_C4: + name = "SDRAM_PLL_C4"; + break; + case ALT_CLK_SDRAM_PLL_C5: + name = "SDRAM_PLL_C5"; + break; + case ALT_CLK_DDR_DQS: + name = "DDR_DQS"; + break; + case ALT_CLK_DDR_2X_DQS: + name = "DDR_2X_DQS"; + break; + case ALT_CLK_DDR_DQ: + name = "DDR_DQ"; + break; + case ALT_CLK_H2F_USER2: + name = "H2F_USER2"; + break; - /* Peripheral PLL GPIO Divider register */ - alt_indread_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.gpiodiv); + // Clock Output Pins + case ALT_CLK_OUT_PIN_EMAC0_TX: + name = "OUT_PIN_EMAC0_TX"; + break; + case ALT_CLK_OUT_PIN_EMAC1_TX: + name = "OUT_PIN_EMAC1_TX"; + break; + case ALT_CLK_OUT_PIN_SDMMC: + name = "OUT_PIN_SDMMC"; + break; + case ALT_CLK_OUT_PIN_I2C0_SCL: + name = "OUT_PIN_I2C0_SCL"; + break; + case ALT_CLK_OUT_PIN_I2C1_SCL: + name = "OUT_PIN_I2C1_SCL"; + break; + case ALT_CLK_OUT_PIN_I2C2_SCL: + name = "OUT_PIN_I2C2_SCL"; + break; + case ALT_CLK_OUT_PIN_I2C3_SCL: + name = "OUT_PIN_I2C3_SCL"; + break; + case ALT_CLK_OUT_PIN_SPIM0: + name = "OUT_PIN_SPIM0"; + break; + case ALT_CLK_OUT_PIN_SPIM1: + name = "OUT_PIN_SPIM1"; + break; + case ALT_CLK_OUT_PIN_QSPI: + name = "OUT_PIN_QSPI"; + break; + case ALT_CLK_UNKNOWN: + name = "UNKNOWN"; + break; - /* Peripheral PLL Source register */ - alt_indread_word(ALT_CLKMGR_PERPLL_SRC_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.src); + // do *not* put a 'default' statement here. Then the compiler will throw + // an error if another clock id enum is added if the corresponding + // string is not added to this function. + } - ret = ALT_E_SUCCESS; - } - else if (clk_group == ALT_SDRAM_PLL_CLK_GRP) - { - /* SDRAM PLL VCO register */ - tmp = (uint32_t *) &clk_group_raw_cfg->clkgrp.sdrpllgrp.vco; - alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, *tmp & (ALT_CLKMGR_SDRPLL_VCO_OUTRST_CLR_MSK & ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_CLR_MSK)); - // the outreset and outresetall bits were probably clear when the - // state was saved, but make sure they're clear now + if (name != NULL) + { + snprintf(output, size, "ALT_CLK_%s", name); + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; + } +} - /* SDRAM PLL Control register */ - alt_indread_word(ALT_CLKMGR_SDRPLL_CTL_ADDR, tmp, &clk_group_raw_cfg->clkgrp.sdrpllgrp.ctrl); - /* SDRAM PLL C0-C2 & C5 Counters */ - alt_indread_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.sdrpllgrp.ddrdqsclk); - alt_indread_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.sdrpllgrp.ddr2xdqsclk); - alt_indread_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.sdrpllgrp.ddrdqclk); - alt_indread_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.sdrpllgrp.s2fuser2clk); +// +// alt_clk_pll_cntr_maxfreq_recalc() recalculate the maxmum frequency of the specified clock. +// +ALT_STATUS_CODE alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_t clk, ALT_PLL_CNTR_FREQMAX_t * maxfreq) +{ + ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + alt_freq_t freq; - /* SDRAM PLL Counter Enable register */ - alt_indread_word(ALT_CLKMGR_SDRPLL_EN_ADDR, tmp, &clk_group_raw_cfg->clkgrp.sdrpllgrp.en); + ret = alt_clk_freq_get(clk, &freq); - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_BAD_ARG; } - } - else { ret = ALT_E_BAD_VERSION; } + if (ret == ALT_E_SUCCESS) + { + + switch (clk) + { + // Main Clock Group + case ALT_CLK_MAIN_PLL_C0: + maxfreq->MainPLL_C0 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C0 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_MAIN_PLL_C1: + maxfreq->MainPLL_C1 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C1 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_MAIN_PLL_C2: + maxfreq->MainPLL_C2 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C2 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_MAIN_PLL_C3: + maxfreq->MainPLL_C3 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C3 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_MAIN_PLL_C4: + maxfreq->MainPLL_C4 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C4 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_MAIN_PLL_C5: + maxfreq->MainPLL_C5 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C5 = %10d\n", (unsigned int)freq); + break; + + // Peripheral Clock Group + case ALT_CLK_PERIPHERAL_PLL_C0: + maxfreq->PeriphPLL_C0 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C0 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_PERIPHERAL_PLL_C1: + maxfreq->PeriphPLL_C1 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C1 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_PERIPHERAL_PLL_C2: + maxfreq->PeriphPLL_C2 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C2 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_PERIPHERAL_PLL_C3: + maxfreq->PeriphPLL_C3 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C3 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_PERIPHERAL_PLL_C4: + maxfreq->PeriphPLL_C4 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C4 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_PERIPHERAL_PLL_C5: + maxfreq->PeriphPLL_C5 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C5 = %10d\n", (unsigned int)freq); + break; + + // SDRAM Clock Group + case ALT_CLK_SDRAM_PLL_C0: + maxfreq->SDRAMPLL_C0 = freq; + printf("alt_pll_cntr_maxfreq.SDRAMPLL_C0 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_SDRAM_PLL_C1: + maxfreq->SDRAMPLL_C1 = freq; + printf("alt_pll_cntr_maxfreq.SDRAMPLL_C1 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_SDRAM_PLL_C2: + maxfreq->SDRAMPLL_C2 = freq; + printf("alt_pll_cntr_maxfreq.SDRAMPLL_C2 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_SDRAM_PLL_C5: + maxfreq->SDRAMPLL_C5 = freq; + printf("alt_pll_cntr_maxfreq.SDRAMPLL_C5 = %10d\n", (unsigned int)freq); + break; + default: + ret = ALT_E_BAD_ARG; + printf("bad max frequency parameter\n"); + break; + } // end of switch-case construct } - // if PLL was not bypassed before, restore that state - if (byp) { ret = alt_clk_pll_bypass_disable(pll); } return ret; } + +// +// u-boot preloader actually initialize clock manager circuitry +// +// alt_clk_clkmgr_init() attempt to fix the pll counter max frequencies, since +// thses frequencies are not known in advance until u-boot programmed clock manager. +// +ALT_STATUS_CODE alt_clk_clkmgr_init(void) +{ + ALT_STATUS_CODE ret = ALT_E_SUCCESS; + ALT_STATUS_CODE status ; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C0,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C1,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C2,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C3,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C4,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C5,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C0,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C1,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C2,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C3,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C4,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C5,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_SDRAM_PLL_C0,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_SDRAM_PLL_C1,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_SDRAM_PLL_C2,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_SDRAM_PLL_C5,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + + return ret; +} + diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_generalpurpose_io.c b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_generalpurpose_io.c index e2b0135c34..d5b6afad04 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_generalpurpose_io.c +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_generalpurpose_io.c @@ -35,6 +35,7 @@ #include "socal/hps.h" #include "socal/socal.h" #include "socal/alt_gpio.h" +#include "socal/alt_rstmgr.h" #include "hwlib.h" #include "alt_generalpurpose_io.h" @@ -53,6 +54,37 @@ /****************************************************************************************/ +/* alt_gpio_init() initializes the GPIO modules */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_init(void) +{ + // put GPIO modules into system manager reset if not already there + alt_gpio_uninit(); + // release GPIO modules from system reset (w/ two-instruction delay) + alt_replbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK | + ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK | + ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK, 0); + return ALT_E_SUCCESS; +} + + +/****************************************************************************************/ +/* alt_gpio_uninit() uninitializes the GPIO modules */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_uninit(void) +{ + // put all GPIO modules into system manager reset + alt_replbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK | + ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK | + ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK, + ALT_GPIO_BITMASK); + return ALT_E_SUCCESS; +} + + +/****************************************************************************************/ /* alt_gpio_port_datadir_set() sets the specified GPIO data bits to use the data */ /* direction(s) specified. 0 = input (default). 1 = output. */ /****************************************************************************************/ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am index 4e3b586341..4093831f3d 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = @@ -183,6 +183,10 @@ $(PROJECT_INCLUDE)/bsp/hwlib.h: hwlib/include/hwlib.h $(PROJECT_INCLUDE)/bsp/$(d $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/hwlib.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/hwlib.h +$(PROJECT_INCLUDE)/bsp/socal/alt_acpidmap.h: hwlib/include/socal/alt_acpidmap.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_acpidmap.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_acpidmap.h + $(PROJECT_INCLUDE)/bsp/socal/alt_clkmgr.h: hwlib/include/socal/alt_clkmgr.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_clkmgr.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_clkmgr.h |