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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-19 10:15:53 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-25 10:07:43 +0200 |
| commit | 5694b0cce4908172af3f6292e7f111ac26620af7 (patch) | |
| tree | f351a0f6094538b59382ef037389f5884ed81926 /c/src | |
| parent | riscv: Add exception codes (diff) | |
| download | rtems-5694b0cce4908172af3f6292e7f111ac26620af7.tar.bz2 | |
riscv: New CPU_Exception_frame
Use the CPU_Interrupt_frame for the volatile context. Add non-volatile
registers and extra state on top of it.
Update #3433.
Diffstat (limited to 'c/src')
0 files changed, 0 insertions, 0 deletions