2008-09-30 Jennifer Averett <jennifer.averett@oarcorp.com>

	* Makefile.am, preinstall.am, PCI_bus/universe.c, console/console.c,
	include/bsp.h, irq/FPGA.c, irq/irq.c, startup/Hwr_init.c,
	startup/bspstart.c, startup/vmeintr.c: Modifications required to run
	on hardware. Some cleanup.

11 files changed, 110 insertions, 327 deletions

diff --git a/c/src/lib/libbsp/powerpc/score603e/ChangeLog b/c/src/lib/libbsp/powerpc/score603e/ChangeLog
index d9f871b419..7eb0c9daa1 100644
--- a/c/src/lib/libbsp/powerpc/score603e/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/score603e/ChangeLog
@@ -1,3 +1,10 @@
+2008-09-30	Jennifer Averett <jennifer.averett@oarcorp.com>
+
+	* Makefile.am, preinstall.am, PCI_bus/universe.c, console/console.c,
+	include/bsp.h, irq/FPGA.c, irq/irq.c, startup/Hwr_init.c,
+	startup/bspstart.c, startup/vmeintr.c: Modifications required to run
+	on hardware. Some cleanup.
+
 2008-09-29	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* Makefile.am: Eliminate bsp.am. Build startup files as side-effect 
diff --git a/c/src/lib/libbsp/powerpc/score603e/Makefile.am b/c/src/lib/libbsp/powerpc/score603e/Makefile.am
index 828bca6eb0..f059afb6aa 100644
--- a/c/src/lib/libbsp/powerpc/score603e/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/score603e/Makefile.am
@@ -48,11 +48,11 @@ libbsp_a_SOURCES += console/85c30.c console/85c30.h console/console.c \
     console/tbl85c30.c console/consolebsp.h
 
 include_bsp_HEADERS = ../../powerpc/shared/pci/pci.h \
-    PCI_bus/PCI.h \
-    ../../powerpc/shared/residual/residual.h \
+    PCI_bus/PCI.h ../../powerpc/shared/residual/residual.h \
     ../../powerpc/shared/residual/pnp.h \
     ../../powerpc/shared/openpic/openpic.h \
-    ../../powerpc/shared/console/consoleIo.h
+    ../../powerpc/shared/console/consoleIo.h \
+    ../../shared/include/irq-generic.h include/irq-config.h
 # pci
 libbsp_a_SOURCES += pci/no_host_bridge.c ../../powerpc/shared/pci/pci.c \
     ../../powerpc/shared/pci/pcifinddevice.c  PCI_bus/PCI.c  PCI_bus/universe.c
@@ -62,7 +62,8 @@ include_bsp_HEADERS += irq/irq.h \
     ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \
     ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
 # irq
-libbsp_a_SOURCES += irq/FPGA.c irq/irq.c ../../powerpc/shared/irq/irq_asm.S
+libbsp_a_SOURCES += include/irq-config.h irq/FPGA.c irq/irq.c  \
+    ../../shared/src/irq-generic.c ../../powerpc/shared/irq/irq_asm.S
 
 include_bsp_HEADERS += ../../powerpc/shared/vectors/vectors.h
 # vectors
@@ -70,6 +71,7 @@ libbsp_a_SOURCES += ../../powerpc/shared/vectors/vectors_init.c \
     ../../powerpc/shared/vectors/vectors.S
 
 include_bsp_HEADERS += ../../shared/vmeUniverse/vmeUniverse.h \
+    ../../shared/include/irq-generic.h \
     ../../shared/vmeUniverse/vme_am_defs.h \
     ../../shared/vmeUniverse/VME.h \
     vme/VMEConfig.h \
diff --git a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c
index fb8dcc45eb..0ceefe6c96 100644
--- a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c
+++ b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c
@@ -157,15 +157,14 @@ void initialize_universe()
 {
   uint32_t         jumper_selection;
   uint32_t         pci_id;
-#if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE)
-  volatile uint32_t         universe_temp_value;
-#endif
 
   /*
    * Read the VME jumper location to determine the VME base address
    */
   jumper_selection = PCI_bus_read(
                      (volatile uint32_t*)SCORE603E_VME_JUMPER_ADDR );
+  printk("initialize_universe: Read 0x%x = 0x%x\n", 
+          SCORE603E_VME_JUMPER_ADDR, jumper_selection);
   jumper_selection = (jumper_selection >> 3) & 0x1f;
 
   /*
@@ -179,67 +178,14 @@ void initialize_universe()
    if (pci_id !=  SCORE603E_UNIVERSE_CHIP_ID ){
      printk ("Invalid SCORE603E_UNIVERSE_CHIP_ID: 0x08%" PRId32 "\n", pci_id);
      rtems_fatal_error_occurred( 0x603e0bad );
+   } else {
+     printk("initialize_universe: Reg 0x%x read 0x%x\n", 
+     SCORE603E_IO_VME_UNIVERSE_BASE, pci_id );
    }
 
-#if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE)
-
-   /*
-    * Set the UNIVERSE PCI Configuration Base Address Register with 0x30001
-    * to specifies the 64 Kbyte aligned base address of the UNIVERSE register
-    * space on PCI to be 0x30000 + 0x80000000 (IO_BASE)
-    */
-   Write_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE+0x10,0x30001 );
-
-   /*
-    * Set the UNIVERSE PCI Configuration Space Control and Status Register to
-    * medium speed device, Target Back to Back Capable, Master Enable, Target
-    * Memory Enable and Target IO Enable
-    */
-   Write_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE+0x4, 0x2800007 );
-
-   /*
-    * Turn off the sysfail by setting SYSFAIL bit to 1 on the VCSR_CLR register
-    */
-   PCI_bus_write( &UNIVERSE->VCSR_CLR, 0x40000000 );
-
-   /*
-    * Set the VMEbus Master Control register with retry forever, 256 bytes
-    * posted write transfer count, VMEbus request level 3, RWD, PCI 32 bytes
-    * aligned burst size and PCI bus number to be zero
-    */
-   PCI_bus_write( &UNIVERSE->MAST_CTL, 0x01C00000 );
-
-   /*
-    * VMEbus DMA Transfer Control register with 32 bit VMEbus Maximum Data
-    * width, A32 VMEbus Address Space, AM code to be data, none-privilleged,
-    * single and BLT cycles on VME bus and 64-bit PCI Bus Transactions enable
-    PCI_bus_write( &UNIVERSE->DCTL, 0x00820180 );
-    */
-
-   PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 );
-   PCI_bus_write( &UNIVERSE->LSI0_BS,  0x04000000 );
-   PCI_bus_write( &UNIVERSE->LSI0_BD,  0x05000000 );
-   PCI_bus_write( &UNIVERSE->LSI0_TO,  0x7C000000 );
-
-   /*
-    * Remove the Universe from VMEbus BI-Mode (bus-isolation).  Once out of
-    * BI-Mode VMEbus accesses can be made.
-    */
-
-   universe_temp_value = PCI_bus_read( &UNIVERSE->MISC_CTL );
-
-   if (universe_temp_value & 0x100000)
-     PCI_bus_write( &UNIVERSE->MISC_CTL,(universe_temp_value | ~0xFF0FFFFF));
-
-#elif (SCORE603E_USE_DINK)
    /*
     * Do not modify the DINK setup of the universe chip.
     */
-
-#else
-#error "SCORE603E BSPSTART.C -- what ROM monitor are you using"
-#endif
-
 }
 
 /*
diff --git a/c/src/lib/libbsp/powerpc/score603e/console/console.c b/c/src/lib/libbsp/powerpc/score603e/console/console.c
index a385431876..cefb732fe1 100644
--- a/c/src/lib/libbsp/powerpc/score603e/console/console.c
+++ b/c/src/lib/libbsp/powerpc/score603e/console/console.c
@@ -23,7 +23,6 @@
 #include "consolebsp.h"
 #include <rtems/bspIo.h>
 
-#if (1)
 /*
  * The Port Used for the Console interface is based upon which
  * debugger is being used.  The SDS debugger uses a binary
@@ -31,28 +30,7 @@
  * not be used as the console port for the SDS debugger.
  */
 
-#if (SCORE603E_USE_SDS)
-#define USE_FOR_CONSOLE_DEF  1
-
-#elif (SCORE603E_USE_OPEN_FIRMWARE)
-#define USE_FOR_CONSOLE_DEF  0
-
-#elif (SCORE603E_USE_NONE)
-#define USE_FOR_CONSOLE_DEF  0
-
-#elif (SCORE603E_USE_DINK)
 #define USE_FOR_CONSOLE_DEF  0
-
-#else
-#error "SCORE603E CONSOLE.C -- what ROM monitor are you using"
-#endif
-
-#endif
-
-#if (0)
-extern int USE_FOR_CONSOLE;
-#endif
-
 int USE_FOR_CONSOLE = USE_FOR_CONSOLE_DEF;
 
 /*
@@ -134,12 +112,6 @@ rtems_isr console_isr(
 
   for (i=0; i < NUM_Z85C30_PORTS; i++){
       ISR_85c30_Async( &Ports_85C30[i] );
-
-#if (0) /* XXX - TO TEST LOOP BACKS comment this out. */
-    if ( Ports_85C30[i].Chip->vector == vector ) {
-      ISR_85c30_Async( &Ports_85C30[i] );
-    }
-#endif
   }
 }
 
@@ -191,7 +163,6 @@ void console_outbyte_interrupts(
   char ch
 );
 
-/* XXXXXX */
 #endif
 
 /* PAGE
diff --git a/c/src/lib/libbsp/powerpc/score603e/include/bsp.h b/c/src/lib/libbsp/powerpc/score603e/include/bsp.h
index 638a2b9373..84585f3234 100644
--- a/c/src/lib/libbsp/powerpc/score603e/include/bsp.h
+++ b/c/src/lib/libbsp/powerpc/score603e/include/bsp.h
@@ -34,6 +34,8 @@ extern "C" {
 #if (HAS_PMC_PSC8)
 #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS (4 + 4)
 #else
+/* XXXXX FIX THIS */
+#error "MUST HAVE PSC8 SET FOR BOEING CODE"
 #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS (4)
 #endif
 
@@ -75,7 +77,7 @@ extern "C" {
                                SCORE603E_BRD_FLASH_DISABLE_MASK) 
 
 #define Processor_Synchronize() \
-  asm(" eieio ")
+  asm volatile(" eieio ")
 
 
 /*
@@ -96,17 +98,6 @@ extern unsigned int BSP_mem_size;
 /* functions */
 
 /*
- * spurious.c
- */
-rtems_isr bsp_stub_handler(
-   rtems_vector_number trap
-);
-rtems_isr bsp_spurious_handler(
-   rtems_vector_number trap
-);
-void bsp_spurious_initialize();
-
-/*
  * genvec.c
  */
 rtems_isr_entry  set_EE_vector(
diff --git a/c/src/lib/libbsp/powerpc/score603e/irq/FPGA.c b/c/src/lib/libbsp/powerpc/score603e/irq/FPGA.c
index 2907a1c308..f7a5a7d4df 100644
--- a/c/src/lib/libbsp/powerpc/score603e/irq/FPGA.c
+++ b/c/src/lib/libbsp/powerpc/score603e/irq/FPGA.c
@@ -22,21 +22,10 @@
  */
 void initialize_PCI_bridge (void)
 {
-#if (!SCORE603E_USE_DINK)
-  uint16_t         mask, shift, data;
-
-  shift = SCORE603E_85C30_0_IRQ - Score_IRQ_First;
-  mask = 1 << shift;
-
-  shift = SCORE603E_85C30_1_IRQ - Score_IRQ_First;
-  mask  = mask & (1 << shift);
-
-  data = *SCORE603E_FPGA_MASK_DATA;
-  data = ~mask;
-
-  *SCORE603E_FPGA_MASK_DATA = data;
-#endif
-
+  /* Note: Accept DINKs setup of the PCI Bridge and don't 
+   *       change anything.
+   */
+  printk("initialize_PCI_bridge: \n");
 }
 
 void set_irq_mask(
@@ -93,9 +82,7 @@ void init_irq_data_register(void)
   uint32_t         index;
   uint32_t         i;
 
-#if (SCORE603E_USE_DINK)
   set_irq_mask( 0xffff );
-#endif
 
   /*
    * Clear any existing interupts from the vector data register.
diff --git a/c/src/lib/libbsp/powerpc/score603e/irq/irq.c b/c/src/lib/libbsp/powerpc/score603e/irq/irq.c
index 84b59ab046..31444af39e 100644
--- a/c/src/lib/libbsp/powerpc/score603e/irq/irq.c
+++ b/c/src/lib/libbsp/powerpc/score603e/irq/irq.c
@@ -140,6 +140,27 @@ printk(" BSP_install_rtems_shared_irq_handler %d\n", irq->name );
 }
 
 /*
+ * This function disables a given XXX interrupt
+ */
+rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number irqLine)
+{
+  /* XXX FIX ME!!!! */
+
+  printk("bsp_interrupt_vector_disable: 0x%x\n", irqLine );
+  return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number irqLine)
+{
+  /* XXX FIX ME!!!! */
+  printk("bsp_interrupt_vector_enable: 0x%x\n", irqLine );
+
+  return RTEMS_SUCCESSFUL;
+}
+
+
+
+/*
  * ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
  */
 
@@ -178,18 +199,23 @@ printk(" BSP_install_rtems_irq_handler %d\n", irq->name );
       /*
        * Enable interrupt 
        */
+      printk("is_pci_irq = TRUE - FIX THIS!\n");
     }
 
     if (is_processor_irq(irq->name)) {
       /*
        * Enable exception at processor level
        */
+      printk("is_processor_irq = TRUE : Fix This\n");
     }
+
     /*
      * Enable interrupt on device
      */
-	if (irq->on)
+    if (irq->on) {
+        printk("Call 0x%x\n", irq->on );
     	irq->on(irq);
+    }
 
     rtems_interrupt_enable(level);
 
@@ -415,7 +441,6 @@ int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
   register unsigned msr;
   register unsigned new_msr;
 
-printk(" C_dispatch_irq_handler %d\n", excNum);
   if (excNum == ASM_DEC_VECTOR) {
     _CPU_MSR_GET(msr);
     new_msr = msr | MSR_EE;
@@ -468,3 +493,21 @@ printk(" _ThreadProcessSignalsFromIrq \n");
    * This will include DEBUG session requested from keyboard...
    */
 }
+
+rtems_status_code bsp_interrupt_facility_initialize( void)
+{
+  /* Install exception handler */
+  if (ppc_exc_set_handler( ASM_EXT_VECTOR, C_dispatch_irq_handler)) {
+    return RTEMS_IO_ERROR;
+  }
+  if (ppc_exc_set_handler( ASM_DEC_VECTOR, C_dispatch_irq_handler)) {
+    return RTEMS_IO_ERROR;
+  }
+  if (ppc_exc_set_handler( ASM_E300_SYSMGMT_VECTOR, C_dispatch_irq_handler)) {
+    return RTEMS_IO_ERROR;
+  }
+
+  return RTEMS_SUCCESSFUL;
+}
+
+
diff --git a/c/src/lib/libbsp/powerpc/score603e/preinstall.am b/c/src/lib/libbsp/powerpc/score603e/preinstall.am
index 12a3f838fa..c186314fb0 100644
--- a/c/src/lib/libbsp/powerpc/score603e/preinstall.am
+++ b/c/src/lib/libbsp/powerpc/score603e/preinstall.am
@@ -93,6 +93,14 @@ $(PROJECT_INCLUDE)/bsp/consoleIo.h: ../../powerpc/shared/console/consoleIo.h $(P
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/consoleIo.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/consoleIo.h
 
+$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
+
+$(PROJECT_INCLUDE)/bsp/irq-config.h: include/irq-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-config.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-config.h
+
 $(PROJECT_INCLUDE)/bsp/irq.h: irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
@@ -117,6 +125,10 @@ $(PROJECT_INCLUDE)/bsp/vmeUniverse.h: ../../shared/vmeUniverse/vmeUniverse.h $(P
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vmeUniverse.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vmeUniverse.h
 
+$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
+
 $(PROJECT_INCLUDE)/bsp/vme_am_defs.h: ../../shared/vmeUniverse/vme_am_defs.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vme_am_defs.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vme_am_defs.h
diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c b/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c
index 6fb0cc6e6b..dc942e873a 100644
--- a/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c
+++ b/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c
@@ -80,70 +80,10 @@ void init_RTC(void)
 
 void init_PCI(void)
 {
-#if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE)
-  uint32_t         value;
-
- /*
-  * NOTE:  Accessing any memory location not mapped by the BAT
-  * registers will cause a TLB miss exception.
-  * Set the DBAT1 to be configured for 256M of PCI MEM
-  * at 0xC0000000 with Write-through and Guarded Attributed and
-  * read/write access allowed
-  */
-
- /* load DBAT1U (spr538) - 256Mbytes, User, Super */
-  value = SCORE603E_PCI_MEM_BASE | 0x1FFF;
-  asm volatile(
-    "isync;"
-    "mtspr 538, %0"
-    : "=r" (value)
-    : "0" (value)
-  );
-
-  /* load DBAT1L (spr539) - Write-through, Guarded and Read/Write */
-  value = SCORE603E_PCI_MEM_BASE | 0x0002;
-  asm volatile (
-      "mtspr 539, %0;"
-      "isync"
-      : "=r" (value)
-      : "0" (value)
-  );
-
-#elif (SCORE603E_USE_DINK)
   /* DINK Monitor setsup and uses all 4 BAT registers.  */
   /* The fourth BAT register can be modified to access this area */
 
-#if (0)
- /*
-  * NOTE:  Accessing any memory location not mapped by the BAT
-  * registers will cause a TLB miss exception.
-  * Set the DBAT3 to be configured for 256M of PCI MEM
-  * at 0xC0000000 with Write-through and Guarded Attributed and
-  * read/write access allowed
-  */
-
- /* load DBAT3U (spr542) - 256Mbytes, User, Super */
-  value = SCORE603E_PCI_MEM_BASE | 0x1FFF;
-  asm volatile(
-    "isync;"
-    "mtspr 542, %0"
-    : "=r" (value)
-    : "0" (value)
-  );
-
-  /* load DBAT3L (spr543) - Write-through, Guarded and Read/Write */
-  value = SCORE603E_PCI_MEM_BASE | 0x0002;
-  asm volatile (
-      "mtspr 543, %0;"
-      "isync"
-      : "=r" (value)
-      : "0" (value)
-  );
-#endif
-
-#else
-#error "SCORE603E BSPSTART.C -- what ROM monitor are you using"
-#endif
+  printk("init_PCI:\n");
 }
 
 #define PPC_Get_HID0( _value ) \
diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c b/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c
index 01e1827964..c7c43285f8 100644
--- a/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c
+++ b/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c
@@ -47,7 +47,7 @@ unsigned int BSP_processor_frequency; /* XXX - Set this based upon the Score boa
 /*
  * Time base divisior (how many tick for 1 second).
  */
-unsigned int BSP_time_base_divisor = 1000;  /* XXX - Just a guess */
+unsigned int BSP_time_base_divisor = 4000;
 
 extern unsigned long __rtems_end[];
 
@@ -79,17 +79,6 @@ void initialize_PMC();
 
 void bsp_predriver_hook(void)
 {
-  #if DEBUG
-    printk("bsp_predriver_hook: init_RTC\n");
-  #endif
-  init_RTC();
-  init_PCI();
-  initialize_universe();
-
-  #if DEBUG
-    printk("bsp_predriver_hook: initialize_PCI_bridge\n");
-  #endif
-  initialize_PCI_bridge ();
 
 #if (HAS_PMC_PSC8)
   #if DEBUG
@@ -98,29 +87,6 @@ void bsp_predriver_hook(void)
   initialize_PMC();
 #endif
 
-#if 0
- /*
-  * Initialize Bsp General purpose vector table.
-  */
-  #if DEBUG
-    printk("bsp_predriver_hook: initialize_external_exception_vector\n");
-  #endif
- initialize_external_exception_vector();
-#endif
-
-#if (0)
-  /*
-   * XXX - Modify this to write a 48000000 (loop to self) command
-   *       to each interrupt location.  This is better for debug.
-   */
-  #if DEBUG
-    printk("bsp_predriver_hook: bsp_spurious_initialize\n");
-  #endif
- bsp_spurious_initialize();
-#endif
-
-  ShowBATS();
-
   #if DEBUG
     printk("bsp_predriver_hook: End of routine\n");
   #endif
@@ -133,64 +99,35 @@ void bsp_predriver_hook(void)
  */
 
 void initialize_PMC() {
-  volatile uint32_t         *PMC_addr;
-  uint8_t          data;
-
-#if (0) /* First Values sent */
-  /*
-   * set PMC base address.
-   */
-  PMC_addr  = BSP_PCI_DEVICE_ADDRESS( 0x14 );
-  *PMC_addr = (BSP_PCI_REGISTER_BASE >> 24) & 0x3f;
+  volatile uint32_t     *PMC_addr;
+  uint32_t               data;
 
   /*
    * Clear status, enable SERR and memory space only.
    */
   PMC_addr = BSP_PCI_DEVICE_ADDRESS( 0x4 );
-  *PMC_addr = 0x0201ff37;
-
-  /*
-   * Bit 0 and 1 HI cause Medium Loopback to occur.
-   */
-  PMC_addr = (volatile uint32_t*)
-        BSP_PMC_SERIAL_ADDRESS( 0x100000 );
-  data = *PMC_addr;
-  /*   *PMC_addr = data | 0x3;  */
-  *PMC_addr = data & 0xfc;
-
-#endif
-
-#if (1)
-
-  /*
-   * Clear status, enable SERR and memory space only.
-   */
+  *PMC_addr = 0x020080cc;
   #if DEBUG
-    printk("initialize_PMC: set Device Address 0x4 \n");
-  ShowBATS();
+    printk("initialize_PMC: 0x%x = 0x%x\n", PMC_addr, 0x020080cc);
   #endif
-  PMC_addr = BSP_PCI_DEVICE_ADDRESS( 0x4 );
-  *PMC_addr = 0x020080cc;
 
   /*
    * set PMC base address.
    */
-  #if DEBUG
-    printk("initialize_PMC: set Device Address 0x14 \n");
-  ShowBATS();
-  #endif
   PMC_addr  = BSP_PCI_DEVICE_ADDRESS( 0x14 );
   *PMC_addr = (BSP_PCI_REGISTER_BASE >> 24) & 0x3f;
-
   #if DEBUG
-    printk("initialize_PMC: set PMC Serial Address 0x100000\n");
+    printk("initialize_PMC: 0x%x = 0x%x\n", PMC_addr, ((BSP_PCI_REGISTER_BASE >> 24) & 0x3f));
   #endif
+
    PMC_addr = (volatile uint32_t*)
       BSP_PMC_SERIAL_ADDRESS( 0x100000 );
   data = *PMC_addr;
+  #if DEBUG
+    printk("initialize_PMC: Read 0x%x (0x%x)\n", PMC_addr, data );
+    printk("initialize_PMC: Read 0x%x (0x%x)\n", PMC_addr, data & 0xfc );
+  #endif
   *PMC_addr = data & 0xfc;
-
-#endif
 }
 
 /*PAGE
@@ -247,7 +184,6 @@ void bsp_start( void )
    */
   #if DEBUG
     printk("bsp_start: Zero out lots of memory\n");
-    ShowBATS();
   #endif
 
   memset(
@@ -266,6 +202,8 @@ void bsp_start( void )
    */
   myCpu         = get_ppc_cpu_type();
   myCpuRevision = get_ppc_cpu_revision();
+  printk("Cpu: 0x%x  Revision: %d\n", myCpu, myCpuRevision);
+  printk("Cpu %s\n", get_ppc_cpu_type_name(myCpu) );
 
   /*
    * Initialize the interrupt related settings.
@@ -279,75 +217,27 @@ void bsp_start( void )
   /*
    * Initialize default raw exception handlers.
    */
-printk("ppc_exc_initialize\n");
   ppc_exc_initialize(
     PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
     intrStackStart,
     intrStackSize
   );
-
-  /*
-   *  There are multiple ROM monitors available for this board.
-   */
-#if (SCORE603E_USE_SDS)
   #if DEBUG
-    printk("bsp_start: USE SDS\n");
+    printk("bsp_predriver_hook: init_RTC\n");
   #endif
 
+/*   init_RTC(); */
+  init_PCI();
+  initialize_universe();
 
-  /*
-   * Write instruction for Unconditional Branch to ROM vector.
-   */
-
-   Code = 0x4bf00002;
-   for (Address = 0x100; Address <= 0xe00; Address += 0x100) {
-     A_Vector = (uint32_t*)Address;
-     Code = 0x4bf00002 + Address;
-     *A_Vector = Code;
-   }
-
-   for (Address = 0x1000; Address <= 0x1400; Address += 0x100) {
-     A_Vector = (uint32_t*)Address;
-     Code = 0x4bf00002 + Address;
-     *A_Vector = Code;
-   }
-
-  msr_value = 0x2030;
-
-#elif (SCORE603E_USE_OPEN_FIRMWARE)
   #if DEBUG
-    printk("bsp_start: USE OPEN FIRMWARE\n");
+    printk("bsp_predriver_hook: initialize_PCI_bridge\n");
   #endif
-  msr_value = 0x2030;
+  initialize_PCI_bridge ();
 
-#elif (SCORE603E_USE_NONE)
-  #if DEBUG
-    printk("bsp_start: USE NONE\n");
-  #endif
   msr_value = 0x2030;
   _CPU_MSR_SET( msr_value );
-  bsp_set_trap_vectors();
 
-#elif (SCORE603E_USE_DINK)
-  #if DEBUG
-    printk("bsp_start: USE DINK\n");
-  #endif
-  msr_value = 0x2030;
-  _CPU_MSR_SET( msr_value );
-
-  /*
-   * Override the DINK error on a Decrementor interrupt.
-   */
-  /* org    dec_vector  - rfi */
-  ptr = (uint32_t*)0x900;
-  *ptr = 0x4c000064;
-
-#else
-  #if DEBUG
-    printk("bsp_start: ERROR unknow ROM Monitor\n");
-  #endif
-#error "SCORE603E BSPSTART.C -- what ROM monitor are you using"
-#endif
 
   _CPU_MSR_SET( msr_value );
 
@@ -369,6 +259,12 @@ printk("ppc_exc_initialize\n");
     printk("bsp_start: END PPC_USE_DATA_CACHE\n");
   #endif
 #endif
+
+  /* Initalize interrupt support */
+  if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
+    BSP_panic( "Cannot intitialize interrupt support\n");
+  }
+
   #if DEBUG
     printk("bsp_start: end BSPSTART\n");
   ShowBATS();
diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/vmeintr.c b/c/src/lib/libbsp/powerpc/score603e/startup/vmeintr.c
index 8e2f334881..db325333e5 100644
--- a/c/src/lib/libbsp/powerpc/score603e/startup/vmeintr.c
+++ b/c/src/lib/libbsp/powerpc/score603e/startup/vmeintr.c
@@ -26,18 +26,12 @@ void VME_interrupt_Disable (
   VME_interrupt_Mask                mask                        /* IN  */
 )
 {
-  volatile uint8_t          *VME_interrupt_enable;
-  uint8_t          value;
+  volatile uint8_t  *VME_interrupt_enable;
+  uint8_t           value;
 
-#if 0
-  VME_interrupt_enable = ACC_VIE;
-#else
   VME_interrupt_enable = 0;
-#endif
   value = *VME_interrupt_enable;
-
   value &= ~mask;  /* turn off interrupts for all levels in mask */
-
   *VME_interrupt_enable = value;
 }
 
@@ -54,14 +48,8 @@ void VME_interrupt_Enable (
   volatile uint8_t          *VME_interrupt_enable;
   uint8_t          value;
 
-#if 0
-  VME_interrupt_enable = ACC_VIE;
-#else
   VME_interrupt_enable = 0;
-#endif
   value = *VME_interrupt_enable;
-
   value |= mask;  /* turn on interrupts for all levels in mask */
-
   *VME_interrupt_enable = value;
 }