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author | Gedare Bloom <gedare@rtems.org> | 2012-03-14 13:06:13 -0400 |
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committer | Gedare Bloom <gedare@rtems.org> | 2012-03-14 13:06:13 -0400 |
commit | 67baf6071d6e92d9e2c959aa5531b84f4afe8063 (patch) | |
tree | f410beef16f1f9d76aa18a3a6529b69a00980121 /c/src/lib/libcpu/sparc64 | |
parent | bsp/lpc24xx: New BSP variant (diff) | |
download | rtems-67baf6071d6e92d9e2c959aa5531b84f4afe8063.tar.bz2 |
PR2041: sparc64: vector number not included in CPU_Interrupt_frame
Add the trap vector to the interrupt frame. Also rename the assembly
macro that accesses the field to be consistent with similar macros.
Diffstat (limited to 'c/src/lib/libcpu/sparc64')
-rw-r--r-- | c/src/lib/libcpu/sparc64/shared/score/interrupt.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/c/src/lib/libcpu/sparc64/shared/score/interrupt.S b/c/src/lib/libcpu/sparc64/shared/score/interrupt.S index 1f666116bb..9e93eff188 100644 --- a/c/src/lib/libcpu/sparc64/shared/score/interrupt.S +++ b/c/src/lib/libcpu/sparc64/shared/score/interrupt.S @@ -118,7 +118,7 @@ PUBLIC(_ISR_Handler) stx %g3, [%sp + STACK_BIAS + ISF_PIL_OFFSET] stx %g4, [%sp + STACK_BIAS + ISF_TPC_OFFSET] stx %g5, [%sp + STACK_BIAS + ISF_TNPC_OFFSET] - stx %g2, [%sp + STACK_BIAS + ISF_TVEC_NUM] + stx %g2, [%sp + STACK_BIAS + ISF_TVEC_OFFSET] rd %y, %g4 ! save y stx %g4, [%sp + STACK_BIAS + ISF_Y_OFFSET] @@ -522,7 +522,7 @@ dispatchAgain: ldx [%sp + STACK_BIAS + ISF_TPC_OFFSET], %g4 ldx [%sp + STACK_BIAS + ISF_TNPC_OFFSET], %g5 ldx [%sp + STACK_BIAS + ISF_TSTATE_OFFSET], %g1 - ldx [%sp + STACK_BIAS + ISF_TVEC_NUM], %g2 + ldx [%sp + STACK_BIAS + ISF_TVEC_OFFSET], %g2 wrpr %g0, %g3, %pil wrpr %g0, %g4, %tpc wrpr %g0, %g5, %tnpc |