Whitespace removal.

2 files changed, 9 insertions, 9 deletions

diff --git a/c/src/lib/libcpu/shared/include/cache.h b/c/src/lib/libcpu/shared/include/cache.h
index 8a1f2c07ba..7bae1259ec 100644
--- a/c/src/lib/libcpu/shared/include/cache.h
+++ b/c/src/lib/libcpu/shared/include/cache.h
@@ -1,6 +1,6 @@
 /*
  *  libcpu Cache Manager Support
- *  
+ *
  *  COPYRIGHT (c) 1989-1999.
  *  On-Line Applications Research Corporation (OAR).
  *
@@ -13,7 +13,7 @@
  *  They provide the processor specific actions to take for
  *  implementing most of the RTEMS Cache Manager directives,
  *  and should only ever be called by these directives.
- *  
+ *
  *  The API for the RTEMS Cache Manager can be found in
  *  c/src/exec/rtems/include/rtems/rtems/cache.h
  *
diff --git a/c/src/lib/libcpu/shared/src/cache_manager.c b/c/src/lib/libcpu/shared/src/cache_manager.c
index 4c87caf49c..8e8ba25d2c 100644
--- a/c/src/lib/libcpu/shared/src/cache_manager.c
+++ b/c/src/lib/libcpu/shared/src/cache_manager.c
@@ -8,7 +8,7 @@
  *  found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  *
- *  
+ *
  *  The functions in this file implement the API to the RTEMS Cache Manager and
  *  are divided into data cache and instruction cache functions. Data cache
  *  functions only have bodies if a data cache is supported. Instruction
@@ -16,14 +16,14 @@
  *  Support for a particular cache exists only if CPU_x_CACHE_ALIGNMENT is
  *  defined, where x E {DATA, INSTRUCTION}. These definitions are found in
  *  the Cache Manager Wrapper header files, often
- *  
+ *
  *  rtems/c/src/lib/libcpu/CPU/cache_.h
- *  
+ *
  *  The functions below are implemented with CPU dependent inline routines
  *  found in the cache.c files for each CPU. In the event that a CPU does
  *  not support a specific function for a cache it has, the CPU dependent
  *  routine does nothing (but does exist).
- *  
+ *
  *  At this point, the Cache Manager makes no considerations, and provides no
  *  support for BSP specific issues such as a secondary cache. In such a system,
  *  the CPU dependent routines would have to be modified, or a BSP layer added
@@ -60,7 +60,7 @@ rtems_cache_flush_multiple_data_lines( const void * d_addr, size_t n_bytes )
   if( n_bytes == 0 )
     /* Do nothing if number of bytes to flush is zero */
     return;
-    
+
   final_address = (void *)((size_t)d_addr + n_bytes - 1);
   d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1));
   while( d_addr <= final_address )  {
@@ -92,7 +92,7 @@ rtems_cache_invalidate_multiple_data_lines( const void * d_addr, size_t n_bytes
   if( n_bytes == 0 )
     /* Do nothing if number of bytes to invalidate is zero */
     return;
-    
+
   final_address = (void *)((size_t)d_addr + n_bytes - 1);
   d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1));
   while( final_address >= d_addr ) {
@@ -219,7 +219,7 @@ rtems_cache_invalidate_multiple_instruction_lines( const void * i_addr, size_t n
   if( n_bytes == 0 )
     /* Do nothing if number of bytes to invalidate is zero */
     return;
-    
+
   final_address = (void *)((size_t)i_addr + n_bytes - 1);
   i_addr = (void *)((size_t)i_addr & ~(CPU_INSTRUCTION_CACHE_ALIGNMENT - 1));
   while( final_address > i_addr ) {