2001-10-11 Alexandra Kossovsky <sasha@oktet.ru>

	* clock/Makefile.am, clock/ckinit.c, clock/.cvsignore, Makefile.am,
	include/Makefile.am, include/iosh7750.h, include/ipl.h,
	include/ispsh7750.h, include/sh4_regs.h, include/sh4uart.h,
	include/sh7750_regs.h, include/.cvsignore, sci/Makefile.am,
	sci/console.c, sci/sh4uart.c, sci/.cvsignore, score/Makefile.am,
	score/cpu_asm.c, score/ispsh7750.c, score/.cvsignore,
	timer/Makefile.am, timer/timer.c, timer/.cvsignore, configure.ac,
	.cvsignore, ChangeLog:  New files.
	Reviewed and updated to latest automake and autoconf standards
	by Ralf Corsepius <corsepiu@faw.uni-ulm.de>.

4 files changed, 696 insertions, 0 deletions

diff --git a/c/src/lib/libcpu/sh/sh7750/score/.cvsignore b/c/src/lib/libcpu/sh/sh7750/score/.cvsignore
new file mode 100644
index 0000000000..282522db03
--- /dev/null
+++ b/c/src/lib/libcpu/sh/sh7750/score/.cvsignore
@@ -0,0 +1,2 @@
+Makefile
+Makefile.in
diff --git a/c/src/lib/libcpu/sh/sh7750/score/Makefile.am b/c/src/lib/libcpu/sh/sh7750/score/Makefile.am
new file mode 100644
index 0000000000..06b4cad533
--- /dev/null
+++ b/c/src/lib/libcpu/sh/sh7750/score/Makefile.am
@@ -0,0 +1,31 @@
+##
+## $Id$
+##
+
+AUTOMAKE_OPTIONS = foreign 1.4
+
+PGM = $(ARCH)/score.rel
+
+C_FILES = cpu_asm.c ispsh7750.c
+C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
+
+OBJS = $(C_O_FILES)
+
+include $(top_srcdir)/../../../../../../make/custom/@RTEMS_BSP@.cfg
+include $(top_srcdir)/../../../../../../automake/compile.am
+include $(top_srcdir)/../../../../../../automake/lib.am
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+$(PGM): $(OBJS)
+	$(make-rel)
+
+all-local: $(ARCH) $(OBJS) $(PGM)
+
+.PRECIOUS: $(PGM)
+
+EXTRA_DIST = ispsh7750.c cpu_asm.c
+
+include $(top_srcdir)/../../../../../../automake/local.am
diff --git a/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c b/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c
new file mode 100644
index 0000000000..b4ae06861c
--- /dev/null
+++ b/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c
@@ -0,0 +1,312 @@
+/*
+ *  This file contains the basic algorithms for all assembly code used
+ *  in an specific CPU port of RTEMS.  These algorithms must be implemented
+ *  in assembly language
+ *
+ *  NOTE:  This port uses a C file with inline assembler instructions
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * 
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ */
+
+/*
+ *  This is supposed to be an assembly file.  This means that system.h
+ *  and cpu.h should not be included in a "real" cpu_asm file.  An
+ *  implementation in assembly should include "cpu_asm.h"
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/cpu.h>
+#include <rtems/score/isr.h>
+#include <rtems/score/thread.h>
+#include <rtems/score/sh.h>
+#include <rtems/score/ispsh7750.h>
+#include <rtems/score/iosh7750.h>
+#include <rtems/score/sh4_regs.h>
+#include <rtems/score/sh_io.h>
+
+/* from cpu_isps.c */
+extern proc_ptr         _Hardware_isr_Table[];
+
+#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+  unsigned long    *_old_stack_ptr;
+#endif
+
+register unsigned long  *stack_ptr asm("r15"); 
+
+/*
+ *  _CPU_Context_save_fp_context
+ *
+ *  This routine is responsible for saving the FP context
+ *  at *fp_context_ptr.  If the point to load the FP context
+ *  from is changed then the pointer is modified by this routine.
+ *
+ *  Sometimes a macro implementation of this is in cpu.h which dereferences
+ *  the ** and a similarly named routine in this file is passed something
+ *  like a (Context_Control_fp *).  The general rule on making this decision
+ *  is to avoid writing assembly language.
+ */
+
+void _CPU_Context_save_fp(
+  void **fp_context_ptr     /* r4 */
+)
+{
+#if SH_HAS_FPU
+ 
+asm volatile("
+    mov.l   @%0,r4    
+    add     %1,r4
+    sts.l   fpscr,@-r4
+    sts.l   fpul,@-r4
+    lds     %2,fpscr
+    fmov    dr14,@-r4
+    fmov    dr12,@-r4
+    fmov    dr10,@-r4
+    fmov    dr8,@-r4
+    fmov    dr6,@-r4
+    fmov    dr4,@-r4
+    fmov    dr2,@-r4
+    fmov    dr0,@-r4
+    "
+#ifdef SH4_USE_X_REGISTERS
+    "
+    lds     %3,fpscr
+    fmov    xd14,@-r4
+    fmov    xd12,@-r4
+    fmov    xd10,@-r4
+    fmov    xd8,@-r4
+    fmov    xd6,@-r4
+    fmov    xd4,@-r4
+    fmov    xd2,@-r4
+    fmov    xd0,@-r4
+    " 
+#endif
+   "lds     %4,fpscr
+   "
+    : 
+    : "r"(fp_context_ptr), "r"(sizeof(Context_Control_fp)), 
+      "r"(SH4_FPSCR_SZ), "r"(SH4_FPSCR_PR | SH4_FPSCR_SZ), "r"(SH4_FPSCR_PR)
+    : "r4", "r0");
+
+#endif
+}
+
+/*
+ *  _CPU_Context_restore_fp_context
+ *
+ *  This routine is responsible for restoring the FP context
+ *  at *fp_context_ptr.  If the point to load the FP context
+ *  from is changed then the pointer is modified by this routine.
+ *
+ *  Sometimes a macro implementation of this is in cpu.h which dereferences
+ *  the ** and a similarly named routine in this file is passed something
+ *  like a (Context_Control_fp *).  The general rule on making this decision
+ *  is to avoid writing assembly language.
+ */
+
+void _CPU_Context_restore_fp(
+  void **fp_context_ptr     /* r4 */
+)
+{
+#if SH_HAS_FPU
+
+asm volatile("
+    mov.l   @%0,r4    
+    "
+#ifdef SH4_USE_X_REGISTERS
+    "
+    lds     %1,fpscr
+    fmov    @r4+,xd0
+    fmov    @r4+,xd2
+    fmov    @r4+,xd4
+    fmov    @r4+,xd6
+    fmov    @r4+,xd8
+    fmov    @r4+,xd10
+    fmov    @r4+,xd12
+    fmov    @r4+,xd14
+    "
+#endif
+    "
+    lds     %2,fpscr
+    fmov    @r4+,dr0
+    fmov    @r4+,dr2
+    fmov    @r4+,dr4
+    fmov    @r4+,dr6
+    fmov    @r4+,dr8
+    fmov    @r4+,dr10
+    fmov    @r4+,dr12
+    fmov    @r4+,dr14
+    lds.l   @r4+,fpul
+    lds.l   @r4+,fpscr
+    " : 
+    : "r"(fp_context_ptr), "r"(SH4_FPSCR_PR | SH4_FPSCR_SZ), "r"(SH4_FPSCR_SZ)
+    : "r4", "r0");
+
+#endif
+}
+
+/*  _CPU_Context_switch
+ *
+ *  This routine performs a normal non-FP context switch.
+ */
+
+/*  within __CPU_Context_switch:
+ *  _CPU_Context_switch
+ *  _CPU_Context_restore
+ *
+ *  This routine is generally used only to restart self in an
+ *  efficient manner.  It may simply be a label in _CPU_Context_switch.
+ *
+ * NOTE: It should be safe not to store r4, r5
+ *
+ * NOTE: It is doubtful if r0 is really needed to be stored
+ *
+ * NOTE: gbr is added, but should not be necessary, as it is
+ *	only used globally in this port.
+ */
+
+/*
+ * FIXME: This is an ugly hack, but we wanted to avoid recalculating 
+ *        the offset each time Context_Control is changed
+ */
+void __CPU_Context_switch(
+  Context_Control  *run,	/* r4 */
+  Context_Control  *heir	/* r5 */
+)
+{
+
+asm volatile("
+	.global __CPU_Context_switch
+__CPU_Context_switch:
+
+	add	%0,r4
+  
+	stc.l   sr,@-r4
+	stc.l	gbr,@-r4
+	mov.l   r0,@-r4
+	mov.l   r1,@-r4
+	mov.l   r2,@-r4
+	mov.l   r3,@-r4
+
+	mov.l   r6,@-r4
+	mov.l   r7,@-r4
+	mov.l	r8,@-r4
+	mov.l	r9,@-r4
+	mov.l	r10,@-r4
+	mov.l	r11,@-r4
+	mov.l	r12,@-r4
+	mov.l	r13,@-r4
+	mov.l   r14,@-r4
+	sts.l   pr,@-r4
+	sts.l   mach,@-r4
+	sts.l   macl,@-r4
+	mov.l   r15,@-r4
+
+	mov     r5, r4"
+  :: "I" (sizeof(Context_Control))
+  );
+
+  asm volatile("
+	.global __CPU_Context_restore
+__CPU_Context_restore:
+	mov.l   @r4+,r15
+	lds.l   @r4+,macl
+	lds.l   @r4+,mach
+	lds.l   @r4+,pr
+	mov.l   @r4+,r14
+	mov.l   @r4+,r13
+	mov.l   @r4+,r12
+	mov.l   @r4+,r11
+	mov.l   @r4+,r10
+	mov.l   @r4+,r9
+	mov.l   @r4+,r8
+	mov.l   @r4+,r7
+	mov.l   @r4+,r6
+
+	mov.l   @r4+,r3
+	mov.l   @r4+,r2
+	mov.l   @r4+,r1
+	mov.l   @r4+,r0
+	ldc.l   @r4+,gbr
+	ldc.l   @r4+,sr
+
+	rts
+	nop" );
+}
+
+/*  
+ *  This routine provides the RTEMS interrupt management.
+ */
+ 
+void __ISR_Handler( unsigned32 vector)
+{
+  register unsigned32 level;
+
+  _CPU_ISR_Disable( level );
+
+  _Thread_Dispatch_disable_level++;
+
+#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+  if( _ISR_Nest_level == 0 )
+    {
+      /* Install irq stack */
+      _old_stack_ptr = stack_ptr;
+      stack_ptr = _CPU_Interrupt_stack_high;
+    }
+
+#endif
+
+  _ISR_Nest_level++;
+
+  _CPU_ISR_Enable( level );
+
+  /* call isp */
+  if( _ISR_Vector_table[ vector])
+    (*_ISR_Vector_table[ vector ])( vector );
+
+  _CPU_ISR_Disable( level );
+
+  _ISR_Nest_level--;
+
+#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+
+  if( _ISR_Nest_level == 0 )
+    /* restore old stack pointer */
+    stack_ptr = _old_stack_ptr;  
+#endif
+
+  _Thread_Dispatch_disable_level--;
+
+  _CPU_ISR_Enable( level );
+
+  if ( _Thread_Dispatch_disable_level == 0 )
+    {
+      if(( _Context_Switch_necessary) || (! _ISR_Signals_to_thread_executing))
+	{
+	  _ISR_Signals_to_thread_executing = FALSE;
+	  _Thread_Dispatch();
+	}
+  }
+}
diff --git a/c/src/lib/libcpu/sh/sh7750/score/ispsh7750.c b/c/src/lib/libcpu/sh/sh7750/score/ispsh7750.c
new file mode 100644
index 0000000000..e8b08dbbe9
--- /dev/null
+++ b/c/src/lib/libcpu/sh/sh7750/score/ispsh7750.c
@@ -0,0 +1,351 @@
+/*
+ * SH7750 interrupt support.
+ *
+ * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
+ * Author: Victor V. Vengerov <vvv@oktet.ru>
+ *
+ *  Based on work:
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
+ * 
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *	Modified to reflect isp entries for sh7045 processor:
+ *	John M. Mills (jmills@tga.com)
+ *	TGA Technologies, Inc.
+ *      100 Pinnacle Way, Suite 140
+ *	Norcross, GA 30071 U.S.A.
+ *	August, 1999
+ *
+ *	This modified file may be copied and distributed in accordance
+ *	the above-referenced license. It is provided for critique and
+ *	developmental purposes without any warranty nor representation
+ *	by the authors or by TGA Technologies.
+ *
+ *  $Id$
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/shtypes.h>
+#include <rtems/score/isr.h>
+
+#if !defined (sh7750)
+#error Wrong CPU MODEL
+#endif
+
+/*
+ * This is a exception vector table
+ *
+ * It has the same structure as the actual vector table (vectab)
+ */
+
+
+#include <rtems/score/ispsh7750.h>
+#include <rtems/score/sh7750_regs.h>
+
+/* VBR register contents saved on startup -- used to hook exception by debug
+ * agent */
+void *_VBR_Saved;
+
+/*PAGE
+ *
+ *  _CPU_ISR_install_vector
+ *
+ *  This kernel routine installs the RTEMS handler for the
+ *  specified vector.
+ *
+ *  Input parameters:
+ *    vector      - interrupt vector number
+ *    old_handler - former ISR for this vector number
+ *    new_handler - replacement ISR for this vector number
+ *
+ *  Output parameters:  NONE
+ *
+ */
+void _CPU_ISR_install_vector(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+   *old_handler = _ISR_Vector_table[vector];
+   _ISR_Vector_table[vector] = new_handler;
+}
+
+
+#define __STRINGIFY1__(x) #x
+#define __STRINGIFY__(x) __STRINGIFY1__(x)
+
+#define STOP_TIMER \
+     "        mov.l TSTR_k,r0      \n"                             \
+     "        mov.b @r0,r1         \n"                             \
+     "        and   #" __STRINGIFY__(~SH7750_TSTR_STR0) ",r1\n"    \
+     "        mov.b r1,@r0         \n"
+
+#define START_TIMER \
+     "        mov.l TSTR_k,r0      \n"                             \
+     "        mov.b @r0,r1         \n"                             \
+     "        or    #" __STRINGIFY__(SH7750_TSTR_STR0) ",r1\n"     \
+     "        mov.b r1,@r0         \n"
+
+asm ("        .text\n"
+     "        .balign 256\n"
+     "        .global __vbr_base\n"
+     "__vbr_base:\n"
+     "        .org __vbr_base + 0x100\n"
+     "vbr_100:\n"
+     "        mov.l  r0,@-r15\n"
+     "        mov.l  r1,@-r15\n"
+     "        mov.l  __VBR_Saved100_k, r0\n"
+     "        mov.l  offset100_k,r1\n"
+     "        mov.l  @r0,r0\n"
+     "        add    r1,r0\n"
+     "        mov.l  @r15+,r1\n"
+     "        jmp    @r0\n"
+     "        mov.l  @r15+,r0\n"
+     "        .align 2\n"
+     "__VBR_Saved100_k:\n"
+     "        .long __VBR_Saved\n"
+     "offset100_k:\n"
+     "        .long  0x100\n"
+     
+     "        .org __vbr_base + 0x400\n"
+     "vbr_400:\n"
+     "        mov.l  r0,@-r15\n"
+     "        mov.l  r1,@-r15\n"
+     "        mov.l  __VBR_Saved400_k, r0\n"
+     "        mov.l  offset400_k,r1\n"
+     "        mov.l  @r0,r0\n"
+     "        add    r1,r0\n"
+     "        mov.l  @r15+,r1\n"
+     "        jmp    @r0\n"
+     "        mov.l  @r15+,r0\n"
+     "        .align 2\n"
+     "__VBR_Saved400_k:\n"
+     "        .long __VBR_Saved\n"
+     "offset400_k:\n"
+     "        .long  0x400\n"
+
+     "        .org __vbr_base + 0x600\n"
+     "vbr_600:\n"
+     "    mov.l r0,@-r15   \n"
+     "    mov.l r1,@-r15   \n"
+     "    stc   sr,r0      \n"
+     "    mov.l __vbr_600_sr_and_k,r1\n"
+     "    and   r1,r0      \n"
+     "    mov.l __vbr_600_sr_or_k,r1\n"
+     "    or    r1,r0      \n"
+     "    ldc   r0,sr      \n"
+     "    ldc.l @r15+,r1_bank\n"
+     "    ldc.l @r15+,r0_bank\n"
+     "    mov.l r0,@-r15   \n"
+     "    mov.l r1,@-r15   \n"
+     "    mov.l r2,@-r15   \n"
+     "    mov.l r3,@-r15   \n"
+     "    mov.l r4,@-r15   \n"
+     "    mov.l r5,@-r15   \n"
+     "    mov.l r6,@-r15   \n"
+     "    mov.l r7,@-r15   \n"
+#if 0     
+     "    mov.l r8,@-r15   \n"
+     "    mov.l r9,@-r15   \n"
+     "    mov.l r10,@-r15  \n"
+     "    mov.l r11,@-r15  \n"
+     "    mov.l r12,@-r15  \n"
+     "    mov.l r13,@-r15  \n"
+#endif
+     "    mov.l r14,@-r15  \n"
+     "    sts.l fpscr,@-r15\n"
+     "    sts.l fpul,@-r15 \n"
+     "    mov.l __ISR_temp_fpscr_k,r0   \n"
+     "    lds   r0,fpscr   \n"
+     "    fmov  fr0,@-r15  \n"
+     "    fmov  fr1,@-r15  \n"
+     "    fmov  fr2,@-r15  \n"
+     "    fmov  fr3,@-r15  \n"
+     "    fmov  fr4,@-r15  \n"
+     "    fmov  fr5,@-r15  \n"
+     "    fmov  fr6,@-r15  \n"
+     "    fmov  fr7,@-r15  \n"
+     "    fmov  fr8,@-r15  \n"
+     "    fmov  fr9,@-r15  \n"
+     "    fmov  fr10,@-r15 \n"
+     "    fmov  fr11,@-r15 \n"
+     "    fmov  fr12,@-r15 \n"
+     "    fmov  fr13,@-r15 \n"
+     "    fmov  fr14,@-r15 \n"
+     "    fmov  fr15,@-r15 \n"
+      
+     "    sts.l pr,@-r15   \n"
+     "    sts.l mach,@-r15 \n"
+     "    sts.l macl,@-r15 \n"
+     "    stc.l spc,@-r15  \n"
+     "    stc.l ssr,@-r15  \n"
+     "    mov r15,r14      \n"
+#if 0
+     "    stc   ssr,r0     \n"
+     "    ldc   r0,sr      \n"
+#endif
+     "    mov.l __ISR_Handler_k, r1\n"
+     "    mov.l _INTEVT_k,r4\n"
+     "    mov.l @r4,r4     \n"
+     "    shlr2 r4         \n"
+     "    shlr  r4         \n"
+     
+     "    mov.l _ISR_Table_k,r0\n"
+     "    mov.l @r0,r0     \n"
+     "    add   r4,r0      \n"
+     "    mov.l @r0,r0     \n"
+     "    cmp/eq #0,r0     \n"
+     "    bt    _ipl_hook  \n"
+
+
+     "    jsr @r1          \n"
+     "     shlr2 r4        \n"
+     "    mov   r14,r15    \n"
+     "    ldc.l @r15+,ssr  \n"
+     "    ldc.l @r15+,spc  \n"
+     "    lds.l @r15+,macl \n"
+     "    lds.l @r15+,mach \n"
+     "    lds.l @r15+,pr   \n"
+     "    mov.l __ISR_temp_fpscr_k,r0   \n"
+     "    lds   r0,fpscr   \n"
+
+     "    fmov  @r15+,fr15 \n"
+     "    fmov  @r15+,fr14 \n"
+     "    fmov  @r15+,fr13 \n"
+     "    fmov  @r15+,fr12 \n"
+     "    fmov  @r15+,fr11 \n"
+     "    fmov  @r15+,fr10 \n"
+     "    fmov  @r15+,fr9  \n"
+     "    fmov  @r15+,fr8  \n"
+     "    fmov  @r15+,fr7  \n"
+     "    fmov  @r15+,fr6  \n"
+     "    fmov  @r15+,fr5  \n"
+     "    fmov  @r15+,fr4  \n"
+     "    fmov  @r15+,fr3  \n"
+     "    fmov  @r15+,fr2  \n"
+     "    fmov  @r15+,fr1  \n"
+     "    fmov  @r15+,fr0  \n"
+     "    lds.l @r15+,fpul \n"
+     "    lds.l @r15+,fpscr\n"
+     "    mov.l @r15+,r14  \n"
+#if 0
+     "    mov.l @r15+,r13  \n"
+     "    mov.l @r15+,r12  \n"
+     "    mov.l @r15+,r11  \n"
+     "    mov.l @r15+,r10  \n"
+     "    mov.l @r15+,r9   \n"
+     "    mov.l @r15+,r8   \n"
+#endif
+     
+     "    mov.l @r15+,r7   \n"
+     "    mov.l @r15+,r6   \n"
+     "    mov.l @r15+,r5   \n"
+     "    mov.l @r15+,r4   \n"
+     "    mov.l @r15+,r3   \n"
+     "    mov.l @r15+,r2   \n"
+     "    mov.l @r15+,r1   \n"
+     "    mov.l @r15+,r0   \n"
+     "    rte              \n"
+     "    nop              \n"
+     "    .align 2         \n"
+     "__vbr_600_sr_and_k:    \n"
+     "    .long " __STRINGIFY__(~(SH4_SR_RB | SH4_SR_BL)) "\n"
+     "__vbr_600_sr_or_k:     \n"
+     "    .long " __STRINGIFY__(SH4_SR_IMASK) "\n"
+     "__ISR_Handler_k:     \n"
+     "    .long ___ISR_Handler\n"
+     "_INTEVT_k:           \n"
+     "    .long " __STRINGIFY__(SH7750_INTEVT) "\n"
+     "_ISR_Table_k:        \n"
+     "    .long   __ISR_Vector_table\n"
+
+     "_ipl_hook:           \n"
+     "    mov   r14,r15    \n"
+     "    ldc.l @r15+,ssr  \n"
+     "    ldc.l @r15+,spc  \n"
+     "    lds.l @r15+,macl \n"
+     "    lds.l @r15+,mach \n"
+     "    lds.l @r15+,pr   \n"
+     "    mov.l __ISR_temp_fpscr_k,r0   \n"
+     "    lds   r0,fpscr   \n"
+     "    fmov  @r15+,fr15 \n"
+     "    fmov  @r15+,fr14 \n"
+     "    fmov  @r15+,fr13 \n"
+     "    fmov  @r15+,fr12 \n"
+     "    fmov  @r15+,fr11 \n"
+     "    fmov  @r15+,fr10 \n"
+     "    fmov  @r15+,fr9  \n"
+     "    fmov  @r15+,fr8  \n"
+     "    fmov  @r15+,fr7  \n"
+     "    fmov  @r15+,fr6  \n"
+     "    fmov  @r15+,fr5  \n"
+     "    fmov  @r15+,fr4  \n"
+     "    fmov  @r15+,fr3  \n"
+     "    fmov  @r15+,fr2  \n"
+     "    fmov  @r15+,fr1  \n"
+     "    fmov  @r15+,fr0  \n"
+     "    lds.l @r15+,fpul \n"
+     "    lds.l @r15+,fpscr\n"
+     "    mov.l @r15+,r14  \n"
+     
+     "    mov.l @r15+,r13  \n"
+     "    mov.l @r15+,r12  \n"
+     "    mov.l @r15+,r11  \n"
+     "    mov.l @r15+,r10  \n"
+     "    mov.l @r15+,r9   \n"
+     "    mov.l @r15+,r8   \n"
+     
+     
+     "    mov.l @r15+,r7   \n"
+     "    mov.l @r15+,r6   \n"
+     "    mov.l @r15+,r5   \n"
+     "    mov.l @r15+,r4   \n"
+     "    mov.l @r15+,r3   \n"
+     "    mov.l @r15+,r2   \n"
+     "    mov.l  __VBR_Saved600_k, r0\n"
+     "    mov.l  offset600_k,r1\n"
+     "    mov.l  @r0,r0\n"
+     "    add    r1,r0\n"
+     "    mov.l  @r15+,r1\n"
+     "    jmp    @r0\n"
+     "    mov.l  @r15+,r0\n"
+     "    .align 2\n"
+     "__ISR_temp_fpscr_k:  \n"
+     "    .long  " __STRINGIFY__(SH4_FPSCR_PR) " \n"
+     "__VBR_Saved600_k:\n"
+     "        .long __VBR_Saved\n"
+     "offset600_k:\n"
+     "        .long  0x600\n"
+
+ );
+     
+
+/************************************************
+ * Dummy interrupt service procedure for 
+ * interrupts being not allowed --> Trap 2
+ ************************************************/
+asm(" .section .text
+.global __dummy_isp
+__dummy_isp:
+      mov.l r14,@-r15
+      mov   r15, r14
+      trapa #2
+      mov.l @r15+,r14
+      rte
+      nop");
+