bsp/gensh1: Move libcpu files to BSP

Update #3254.

11 files changed, 0 insertions, 1998 deletions

diff --git a/c/src/lib/libcpu/sh/sh7032/clock/ckinit.c b/c/src/lib/libcpu/sh/sh7032/clock/ckinit.c
deleted file mode 100644
index 6faaf27f58..0000000000
--- a/c/src/lib/libcpu/sh/sh7032/clock/ckinit.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- *  This file contains the clock driver the Hitachi SH 703X
- */
-
-/*
- *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
- *           Bernd Becker (becker@faw.uni-ulm.de)
- *
- *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- *  COPYRIGHT (c) 1998.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#include <rtems.h>
-
-#include <stdlib.h>
-
-#include <rtems/clockdrv.h>
-#include <rtems/score/sh_io.h>
-#include <rtems/score/sh.h>
-#include <rtems/score/ispsh7032.h>
-#include <rtems/score/iosh7032.h>
-
-extern uint32_t bsp_clicks_per_second;
-
-#ifndef CLOCKPRIO
-#define CLOCKPRIO 10
-#endif
-
-#define I_CLK_PHI_1	0
-#define I_CLK_PHI_2	1
-#define I_CLK_PHI_4	2
-#define I_CLK_PHI_8	3
-
-/*
- * Set I_CLK_PHI to one of the I_CLK_PHI_X values from above to choose
- * a PHI/X clock rate.
- */
-
-#define I_CLK_PHI 	I_CLK_PHI_4
-#define CLOCK_SCALE	(1<<I_CLK_PHI)
-
-#define ITU0_STARTMASK 	0xfe
-#define ITU0_SYNCMASK 	0xfe
-#define ITU0_MODEMASK 	0xfe
-#define ITU0_TCRMASK 	(0x20 | I_CLK_PHI)
-#define ITU_STAT_MASK 	0xf8
-#define ITU0_IRQMASK 	0xfe
-#define ITU0_TIERMASK 	0x01
-#define IPRC_ITU0_MASK 	0xff0f
-#define ITU0_TIORVAL 	0x08
-
-/*
- * clicks_per_tick := clicks_per_sec * usec_per_tick
- *
- * This is a very expensive function ;-)
- *
- * Below are two variants:
- * 1. A variant applying integer arithmetics, only.
- * 2. A variant applying floating point arithmetics
- *
- * The floating point variant pulls in the fmath routines when linking,
- * resulting in slightly larger executables for applications that do not
- * apply fmath otherwise. However, the imath variant is significantly slower
- * than the fmath variant and more complex.
- *
- * Assuming that most applications will not use fmath, but are critical
- * in memory size constraints, we apply the integer variant.
- *
- * To the sake of simplicity, we might abandon one of both variants in
- * future.
- */
-static unsigned int sh_clicks_per_tick(
-  unsigned int clicks_per_sec,
-  unsigned int usec_per_tick
-)
-{
-#if 1
-  unsigned int clicks_per_tick = 0 ;
-
-  unsigned int b = clicks_per_sec ;
-  unsigned int c = 1000000 ;
-  unsigned int d = 1 ;
-  unsigned int a = ( ( b / c ) * usec_per_tick ) / d;
-
-  clicks_per_tick += a ;
-
-  while ( ( b %= c ) > 0 )
-  {
-    c /= 10 ;
-    d *= 10 ;
-    a = ( ( b / c ) * usec_per_tick ) / d ;
-    clicks_per_tick += a ;
-  }
-  return clicks_per_tick ;
-#else
-  double fclicks_per_tick =
-    ((double) clicks_per_sec * (double) usec_per_tick) / 1000000.0 ;
-  return (uint32_t) fclicks_per_tick ;
-#endif
-}
-
-/*
- *  The interrupt vector number associated with the clock tick device
- *  driver.
- */
-
-#define CLOCK_VECTOR IMIA0_ISP_V
-
-/*
- *  Clock_driver_ticks is a monotonically increasing counter of the
- *  number of clock ticks since the driver was initialized.
- */
-
-volatile uint32_t   Clock_driver_ticks;
-
-void Clock_exit( void );
-static rtems_isr Clock_isr( rtems_vector_number vector );
-
-/*
- *  Clock_isrs is the number of clock ISRs until the next invocation of
- *  the RTEMS clock tick routine.  The clock tick device driver
- *  gets an interrupt once a millisecond and counts down until the
- *  length of time between the user configured microseconds per tick
- *  has passed.
- */
-
-uint32_t   Clock_isrs;              /* ISRs until next tick */
-static uint32_t   Clock_isrs_const;        /* only calculated once */
-
-/*
- *  The previous ISR on this clock tick interrupt vector.
- */
-rtems_isr_entry  Old_ticker;
-
-/*
- *  Isr Handler
- */
-static rtems_isr Clock_isr(
-  rtems_vector_number vector
-)
-{
-  /*
-   * bump the number of clock driver ticks since initialization
-   *
-   * determine if it is time to announce the passing of tick as configured
-   * to RTEMS through the rtems_clock_tick directive
-   *
-   * perform any timer dependent tasks
-   */
-  uint8_t   temp;
-
-  /* reset the flags of the status register */
-  temp = read8( ITU_TSR0) & ITU_STAT_MASK;
-  write8( temp, ITU_TSR0);
-
-  Clock_driver_ticks++ ;
-
-  if( Clock_isrs == 1)
-    {
-      rtems_clock_tick();
-      Clock_isrs = Clock_isrs_const;
-    }
-  else
-    {
-      Clock_isrs-- ;
-    }
-}
-
-/*
- *  Install_clock
- *
- *  Install a clock tick handler and reprograms the chip.  This
- *  is used to initially establish the clock tick.
- */
-static void Install_clock(
-  rtems_isr_entry clock_isr
-)
-{
-  uint8_t   temp8 = 0;
-  uint32_t   microseconds_per_tick;
-  uint32_t   cclicks_per_tick;
-  uint16_t   Clock_limit;
-
-  /*
-   *  Initialize the clock tick device driver variables
-   */
-
-  Clock_driver_ticks = 0;
-
-  if ( rtems_configuration_get_microseconds_per_tick() != 0 )
-    microseconds_per_tick = rtems_configuration_get_microseconds_per_tick() ;
-  else
-    microseconds_per_tick = 10000 ; /* 10000 us */
-
-  /* clock clicks per tick */
-  cclicks_per_tick = sh_clicks_per_tick(
-     bsp_clicks_per_second / CLOCK_SCALE, microseconds_per_tick );
-
-  Clock_isrs_const = cclicks_per_tick >> 16 ;
-  if ( ( cclicks_per_tick | 0xffff ) > 0 )
-    Clock_isrs_const++ ;
-  Clock_limit = cclicks_per_tick / Clock_isrs_const ;
-  Clock_isrs = Clock_isrs_const;
-
-  rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker );
-  /*
-   *  Hardware specific initialize goes here
-   */
-
-  /* stop Timer 0 */
-  temp8 = read8( ITU_TSTR) & ITU0_STARTMASK;
-  write8( temp8, ITU_TSTR);
-
-  /* set initial counter value to 0 */
-  write16( 0, ITU_TCNT0);
-
-  /* Timer 0 runs independent */
-  temp8 = read8( ITU_TSNC) & ITU0_SYNCMASK;
-  write8( temp8, ITU_TSNC);
-
-  /* Timer 0 normal mode */
-  temp8 = read8( ITU_TMDR) & ITU0_MODEMASK;
-  write8( temp8, ITU_TMDR);
-
-  /* TCNT is cleared by GRA ; internal clock /4 */
-  write8( ITU0_TCRMASK , ITU_TCR0);
-
-  /* use GRA without I/O - pins  */
-  write8( ITU0_TIORVAL, ITU_TIOR0);
-
-  /* reset flags of the status register */
-  temp8 = read8( ITU_TSR0) & ITU_STAT_MASK;
-  write8( temp8, ITU_TSR0);
-
-  /* Irq if is equal GRA */
-  temp8 = read8( ITU_TIER0) | ITU0_TIERMASK;
-  write8( temp8, ITU_TIER0);
-
-  /* set interrupt priority */
-  if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL)
-    rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
-
-  /* set counter limits */
-  write16( Clock_limit, ITU_GRA0);
-
-  /* start counter */
-  temp8 = read8( ITU_TSTR) |~ITU0_STARTMASK;
-  write8( temp8, ITU_TSTR);
-
-  /*
-   *  Schedule the clock cleanup routine to execute if the application exits.
-   */
-
-  atexit( Clock_exit );
-}
-
-/*
- *  Clean up before the application exits
- */
-void Clock_exit( void )
-{
-  uint8_t   temp8 = 0;
-
-  /* turn off the timer interrupts */
-  /* set interrupt priority to 0 */
-  if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL)
-    rtems_fatal_error_occurred( RTEMS_UNSATISFIED);
-
-/*
- *   temp16 = read16( ITU_TIER0) & IPRC_ITU0_IRQMASK;
- *   write16( temp16, ITU_TIER0);
- */
-
-  /* stop counter */
-  temp8 = read8( ITU_TSTR) & ITU0_STARTMASK;
-  write8( temp8, ITU_TSTR);
-
-  /* old vector shall not be installed */
-}
-
-/*
- *  Clock_initialize
- *
- *  Device driver entry point for clock tick driver initialization.
- */
-
-rtems_device_driver Clock_initialize(
-  rtems_device_major_number major,
-  rtems_device_minor_number minor,
-  void *pargp
-)
-{
-  Install_clock( Clock_isr );
-
-  return RTEMS_SUCCESSFUL;
-}
diff --git a/c/src/lib/libcpu/sh/sh7032/delay/delay.c b/c/src/lib/libcpu/sh/sh7032/delay/delay.c
deleted file mode 100644
index 085771f777..0000000000
--- a/c/src/lib/libcpu/sh/sh7032/delay/delay.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- *  This routine is a simple spin delay
- *
- *  Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
- *
- *  COPYRIGHT (c) 1999, Ralf Corsepius, Ulm, Germany
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- *  COPYRIGHT (c) 1989-1999.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-
-#include <rtems.h>
-
-extern uint32_t bsp_clicks_per_second;
-
-/*
- *  Simple spin delay in microsecond units for device drivers.
- *  This is very dependent on the clock speed of the target.
- *
- *  Since we don't have a real time clock, this is a very rough
- *  approximation, assuming that each cycle of the delay loop takes
- *  approx. 4 machine cycles.
- *
- *  e.g.: clicks_per_second = 20MHz
- *        => 5e-8 secs per instruction
- *        => 4 * 5e-8 secs per delay loop
- */
-
-void CPU_delay( uint32_t   microseconds )
-{
-  register uint32_t   clicks_per_usec = bsp_clicks_per_second / 1000000;
-  register uint32_t   _delay = (microseconds) * (clicks_per_usec);
-
-  __asm__ volatile (
-"0:	add  #-4,%0\n\
-	nop\n\
-	cmp/pl %0\n\
-	bt 0b\n\
-	nop"
-     :: "r" (_delay) );
-}
diff --git a/c/src/lib/libcpu/sh/sh7032/include/iosh7032.h b/c/src/lib/libcpu/sh/sh7032/include/iosh7032.h
deleted file mode 100644
index 3750024a64..0000000000
--- a/c/src/lib/libcpu/sh/sh7032/include/iosh7032.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- *  This include file contains information pertaining to the Hitachi SH
- *  processor.
- *
- *  NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
- *
- *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
- *           Bernd Becker (becker@faw.uni-ulm.de)
- *
- *  Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
- *  contained no copyright notice.
- *
- *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- *  COPYRIGHT (c) 1998.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef __IOSH7030_H
-#define __IOSH7030_H
-
-/*
- * After each line is explained whether the access is char short or long.
- * The functions read/writeb, w, l, 8, 16, 32 can be found
- * in exec/score/cpu/sh/sh_io.h
- *
- * 8 bit  == char     ( readb, writeb, read8, write8)
- * 16 bit == short    ( readw, writew, read16, write16 )
- * 32 bit == long     ( readl, writel, read32, write32 )
- */
-
-#define SCI0_SMR 	0x05fffec0 /* char  */
-#define SCI0_BRR 	0x05fffec1 /* char  */
-#define SCI0_SCR 	0x05fffec2 /* char  */
-#define SCI0_TDR 	0x05fffec3 /* char  */
-#define SCI0_SSR 	0x05fffec4 /* char  */
-#define SCI0_RDR 	0x05fffec5 /* char  */
-
-#define SCI1_SMR 	0x05fffec8 /* char  */
-#define SCI1_BRR 	0x05fffec9 /* char  */
-#define SCI1_SCR 	0x05fffeca /* char  */
-#define SCI1_TDR 	0x05fffecb /* char  */
-#define SCI1_SSR 	0x05fffecc /* char  */
-#define SCI1_RDR 	0x05fffecd /* char  */
-
-
-#define ADDRAH 		0x05fffee0 /* char  */
-#define ADDRAL 		0x05fffee1 /* char  */
-#define ADDRBH 		0x05fffee2 /* char  */
-#define ADDRBL 		0x05fffee3 /* char  */
-#define ADDRCH 		0x05fffee4 /* char  */
-#define ADDRCL 		0x05fffee5 /* char  */
-#define ADDRDH 		0x05fffee6 /* char  */
-#define ADDRDL 		0x05fffee7 /* char  */
-#define AD_DRA 		0x05fffee0 /* short */
-#define AD_DRB 		0x05fffee2 /* short */
-#define AD_DRC 		0x05fffee4 /* short */
-#define AD_DRD 		0x05fffee6 /* short */
-#define ADCSR  		0x05fffee8 /* char  */
-#define ADCR   		0x05fffee9 /* char  */
-
-/*ITU SHARED*/
-#define ITU_TSTR  	0x05ffff00 /* char  */
-#define ITU_TSNC  	0x05ffff01 /* char  */
-#define ITU_TMDR  	0x05ffff02 /* char  */
-#define ITU_TFCR  	0x05ffff03 /* char  */
-
-/*ITU CHANNEL 0*/
-#define ITU_TCR0  	0x05ffff04 /* char  */
-#define ITU_TIOR0 	0x05ffff05 /* char  */
-#define ITU_TIER0 	0x05ffff06 /* char  */
-#define ITU_TSR0  	0x05ffff07 /* char  */
-#define ITU_TCNT0 	0x05ffff08 /* short */
-#define ITU_GRA0  	0x05ffff0a /* short */
-#define ITU_GRB0  	0x05ffff0c /* short */
-
- /*ITU CHANNEL 1*/
-#define ITU_TCR1  	0x05ffff0E /* char  */
-#define ITU_TIOR1 	0x05ffff0F /* char  */
-#define ITU_TIER1 	0x05ffff10 /* char  */
-#define ITU_TSR1  	0x05ffff11 /* char  */
-#define ITU_TCNT1 	0x05ffff12 /* short */
-#define ITU_GRA1  	0x05ffff14 /* short */
-#define ITU_GRB1  	0x05ffff16 /* short */
-
-
- /*ITU CHANNEL 2*/
-#define ITU_TCR2  	0x05ffff18 /* char  */
-#define ITU_TIOR2 	0x05ffff19 /* char  */
-#define ITU_TIER2 	0x05ffff1A /* char  */
-#define ITU_TSR2  	0x05ffff1B /* char  */
-#define ITU_TCNT2 	0x05ffff1C /* short */
-#define ITU_GRA2  	0x05ffff1E /* short */
-#define ITU_GRB2  	0x05ffff20 /* short */
-
- /*ITU CHANNEL 3*/
-#define ITU_TCR3  	0x05ffff22 /* char  */
-#define ITU_TIOR3 	0x05ffff23 /* char  */
-#define ITU_TIER3 	0x05ffff24 /* char  */
-#define ITU_TSR3  	0x05ffff25 /* char  */
-#define ITU_TCNT3 	0x05ffff26 /* short */
-#define ITU_GRA3  	0x05ffff28 /* short */
-#define ITU_GRB3  	0x05ffff2A /* short */
-#define ITU_BRA3  	0x05ffff2C /* short */
-#define ITU_BRB3  	0x05ffff2E /* short */
-
- /*ITU CHANNELS 0-4 SHARED*/
-#define ITU_TOCR  	0x05ffff31 /* char  */
-
- /*ITU CHANNEL 4*/
-#define ITU_TCR4  	0x05ffff32 /* char  */
-#define ITU_TIOR4 	0x05ffff33 /* char  */
-#define ITU_TIER4 	0x05ffff34 /* char  */
-#define ITU_TSR4  	0x05ffff35 /* char  */
-#define ITU_TCNT4 	0x05ffff36 /* short */
-#define ITU_GRA4  	0x05ffff38 /* short */
-#define ITU_GRB4  	0x05ffff3A /* short */
-#define ITU_BRA4  	0x05ffff3C /* short */
-#define ITU_BRB4  	0x05ffff3E /* short */
-
- /*DMAC CHANNELS 0-3 SHARED*/
-#define DMAOR           0x05ffff48 /* short */
-
- /*DMAC CHANNEL 0*/
-#define DMA_SAR0        0x05ffff40 /* long  */
-#define DMA_DAR0        0x05ffff44 /* long  */
-#define DMA_TCR0        0x05ffff4a /* short */
-#define DMA_CHCR0       0x05ffff4e /* short */
-
- /*DMAC CHANNEL 1*/
-#define DMA_SAR1        0x05ffff50 /* long  */
-#define DMA_DAR1        0x05ffff54 /* long  */
-#define DMA_TCR1        0x05fffF5a /* short */
-#define DMA_CHCR1       0x05ffff5e /* short */
-
- /*DMAC CHANNEL 3*/
-#define DMA_SAR3        0x05ffff60 /* long  */
-#define DMA_DAR3        0x05ffff64 /* long  */
-#define DMA_TCR3        0x05fffF6a /* short */
-#define DMA_CHCR3       0x05ffff6e /* short */
-
-/*DMAC CHANNEL 4*/
-#define DMA_SAR4        0x05ffff70 /* long  */
-#define DMA_DAR4        0x05ffff74 /* long  */
-#define DMA_TCR4        0x05fffF7a /* short */
-#define DMA_CHCR4       0x05ffff7e /* short */
-
-/*INTC*/
-#define INTC_IPRA 	0x05ffff84 /* short */
-#define INTC_IPRB 	0x05ffff86 /* short */
-#define INTC_IPRC 	0x05ffff88 /* short */
-#define INTC_IPRD 	0x05ffff8A /* short */
-#define INTC_IPRE 	0x05ffff8C /* short */
-#define INTC_ICR  	0x05ffff8E /* short */
-
-/*UBC*/
-#define UBC_BARH  	0x05ffff90 /* short */
-#define UBC_BARL  	0x05ffff92 /* short */
-#define UBC_BAMRH 	0x05ffff94 /* short */
-#define UBC_BAMRL 	0x05ffff96 /* short */
-#define UBC_BBR   	0x05ffff98 /* short */
-
-/*BSC*/
-#define BSC_BCR   	0x05ffffA0 /* short */
-#define BSC_WCR1  	0x05ffffA2 /* short */
-#define BSC_WCR2  	0x05ffffA4 /* short */
-#define BSC_WCR3  	0x05ffffA6 /* short */
-#define BSC_DCR   	0x05ffffA8 /* short */
-#define BSC_PCR   	0x05ffffAA /* short */
-#define BSC_RCR   	0x05ffffAC /* short */
-#define BSC_RTCSR 	0x05ffffAE /* short */
-#define BSC_RTCNT 	0x05ffffB0 /* short */
-#define BSC_RTCOR 	0x05ffffB2 /* short */
-
-/*WDT*/
-#define WDT_TCSR  	0x05ffffB8 /* char  */
-#define WDT_TCNT  	0x05ffffB9 /* char  */
-#define WDT_RSTCSR 	0x05ffffBB /* char  */
-
-/*POWER DOWN STATE*/
-#define PDT_SBYCR 	0x05ffffBC /* char  */
-
-/*PORT A*/
-#define PADR 		0x05ffffC0 /* short */
-
-/*PORT B*/
-#define PBDR 		0x05ffffC2 /* short */
-
- /*PORT C*/
-#define PCDR 		0x05ffffD0 /* short */
-
-/*PFC*/
-#define PFC_PAIOR 	0x05ffffC4 /* short */
-#define PFC_PBIOR 	0x05ffffC6 /* short */
-#define PFC_PACR1 	0x05ffffC8 /* short */
-#define PFC_PACR2 	0x05ffffCA /* short */
-#define PFC_PBCR1 	0x05ffffCC /* short */
-#define PFC_PBCR2 	0x05ffffCE /* short */
-#define PFC_CASCR 	0x05ffffEE /* short */
-
-/*TPC*/
-#define TPC_TPMR 	0x05ffffF0 /* short */
-#define TPC_TPCR 	0x05ffffF1 /* short */
-#define TPC_NDERH 	0x05ffffF2 /* short */
-#define TPC_NDERL 	0x05ffffF3 /* short */
-#define TPC_NDRB 	0x05ffffF4 /* char  */
-#define TPC_NDRA 	0x05ffffF5 /* char  */
-#define TPC_NDRB1 	0x05ffffF6 /* char  */
-#define TPC_NDRA1 	0x05ffffF7 /* char  */
-
-#endif
diff --git a/c/src/lib/libcpu/sh/sh7032/include/ispsh7032.h b/c/src/lib/libcpu/sh/sh7032/include/ispsh7032.h
deleted file mode 100644
index 9c7cee8bd6..0000000000
--- a/c/src/lib/libcpu/sh/sh7032/include/ispsh7032.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- *  This include file contains information pertaining to the Hitachi SH
- *  processor.
- *
- *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
- *           Bernd Becker (becker@faw.uni-ulm.de)
- *
- *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- *  COPYRIGHT (c) 1998.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef __CPU_ISPS_H
-#define __CPU_ISPS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rtems/score/types.h>
-
-extern void __ISR_Handler( uint32_t   vector );
-
-
-/*
- * interrupt vector table offsets
- */
-#define NMI_ISP_V 11
-#define USB_ISP_V 12
-#define IRQ0_ISP_V 64
-#define IRQ1_ISP_V 65
-#define IRQ2_ISP_V 66
-#define IRQ3_ISP_V 67
-#define IRQ4_ISP_V 68
-#define IRQ5_ISP_V 69
-#define IRQ6_ISP_V 70
-#define IRQ7_ISP_V 71
-#define DMA0_ISP_V 72
-#define DMA1_ISP_V 74
-#define DMA2_ISP_V 76
-#define DMA3_ISP_V 78
-
-#define IMIA0_ISP_V 80
-#define IMIB0_ISP_V 81
-#define OVI0_ISP_V 82
-
-#define IMIA1_ISP_V 84
-#define IMIB1_ISP_V 85
-#define OVI1_ISP_V 86
-
-#define IMIA2_ISP_V 88
-#define IMIB2_ISP_V 89
-#define OVI2_ISP_V 90
-
-#define IMIA3_ISP_V 92
-#define IMIB3_ISP_V 93
-#define OVI3_ISP_V 94
-
-#define IMIA4_ISP_V 96
-#define IMIB4_ISP_V 97
-#define OVI4_ISP_V 98
-
-#define ERI0_ISP_V 100
-#define RXI0_ISP_V 101
-#define TXI0_ISP_V 102
-#define TEI0_ISP_V 103
-
-#define ERI1_ISP_V 104
-#define RXI1_ISP_V 105
-#define TXI1_ISP_V 106
-#define TEI1_ISP_V 107
-
-#define PRT_ISP_V 108
-#define ADU_ISP_V 109
-#define WDT_ISP_V 112
-#define DREF_ISP_V 113
-
-
-/* dummy ISP */
-extern void _dummy_isp( void );
-
-/* Non Maskable Interrupt */
-extern void _nmi_isp( void );
-
-/* User Break Controller */
-extern void _usb_isp( void );
-
-/* External interrupts 0-7 */
-extern void _irq0_isp( void );
-extern void _irq1_isp( void );
-extern void _irq2_isp( void );
-extern void _irq3_isp( void );
-extern void _irq4_isp( void );
-extern void _irq5_isp( void );
-extern void _irq6_isp( void );
-extern void _irq7_isp( void );
-
-/* DMA - Controller */
-extern void _dma0_isp( void );
-extern void _dma1_isp( void );
-extern void _dma2_isp( void );
-extern void _dma3_isp( void );
-
-/* Interrupt Timer Unit */
-/* Timer 0 */
-extern void _imia0_isp( void );
-extern void _imib0_isp( void );
-extern void _ovi0_isp( void );
-/* Timer 1 */
-extern void _imia1_isp( void );
-extern void _imib1_isp( void );
-extern void _ovi1_isp( void );
-/* Timer 2 */
-extern void _imia2_isp( void );
-extern void _imib2_isp( void );
-extern void _ovi2_isp( void );
-/* Timer 3 */
-extern void _imia3_isp( void );
-extern void _imib3_isp( void );
-extern void _ovi3_isp( void );
-/* Timer 4 */
-extern void _imia4_isp( void );
-extern void _imib4_isp( void );
-extern void _ovi4_isp( void );
-
-/* seriell interfaces */
-extern void _eri0_isp( void );
-extern void _rxi0_isp( void );
-extern void _txi0_isp( void );
-extern void _tei0_isp( void );
-extern void _eri1_isp( void );
-extern void _rxi1_isp( void );
-extern void _txi1_isp( void );
-extern void _tei1_isp( void );
-
-/* Parity Control Unit of the Bus State Controllers */
-extern void _prt_isp( void );
-
-/* ADC */
-extern void _adu_isp( void );
-
-/* Watchdog Timer */
-extern void _wdt_isp( void );
-
-/* DRAM refresh control unit of bus state controller */
-extern void _dref_isp( void );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/c/src/lib/libcpu/sh/sh7032/include/sci.h b/c/src/lib/libcpu/sh/sh7032/include/sci.h
deleted file mode 100644
index 5653afca3c..0000000000
--- a/c/src/lib/libcpu/sh/sh7032/include/sci.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- *  Driver for the sh1 703x on-chip serial devices (sci)
- *
- *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
- *           Bernd Becker (becker@faw.uni-ulm.de)
- *
- *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- *  COPYRIGHT (c) 1998.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _sh_sci_h
-#define _sh_sci_h
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * Devices are set to 9600 bps, 8 databits, 1 stopbit, no
- * parity and asynchronous mode by default.
- *
- * NOTE:
- *       The onboard serial devices of the SH do not support hardware
- *       handshake.
- */
-
-#define DEVSCI_DRIVER_TABLE_ENTRY \
-  { sh_sci_initialize, sh_sci_open, sh_sci_close, sh_sci_read, \
-      sh_sci_write, sh_sci_control }
-
-extern rtems_device_driver sh_sci_initialize(
-  rtems_device_major_number,
-  rtems_device_minor_number,
-  void *
-);
-
-extern rtems_device_driver sh_sci_open(
-  rtems_device_major_number,
-  rtems_device_minor_number,
-  void *
-);
-
-extern rtems_device_driver sh_sci_close(
-  rtems_device_major_number,
-  rtems_device_minor_number,
-  void *
-);
-
-extern rtems_device_driver sh_sci_read(
-  rtems_device_major_number,
-  rtems_device_minor_number,
-  void *
-);
-
-extern rtems_device_driver sh_sci_write(
-  rtems_device_major_number,
-  rtems_device_minor_number,
-  void *
-);
-
-extern rtems_device_driver sh_sci_control(
-  rtems_device_major_number,
-  rtems_device_minor_number,
-  void *
-);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/c/src/lib/libcpu/sh/sh7032/include/sh7_pfc.h b/c/src/lib/libcpu/sh/sh7032/include/sh7_pfc.h
deleted file mode 100644
index 1045af6af8..0000000000
--- a/c/src/lib/libcpu/sh/sh7032/include/sh7_pfc.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Bit values for the pin function controller of the Hitachi SH703X
- *
- * From Hitachi tutorials
- *
- *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
- *           Bernd Becker (becker@faw.uni-ulm.de)
- *
- *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- *  COPYRIGHT (c) 1998.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _sh7_pfc_h
-#define _sh7_pfc_h
-
-#include <rtems/score/iosh7032.h>
-
-/*
- * Port B IO Register (PBIOR)
- */
-#define PBIOR           PFC_PBIOR
-#define PB15IOR         0x8000
-#define PB14IOR         0x4000
-#define PB13IOR         0x2000
-#define PB12IOR         0x1000
-#define PB11IOR         0x0800
-#define PB10IOR         0x0400
-#define PB9IOR          0x0200
-#define PB8IOR          0x0100
-#define PB7IOR          0x0080
-#define PB6IOR          0x0040
-#define PB5IOR          0x0020
-#define PB4IOR          0x0010
-#define PB3IOR          0x0008
-#define PB2IOR          0x0004
-#define PB1IOR          0x0002
-#define PB0IOR          0x0001
-
-/*
- * Port B Control Register (PBCR1)
- */
-#define PBCR1           PFC_PBCR1
-#define PB15MD1         0x8000
-#define PB15MD0         0x4000
-#define PB14MD1         0x2000
-#define PB14MD0         0x1000
-#define PB13MD1         0x0800
-#define PB13MD0         0x0400
-#define PB12MD1         0x0200
-#define PB12MD0         0x0100
-#define PB11MD1         0x0080
-#define PB11MD0         0x0040
-#define PB10MD1         0x0020
-#define PB10MD0         0x0010
-#define PB9MD1          0x0008
-#define PB9MD0          0x0004
-#define PB8MD1          0x0002
-#define PB8MD0          0x0001
-
-#define PB15MD          PB15MD1|PB14MD0
-#define PB14MD          PB14MD1|PB14MD0
-#define PB13MD          PB13MD1|PB13MD0
-#define PB12MD          PB12MD1|PB12MD0
-#define PB11MD          PB11MD1|PB11MD0
-#define PB10MD          PB10MD1|PB10MD0
-#define PB9MD           PB9MD1|PB9MD0
-#define PB8MD           PB8MD1|PB8MD0
-
-#define PB_TXD1         PB11MD1
-#define PB_RXD1         PB10MD1
-#define PB_TXD0         PB9MD1
-#define PB_RXD0         PB8MD1
-
-/*
- * Port B Control Register (PBCR2)
- */
-#define PBCR2   PFC_PBCR2
-#define PB7MD1  0x8000
-#define PB7MD0  0x4000
-#define PB6MD1  0x2000
-#define PB6MD0  0x1000
-#define PB5MD1  0x0800
-#define PB5MD0  0x0400
-#define PB4MD1  0x0200
-#define PB4MD0  0x0100
-#define PB3MD1  0x0080
-#define PB3MD0  0x0040
-#define PB2MD1  0x0020
-#define PB2MD0  0x0010
-#define PB1MD1  0x0008
-#define PB1MD0  0x0004
-#define PB0MD1  0x0002
-#define PB0MD0  0x0001
-
-#define PB7MD   PB7MD1|PB7MD0
-#define PB6MD   PB6MD1|PB6MD0
-#define PB5MD   PB5MD1|PB5MD0
-#define PB4MD   PB4MD1|PB4MD0
-#define PB3MD   PB3MD1|PB3MD0
-#define PB2MD   PB2MD1|PB2MD0
-#define PB1MD   PB1MD1|PB1MD0
-#define PB0MD   PB0MD1|PB0MD0
-
-#endif /* _sh7_pfc_h */
diff --git a/c/src/lib/libcpu/sh/sh7032/include/sh7_sci.h b/c/src/lib/libcpu/sh/sh7032/include/sh7_sci.h
deleted file mode 100644
index 0b80a485d3..0000000000
--- a/c/src/lib/libcpu/sh/sh7032/include/sh7_sci.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Bit values for the serial control registers of the Hitachi SH703X
- *
- * From Hitachi tutorials
- *
- *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
- *           Bernd Becker (becker@faw.uni-ulm.de)
- *
- *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- *  COPYRIGHT (c) 1998.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _sh7_sci_h
-#define _sh7_sci_h
-
-#include <rtems/score/iosh7032.h>
-
-/*
- * Serial mode register bits
- */
-
-#define SCI_SYNC_MODE               0x80
-#define SCI_SEVEN_BIT_DATA          0x40
-#define SCI_PARITY_ON               0x20
-#define SCI_ODD_PARITY              0x10
-#define SCI_STOP_BITS_2             0x08
-#define SCI_ENABLE_MULTIP           0x04
-#define SCI_PHI_64                  0x03
-#define SCI_PHI_16                  0x02
-#define SCI_PHI_4                   0x01
-#define SCI_PHI_0                   0x00
-
-/*
- * Serial register offsets, relative to SCI0_SMR or SCI1_SMR
- */
-
-#define SCI_SMR			0x00
-#define SCI_BRR			0x01
-#define SCI_SCR			0x02
-#define SCI_TDR			0x03
-#define SCI_SSR			0x04
-#define SCI_RDR			0x05
-
-/*
- * Serial control register bits
- */
-#define SCI_TIE                 0x80    /* Transmit interrupt enable */
-#define SCI_RIE                 0x40    /* Receive interrupt enable */
-#define SCI_TE                  0x20    /* Transmit enable */
-#define SCI_RE                  0x10    /* Receive enable */
-#define SCI_MPIE                0x08    /* Multiprocessor interrupt enable */
-#define SCI_TEIE                0x04    /* Transmit end interrupt enable */
-#define SCI_CKE1                0x02    /* Clock enable 1 */
-#define SCI_CKE0                0x01    /* Clock enable 0 */
-
-/*
- * Serial status register bits
- */
-#define SCI_TDRE                0x80    /* Transmit data register empty */
-#define SCI_RDRF                0x40    /* Receive data register full */
-#define SCI_ORER                0x20    /* Overrun error */
-#define SCI_FER                 0x10    /* Framing error */
-#define SCI_PER                 0x08    /* Parity error */
-#define SCI_TEND                0x04    /* Transmit end */
-#define SCI_MPB                 0x02    /* Multiprocessor bit */
-#define SCI_MPBT                0x01    /* Multiprocessor bit transfer */
-
-#endif /* _sh7_sci_h */
diff --git a/c/src/lib/libcpu/sh/sh7032/sci/sci.c b/c/src/lib/libcpu/sh/sh7032/sci/sci.c
deleted file mode 100644
index 04d9ca5c70..0000000000
--- a/c/src/lib/libcpu/sh/sh7032/sci/sci.c
+++ /dev/null
@@ -1,358 +0,0 @@
-/*
- * /dev/sci[0|1] for Hitachi SH 703X
- *
- *  Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
- *
- *  COPYRIGHT (c) 1997-1999, Ralf Corsepius, Ulm, Germany
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- *  COPYRIGHT (c) 1998.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#include <rtems.h>
-
-#include <stdlib.h>
-
-#include <rtems/libio.h>
-#include <rtems/iosupp.h>
-#include <rtems/score/sh_io.h>
-#include <rtems/score/ispsh7032.h>
-#include <rtems/score/iosh7032.h>
-#include <sh/sh7_sci.h>
-#include <sh/sh7_pfc.h>
-#include <sh/sci.h>
-
-/*
- * NOTE: Some SH variants have 3 sci devices
- */
-
-#define SCI_MINOR_DEVICES       2
-
-#define SH_SCI_BASE_0   SCI0_SMR
-#define SH_SCI_BASE_1   SCI1_SMR
-
-struct scidev_t {
-  char *			name ;
-  uint32_t  			addr ;
-  rtems_device_minor_number	minor ;
-  unsigned short		opened ;
-  tcflag_t			cflags ;
-  speed_t       spd ;
-} sci_device[SCI_MINOR_DEVICES] =
-{
-  { "/dev/sci0", SH_SCI_BASE_0, 0, 0, CS8, B9600 },
-  { "/dev/sci1", SH_SCI_BASE_1, 1, 0, CS8, B9600 }
-} ;
-
-/*  imported from scitab.rel */
-extern int _sci_get_brparms(
-  speed_t       spd,
-  unsigned char *smr,
-  unsigned char *brr );
-
-/* Translate termios' tcflag_t into sci settings */
-static int _sci_set_cflags(
-  struct scidev_t      *sci_dev,
-  tcflag_t      c_cflag,
-  speed_t       spd )
-{
-  uint8_t  	smr ;
-  uint8_t  	brr ;
-
-  if ( spd )
-  {
-    if ( _sci_get_brparms( spd, &smr, &brr ) != 0 )
-      return -1 ;
-  }
-
-  if ( c_cflag & CSIZE )
-  {
-    if ( c_cflag & CS8 )
-      smr &= ~SCI_SEVEN_BIT_DATA;
-    else if ( c_cflag & CS7 )
-      smr |= SCI_SEVEN_BIT_DATA;
-    else
-      return -1 ;
-  }
-
-  if ( c_cflag & CSTOPB )
-    smr |= SCI_STOP_BITS_2;
-  else
-    smr &= ~SCI_STOP_BITS_2;
-
-  if ( c_cflag & PARENB )
-    smr |= SCI_PARITY_ON ;
-  else
-    smr &= ~SCI_PARITY_ON ;
-
-  if ( c_cflag & PARODD )
-    smr |= SCI_ODD_PARITY ;
-  else
-    smr &= ~SCI_ODD_PARITY;
-
-  write8( smr, sci_dev->addr + SCI_SMR );
-  write8( brr, sci_dev->addr + SCI_BRR );
-
-  return 0 ;
-}
-
-static void _sci_init(
-  rtems_device_minor_number minor )
-{
-  uint16_t  	temp16 ;
-
-  /* Pin function controller initialisation for asynchronous mode */
-  if( minor == 0)
-    {
-      temp16 = read16( PFC_PBCR1);
-      temp16 &= ~( PB8MD | PB9MD );
-      temp16 |= (PB_TXD0 | PB_RXD0);
-      write16( temp16, PFC_PBCR1);
-    }
-  else
-    {
-      temp16 = read16( PFC_PBCR1);
-      temp16 &= ~( PB10MD | PB11MD);
-      temp16 |= (PB_TXD1 | PB_RXD1);
-      write16( temp16, PFC_PBCR1);
-    }
-
-  /* disable sck-pin */
-  if( minor == 0)
-  {
-	  temp16 = read16( PFC_PBCR1);
-	  temp16 &= ~(PB12MD);
-	  write16( temp16, PFC_PBCR1);
-  }
-  else
-  {
-	  temp16 = read16( PFC_PBCR1);
-	  temp16 &= ~(PB13MD);
-	  write16( temp16, PFC_PBCR1);
-  }
-}
-
-static void _sci_tx_polled(
-  int minor,
-  const char buf )
-{
-  struct scidev_t *scidev = &sci_device[minor] ;
-  int8_t           ssr ;
-
-  while ( !inb((scidev->addr + SCI_SSR) & SCI_TDRE ))
-      ;
-  write8(buf,scidev->addr+SCI_TDR);
-
-  ssr = inb(scidev->addr+SCI_SSR);
-  ssr &= ~SCI_TDRE ;
-  write8(ssr,scidev->addr+SCI_SSR);
-}
-
-static int _sci_rx_polled (
-  int minor)
-{
-  struct scidev_t *scidev = &sci_device[minor] ;
-
-  unsigned char c;
-  char ssr ;
-  ssr = read8(scidev->addr + SCI_SSR) ;
-
-  if (ssr & (SCI_PER | SCI_FER | SCI_ORER))
-    write8(ssr & ~(SCI_PER | SCI_FER | SCI_ORER), scidev->addr+SCI_SSR);
-
-  if ( !(ssr & SCI_RDRF) )
-    return -1;
-
-  c = read8(scidev->addr + SCI_RDR) ;
-
-  write8(ssr & ~SCI_RDRF,scidev->addr + SCI_SSR);
-  return c;
-}
-
-/*
- * sci_initialize
- */
-
-rtems_device_driver sh_sci_initialize(
-  rtems_device_major_number  major,
-  rtems_device_minor_number  minor,
-  void                      *arg )
-{
-  rtems_device_driver status ;
-  rtems_device_minor_number     i;
-
-  /*
-   * register all possible devices.
-   * the initialization of the hardware is done by sci_open
-   */
-
-  for ( i = 0 ; i < SCI_MINOR_DEVICES ; i++ )
-  {
-    status = rtems_io_register_name(
-      sci_device[i].name,
-      major,
-      sci_device[i].minor );
-    if (status != RTEMS_SUCCESSFUL)
-      rtems_fatal_error_occurred(status);
-  }
-
-  /* default hardware setup */
-
-  return RTEMS_SUCCESSFUL;
-}
-
-
-/*
- *  Open entry point
- */
-
-rtems_device_driver sh_sci_open(
-  rtems_device_major_number major,
-  rtems_device_minor_number minor,
-  void                    * arg )
-{
-  uint8_t   temp8;
-
- /* check for valid minor number */
-   if(( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 ))
-   {
-     return RTEMS_INVALID_NUMBER;
-   }
-
- /* device already opened */
-  if ( sci_device[minor].opened > 0 )
-  {
-    sci_device[minor].opened++ ;
-    return RTEMS_SUCCESSFUL ;
-  }
-
-  _sci_init( minor );
-
-  if (minor == 0) {
-    temp8 = read8(sci_device[minor].addr + SCI_SCR);
-    temp8 &= ~(SCI_TE | SCI_RE) ;
-    write8(temp8, sci_device[minor].addr + SCI_SCR);	/* Clear SCR */
-    _sci_set_cflags( &sci_device[minor], sci_device[minor].cflags, sci_device[minor].spd );
-
-/* FIXME: Should be one bit delay */
-    CPU_delay(50000); /* microseconds */
-
-    temp8 |= SCI_RE | SCI_TE;
-    write8(temp8, sci_device[minor].addr + SCI_SCR);	/* Enable clock output */
-  } else {
-    temp8 = read8(sci_device[minor].addr + SCI_SCR);
-    temp8 &= ~(SCI_TE | SCI_RE) ;
-    write8(temp8, sci_device[minor].addr + SCI_SCR);	/* Clear SCR */
-    _sci_set_cflags( &sci_device[minor], sci_device[minor].cflags, sci_device[minor].spd );
-
-/* FIXME: Should be one bit delay */
-    CPU_delay(50000); /* microseconds */
-
-    temp8 |= SCI_RE | SCI_TE;
-    write8(temp8, sci_device[minor].addr + SCI_SCR);	/* Enable clock output */
-  }
-
-  sci_device[minor].opened++ ;
-
-  return RTEMS_SUCCESSFUL ;
-}
-
-/*
- *  Close entry point
- */
-
-rtems_device_driver sh_sci_close(
-  rtems_device_major_number major,
-  rtems_device_minor_number minor,
-  void                    * arg
-)
-{
-  if( sci_device[minor].opened == 0 )
-    {
-      return RTEMS_INVALID_NUMBER;
-    }
-
-  sci_device[minor].opened-- ;
-
-  return RTEMS_SUCCESSFUL ;
-}
-
-/*
- * read bytes from the serial port.
- */
-
-rtems_device_driver sh_sci_read(
-  rtems_device_major_number major,
-  rtems_device_minor_number minor,
-  void                    * arg
-)
-{
-  int count = 0;
-
-  rtems_libio_rw_args_t *rw_args = (rtems_libio_rw_args_t *) arg;
-  char * buffer = rw_args->buffer;
-  int maximum = rw_args->count;
-
-  for (count = 0; count < maximum; count++) {
-    buffer[ count ] = _sci_rx_polled(minor);
-    if (buffer[ count ] == '\n' || buffer[ count ] == '\r') {
-      buffer[ count++ ]  = '\n';
-      break;
-    }
-  }
-
-  rw_args->bytes_moved = count;
-  return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED;
-}
-
-/*
- * write bytes to the serial port.
- */
-
-rtems_device_driver sh_sci_write(
-  rtems_device_major_number major,
-  rtems_device_minor_number minor,
-  void                    * arg
-)
-{
-  int count;
-
-  rtems_libio_rw_args_t *rw_args = (rtems_libio_rw_args_t *) arg;
-  char *buffer = rw_args->buffer;
-  int maximum = rw_args->count;
-
-  for (count = 0; count < maximum; count++) {
-#if 0
-    if ( buffer[ count ] == '\n') {
-      outbyte(minor, '\r');
-    }
-#endif
-    _sci_tx_polled( minor, buffer[ count ] );
-  }
-
-  rw_args->bytes_moved = maximum;
-  return 0;
-}
-
-/*
- *  IO Control entry point
- */
-
-rtems_device_driver sh_sci_control(
-  rtems_device_major_number major,
-  rtems_device_minor_number minor,
-  void                    * arg
-)
-{
-  /* Not yet supported */
-  return RTEMS_SUCCESSFUL ;
-}
diff --git a/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c b/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c
deleted file mode 100644
index 99d9cc9a6a..0000000000
--- a/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- *  This file contains the basic algorithms for all assembly code used
- *  in an specific CPU port of RTEMS.  These algorithms must be implemented
- *  in assembly language
- *
- *  NOTE:  This port uses a C file with inline assembler instructions
- *
- *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
- *           Bernd Becker (becker@faw.uni-ulm.de)
- *
- *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- *  COPYRIGHT (c) 1998.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- *
- */
-
-/*
- *  This is supposed to be an assembly file.  This means that system.h
- *  and cpu.h should not be included in a "real" cpu_asm file.  An
- *  implementation in assembly should include "cpu_asm.h"
- */
-
-#include <rtems/system.h>
-#include <rtems/score/percpu.h>
-#include <rtems/score/isr.h>
-#include <rtems/score/threaddispatch.h>
-#include <rtems/score/sh.h>
-#include <rtems/score/ispsh7032.h>
-
-#include <rtems/score/ispsh7032.h>
-#include <rtems/score/iosh7032.h>
-#include <rtems/score/sh_io.h>
-
-/* from cpu_isps.c */
-extern proc_ptr         _Hardware_isr_Table[];
-
-#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
-  unsigned long    *_old_stack_ptr;
-#endif
-
-register unsigned long  *stack_ptr __asm__ ("r15");
-
-/*
- * sh_set_irq_priority
- *
- * this function sets the interrupt level of the specified interrupt
- *
- * parameters:
- *             - irq : interrupt number
- *             - prio: priority to set for this interrupt number
- *
- * returns:    0 if ok
- *             -1 on error
- */
-
-unsigned int sh_set_irq_priority(
-  unsigned int irq,
-  unsigned int prio )
-{
-  uint32_t         shiftcount;
-  uint32_t         prioreg;
-  uint16_t         temp16;
-  ISR_Level        level;
-
-  /*
-   * first check for valid interrupt
-   */
-  if (( irq > 113) || (_Hardware_isr_Table[irq] == _dummy_isp))
-    return -1;
-  /*
-   * check for valid irq priority
-   */
-  if ( prio > 15 )
-    return -1;
-
-  /*
-   * look up appropriate interrupt priority register
-   */
-  if ( irq > 71)
-    {
-      irq = irq - 72;
-      shiftcount = 12 - ((irq & ~0x03) % 16);
-
-      switch( irq / 16)
-	{
-	case 0: { prioreg = INTC_IPRC; break;}
-	case 1: { prioreg = INTC_IPRD; break;}
-	case 2: { prioreg = INTC_IPRE; break;}
-	default: return -1;
-	}
-    }
-  else
-    {
-      shiftcount = 12 - 4 * ( irq % 4);
-      if ( irq > 67)
-	prioreg = INTC_IPRB;
-      else
-	prioreg = INTC_IPRA;
-    }
-
-  /*
-   * Set the interrupt priority register
-   */
-  _ISR_Local_disable( level );
-
-    temp16 = read16( prioreg);
-    temp16 &= ~( 15 << shiftcount);
-    temp16 |= prio << shiftcount;
-    write16( temp16, prioreg);
-
-  _ISR_Local_enable( level );
-
-  return 0;
-}
-
-/*
- *  This routine provides the RTEMS interrupt management.
- */
-
-void __ISR_Handler( uint32_t   vector)
-{
-  ISR_Level level;
-
-  _ISR_Local_disable( level );
-
-  _Thread_Dispatch_disable();
-
-#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
-  if ( _ISR_Nest_level == 0 )
-    {
-      /* Install irq stack */
-      _old_stack_ptr = stack_ptr;
-      stack_ptr = _CPU_Interrupt_stack_high;
-    }
-
-#endif
-
-  _ISR_Nest_level++;
-
-  _ISR_Local_enable( level );
-
-  /* call isp */
-  if ( _ISR_Vector_table[ vector])
-    (*_ISR_Vector_table[ vector ])( vector );
-
-  _ISR_Local_disable( level );
-
-  _Thread_Dispatch_unnest( _Per_CPU_Get() );
-
-  _ISR_Nest_level--;
-
-#if(CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
-
-  if ( _ISR_Nest_level == 0 )
-    /* restore old stack pointer */
-    stack_ptr = _old_stack_ptr;
-#endif
-
-  _ISR_Local_enable( level );
-
-  if ( _ISR_Nest_level )
-    return;
-
-  if ( !_Thread_Dispatch_is_enabled() ) {
-    return;
-  }
-
-  if ( _Thread_Dispatch_necessary ) {
-    _Thread_Dispatch();
-  }
-}
diff --git a/c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c b/c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c
deleted file mode 100644
index 0240a5df26..0000000000
--- a/c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * This file contains the isp frames for the user interrupts.
- * From these procedures __ISR_Handler is called with the vector number
- * as argument.
- *
- * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
- * some releases of gcc doesn't properly handle #pragma interrupt, if a
- * file contains both isrs and normal functions.
- *
- *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
- *           Bernd Becker (becker@faw.uni-ulm.de)
- *
- *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
- *
- *
- *  COPYRIGHT (c) 1998.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#include <rtems/system.h>
-#include <rtems/score/types.h>
-#include <rtems/score/ispsh7032.h>
-
-/*
- * This is an exception vector table
- *
- * It has the same structure like the actual vector table (vectab)
- */
-proc_ptr _Hardware_isr_Table[256]={
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp,
-_nmi_isp, _usb_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp,
-/* trapa 0 -31 */
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-/* irq 64 ... */
-_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp,
-_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
-_dma0_isp, _dummy_isp, _dma1_isp, _dummy_isp,
-_dma2_isp, _dummy_isp, _dma3_isp, _dummy_isp,
-_imia0_isp, _imib0_isp, _ovi0_isp, _dummy_isp,
-_imia1_isp, _imib1_isp, _ovi1_isp, _dummy_isp,
-_imia2_isp, _imib2_isp, _ovi2_isp, _dummy_isp,
-_imia3_isp, _imib3_isp, _ovi3_isp, _dummy_isp,
-_imia4_isp, _imib4_isp, _ovi4_isp, _dummy_isp,
-_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp,
-_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
-_prt_isp, _adu_isp, _dummy_isp, _dummy_isp,
-_wdt_isp,
-/* 113 */ _dref_isp
-};
-
-#define Str(a)#a
-
-/*
- * Some versions of gcc and all version of egcs at least until egcs-1.1b
- * are not able to handle #pragma interrupt correctly if more than 1 isr is
- * contained in a file and when optimizing.
- * We try to work around this problem by using the macro below.
- */
-#define isp( name, number, func)\
-__asm__ (".global _"Str(name)"\n\t" \
-     "_"Str(name)":       \n\t" \
-     "    mov.l r0,@-r15   \n\t" \
-     "    mov.l r1,@-r15   \n\t" \
-     "    mov.l r2,@-r15   \n\t" \
-     "    mov.l r3,@-r15   \n\t" \
-     "    mov.l r4,@-r15   \n\t" \
-     "    mov.l r5,@-r15   \n\t" \
-     "    mov.l r6,@-r15   \n\t" \
-     "    mov.l r7,@-r15   \n\t" \
-     "    mov.l r14,@-r15  \n\t" \
-     "    sts.l pr,@-r15   \n\t" \
-     "    sts.l mach,@-r15 \n\t" \
-     "    sts.l macl,@-r15 \n\t" \
-     "    mov r15,r14      \n\t" \
-     "    mov.l "Str(name)"_k, r1\n\t" \
-     "    jsr @r1           \n\t" \
-     "    mov #"Str(number)", r4\n\t" \
-     "    mov   r14,r15    \n\t" \
-     "    lds.l @r15+,macl \n\t" \
-     "    lds.l @r15+,mach \n\t" \
-     "    lds.l @r15+,pr   \n\t" \
-     "    mov.l @r15+,r14  \n\t" \
-     "    mov.l @r15+,r7   \n\t" \
-     "    mov.l @r15+,r6   \n\t" \
-     "    mov.l @r15+,r5   \n\t" \
-     "    mov.l @r15+,r4   \n\t" \
-     "    mov.l @r15+,r3   \n\t" \
-     "    mov.l @r15+,r2   \n\t" \
-     "    mov.l @r15+,r1   \n\t" \
-     "    mov.l @r15+,r0   \n\t" \
-     "    rte              \n\t" \
-     "    nop              \n\t" \
-     "    .align 2         \n\t" \
-     #name"_k: \n\t" \
-     ".long "Str(func));
-
-/************************************************
- * Dummy interrupt service procedure for
- * interrupts being not allowed --> Trap 34
- ************************************************/
-__asm__ (" .section .text\n\
-.global __dummy_isp\n\
-__dummy_isp:\n\
-      mov.l r14,@-r15\n\
-      mov   r15, r14\n\
-      trapa #34\n\
-      mov.l @r15+,r14\n\
-      rte\n\
-      nop");
-
-/*****************************
- * Non maskable interrupt
- *****************************/
-isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
-
-/*****************************
- * User break controller
- *****************************/
-isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
-
-/*****************************
- *  External interrupts 0-7
- *****************************/
-isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
-isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler);
-isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler);
-isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler);
-isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler);
-isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler);
-isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler);
-isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler);
-
-/*****************************
- * DMA - controller
- *****************************/
-isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
-isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler);
-isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler);
-isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler);
-
-
-/*****************************
- * Interrupt timer unit
- *****************************/
-
-/*****************************
- * Timer 0
- *****************************/
-isp( _imia0_isp, IMIA0_ISP_V, ___ISR_Handler);
-isp( _imib0_isp, IMIB0_ISP_V, ___ISR_Handler);
-isp( _ovi0_isp,  OVI0_ISP_V, ___ISR_Handler);
-
-/*****************************
- * Timer 1
- *****************************/
-isp( _imia1_isp, IMIA1_ISP_V, ___ISR_Handler);
-isp( _imib1_isp, IMIB1_ISP_V, ___ISR_Handler);
-isp( _ovi1_isp,  OVI1_ISP_V, ___ISR_Handler);
-
-/*****************************
- * Timer 2
- *****************************/
-isp( _imia2_isp, IMIA2_ISP_V, ___ISR_Handler);
-isp( _imib2_isp, IMIB2_ISP_V, ___ISR_Handler);
-isp( _ovi2_isp,  OVI2_ISP_V, ___ISR_Handler);
-
-/*****************************
- * Timer 3
- *****************************/
-isp( _imia3_isp, IMIA3_ISP_V, ___ISR_Handler);
-isp( _imib3_isp, IMIB3_ISP_V, ___ISR_Handler);
-isp( _ovi3_isp,  OVI3_ISP_V, ___ISR_Handler);
-
-/*****************************
- * Timer 4
- *****************************/
-isp( _imia4_isp, IMIA4_ISP_V, ___ISR_Handler);
-isp( _imib4_isp, IMIB4_ISP_V, ___ISR_Handler);
-isp( _ovi4_isp,  OVI4_ISP_V, ___ISR_Handler);
-
-
-/*****************************
- * Serial interfaces
- *****************************/
-
-/*****************************
- * Serial interface 0
- *****************************/
-isp( _eri0_isp,  ERI0_ISP_V, ___ISR_Handler);
-isp( _rxi0_isp,  RXI0_ISP_V, ___ISR_Handler);
-isp( _txi0_isp,  TXI0_ISP_V, ___ISR_Handler);
-isp( _tei0_isp,  TEI0_ISP_V, ___ISR_Handler);
-
-/*****************************
- * Serial interface 1
- *****************************/
-isp( _eri1_isp,  ERI1_ISP_V, ___ISR_Handler);
-isp( _rxi1_isp,  RXI1_ISP_V, ___ISR_Handler);
-isp( _txi1_isp,  TXI1_ISP_V, ___ISR_Handler);
-isp( _tei1_isp,  TEI1_ISP_V, ___ISR_Handler);
-
-
-/*****************************
- * Parity control unit of
- * the bus state controller
- *****************************/
-isp( _prt_isp,  PRT_ISP_V, ___ISR_Handler);
-
-
-/******************************
- * Analog digital converter
- * ADC
- ******************************/
-isp( _adu_isp,  ADU_ISP_V, ___ISR_Handler);
-
-
-/******************************
- *  Watchdog timer
- ******************************/
-isp( _wdt_isp,  WDT_ISP_V, ___ISR_Handler);
-
-
-/******************************
- * DRAM refresh control unit
- * of bus state controller
- ******************************/
-isp( _dref_isp,  DREF_ISP_V, ___ISR_Handler);
diff --git a/c/src/lib/libcpu/sh/sh7032/timer/timer.c b/c/src/lib/libcpu/sh/sh7032/timer/timer.c
deleted file mode 100644
index 94a834cb1e..0000000000
--- a/c/src/lib/libcpu/sh/sh7032/timer/timer.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/**
- * @file
- * @brief Timer for the Hitachi SH 703X
- */
-
-/*
- *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
- *           Bernd Becker (becker@faw.uni-ulm.de)
- *
- *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- *  COPYRIGHT (c) 1998.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#include <rtems.h>
-#include <rtems/btimer.h>
-
-#include <rtems/score/sh_io.h>
-#include <rtems/score/ispsh7032.h>
-#include <rtems/score/iosh7032.h>
-
-extern uint32_t bsp_clicks_per_second;
-
-#define I_CLK_PHI_1     0
-#define I_CLK_PHI_2     1
-#define I_CLK_PHI_4     2
-#define I_CLK_PHI_8     3
-
-/*
- * Set I_CLK_PHI to one of the I_CLK_PHI_X values from above to choose
- * a PHI/X clock rate.
- */
-
-#define I_CLK_PHI       I_CLK_PHI_4
-#define CLOCK_SCALE     (1<<I_CLK_PHI)
-
-#define ITU1_STARTMASK 	0xfd
-#define ITU1_SYNCMASK 	0xfd
-#define ITU1_MODEMASK 	0xfd
-#define ITU1_TCRMASK 	(0x00 | I_CLK_PHI)
-#define ITU1_TIORMASK 	0x88
-#define ITU1_STAT_MASK 	0xf8
-#define ITU1_TIERMASK 	0xfc
-#define IPRC_ITU1_MASK	0xfff0
-
-#ifndef ITU1_PRIO
-#define ITU1_PRIO 15
-#endif
-
-#define ITU1_VECTOR OVI1_ISP_V
-
-extern rtems_isr timerisr(void);
-
-static uint32_t   Timer_interrupts;
-
-bool benchmark_timer_find_average_overhead;
-
-static uint32_t   Timer_HZ ;
-
-void benchmark_timer_initialize( void )
-{
-  uint8_t                temp8;
-  uint16_t               temp16;
-  rtems_interrupt_level  level;
-  rtems_isr             *ignored;
-
-  Timer_HZ = bsp_clicks_per_second / CLOCK_SCALE ;
-
-  /*
-   *  Timer has never overflowed.  This may not be necessary on some
-   *  implemenations of timer but ....
-   */
-
-  Timer_interrupts /* .i */ = 0;
-  rtems_interrupt_disable( level );
-
-  /*
-   *  Somehow start the timer
-   */
-  /* stop Timer 1  */
-  temp8 = read8(ITU_TSTR) & ITU1_STARTMASK;
-  write8( temp8, ITU_TSTR );
-
-  /* initialize counter 1 */
-  write16( 0, ITU_TCNT1 );
-
-  /* Timer 1 is independent of other timers */
-  temp8 = read8(ITU_TSNC) & ITU1_SYNCMASK;
-  write8( temp8, ITU_TSNC );
-
-  /* Timer 1, normal mode */
-  temp8 = read8(ITU_TMDR) & ITU1_MODEMASK;
-  write8( temp8, ITU_TMDR );
-
-  /* Use a Phi/X counter */
-  write8( ITU1_TCRMASK, ITU_TCR1 );
-
-  /* gra and grb are not used */
-  write8( ITU1_TIORMASK, ITU_TIOR1 );
-
-  /* reset all status flags */
-  temp8 = read8(ITU_TSR1) & ITU1_STAT_MASK;
-  write8( temp8, ITU_TSR1 );
-
-  /* enable overflow interrupt */
-  write8( ITU1_TIERMASK, ITU_TIER1 );
-
-  /* set interrupt priority */
-  temp16 = read16(INTC_IPRC) & IPRC_ITU1_MASK;
-  temp16 |= ITU1_PRIO;
-  write16( temp16, INTC_IPRC );
-
-  /* initialize ISR */
-  _CPU_ISR_install_raw_handler( ITU1_VECTOR, timerisr, &ignored );
-  rtems_interrupt_enable( level );
-
-  /* start timer 1 */
-  temp8 = read8(ITU_TSTR) | ~ITU1_STARTMASK;
-  write8( temp8, ITU_TSTR );
-}
-
-/*
- *  The following controls the behavior of benchmark_timer_read().
- *
- *  AVG_OVERHEAD is the overhead for starting and stopping the timer.  It
- *  is usually deducted from the number returned.
- *
- *  LEAST_VALID is the lowest number this routine should trust.  Numbers
- *  below this are "noise" and zero is returned.
- */
-
-#define AVG_OVERHEAD      1  /* It typically takes X.X microseconds */
-                             /* (Y countdowns) to start/stop the timer. */
-                             /* This value is in microseconds. */
-#define LEAST_VALID       0 /* 20 */ /* Don't trust a clicks value lower than this */
-
-benchmark_timer_t benchmark_timer_read( void )
-{
-  uint32_t   cclicks;
-  uint32_t   total ;
-  /*
-   *  Read the timer and see how many clicks it has been since we started.
-   */
-
-
-  cclicks = read16( ITU_TCNT1 );    /* XXX: read some HW here */
-
-  /*
-   *  Total is calculated by taking into account the number of timer overflow
-   *  interrupts since the timer was initialized and clicks since the last
-   *  interrupts.
-   */
-
-  total = cclicks + Timer_interrupts * 65536;
-
-  if ( benchmark_timer_find_average_overhead )
-    return total / CLOCK_SCALE;          /* in XXX microsecond units */
-  else
-  {
-    if ( total < LEAST_VALID )
-      return 0;            /* below timer resolution */
-  /*
-   *  Somehow convert total into microseconds
-   */
-    return (total / CLOCK_SCALE - AVG_OVERHEAD);
-  }
-}
-
-void benchmark_timer_disable_subtracting_average_overhead(bool find_flag)
-{
-  benchmark_timer_find_average_overhead = find_flag;
-}
-
-/* Timer 1 is used */
-
-#pragma interrupt
-void timerisr( void )
-{
-  uint8_t   temp8;
-
-  /* reset the flags of the status register */
-  temp8 = read8(ITU_TSR1) & ITU1_STAT_MASK;
-  write8( temp8, ITU_TSR1 );
-
-  Timer_interrupts += 1;
-}