New port from Ralf Corsepius <corsepiu@faw.uni-ulm.de>.

5 files changed, 385 insertions, 0 deletions

diff --git a/c/src/lib/libcpu/sh/sh7032/include/Makefile.in b/c/src/lib/libcpu/sh/sh7032/include/Makefile.in
new file mode 100644
index 0000000000..80e073e691
--- /dev/null
+++ b/c/src/lib/libcpu/sh/sh7032/include/Makefile.in
@@ -0,0 +1,36 @@
+#
+# $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+VPATH=@srcdir@
+RTEMS_ROOT = @top_srcdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+H_FILES = \
+	$(srcdir)/null.h \
+	$(srcdir)/sh7_pfc.h \
+	$(srcdir)/sh7_sci.h \
+	$(srcdir)/termbits.h \
+	$(srcdir)/ioqueue.h
+
+SRCS=$(H_FILES)
+
+include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+CLEAN_ADDITIONS +=
+CLOBBER_ADDITIONS +=
+
+all:	install
+
+# NOTE: Unlike other CPUS, we install into a subdirectory to avoid 
+#       file name conflicts
+
+install:
+	test -d $(PROJECT_INCLUDE)/sh || $(MKDIR) $(PROJECT_INCLUDE)/sh 
+	$(INSTALL) -m 444 $(H_FILES) $(PROJECT_INCLUDE)/sh
+
+all: FORCEIT
+	cd ../../../../libbsp/$(RTEMS_CPU)/$(RTEMS_BSP)/include; $(MAKE) all
diff --git a/c/src/lib/libcpu/sh/sh7032/include/ioqueue.h b/c/src/lib/libcpu/sh/sh7032/include/ioqueue.h
new file mode 100644
index 0000000000..55020acfad
--- /dev/null
+++ b/c/src/lib/libcpu/sh/sh7032/include/ioqueue.h
@@ -0,0 +1,77 @@
+/*
+ * Defines for low level queue management
+ *
+ *  Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, Ralf Corsepius, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * 
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ * $Id$
+ * 
+ */
+
+#ifndef _io_queue_h
+#define _io_queue_h
+
+#include <stdlib.h>	/* size_t */
+
+/*
+ * NOTE: size needs to be a power of 2
+ */
+#define IO_QUEUE(type,size,name) 			\
+typedef struct {					\
+  volatile type			queue[size] ;		\
+  volatile unsigned short	tail ;			\
+  volatile unsigned short	head ;			\
+} name ;
+
+#define IO_QUEUE_FULL(queue, size) \
+  ((queue)->tail == (((queue)->head+1) & ((size)-1)))
+
+#define IO_QUEUE_EMPTY(queue) \
+  (((queue)->tail) == ((queue)->head))
+
+#define IO_QUEUE_INIT(queue) \
+  (queue)->tail = (queue)->head = 0
+
+#define IO_QUEUE_ADD(queue,size) \
+  (queue)->head = (((queue)->head + 1) & ((size)-1))
+  
+#define IO_QUEUE_SUB(queue,size) \
+  (queue)->tail = (((queue)->tail + 1) & ((size)-1))
+
+#define IO_QUEUE_PUT(_queue,item) \
+{ \
+    size_t i; \
+    unsigned char* dest = (unsigned char*) ((_queue)->queue[(_queue)->head]); \
+    unsigned char* src  = (unsigned char*) (item); \
+    for( i = 0; i < sizeof(item); i++) \
+    { \
+	dest[i] = src[i]; \
+    } \
+}
+
+#define IO_QUEUE_GET(_queue,item) \
+{\
+   size_t i; \
+   unsigned char *src = (unsigned char*) (_queue)->queue[(_queue)->tail]; \
+   unsigned char *dest = (unsigned char*) (item); \
+   for( i=0; i< sizeof(item); i++)\
+   {\
+      dest[i] = src[i]; \
+   }\
+}
+
+#endif
diff --git a/c/src/lib/libcpu/sh/sh7032/include/null.h b/c/src/lib/libcpu/sh/sh7032/include/null.h
new file mode 100644
index 0000000000..9ce4886c14
--- /dev/null
+++ b/c/src/lib/libcpu/sh/sh7032/include/null.h
@@ -0,0 +1,72 @@
+/*  null.h
+ *
+ *  Null device driver, derived from rtems' stub driver.
+ *
+ *  Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1989-1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef __NULL_DRIVER_h
+#define __NULL_DRIVER_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DEVNULL_DRIVER_TABLE_ENTRY \
+  { null_initialize, null_open, null_close, null_read, \
+    null_write, null_control }
+
+#define NULL_SUCCESSFUL RTEMS_SUCCESSFUL
+
+rtems_device_driver null_initialize(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+rtems_device_driver null_open(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+rtems_device_driver null_close(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+rtems_device_driver null_read(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+rtems_device_driver null_write(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+rtems_device_driver null_control(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/* end of include file */
diff --git a/c/src/lib/libcpu/sh/sh7032/include/sh7_pfc.h b/c/src/lib/libcpu/sh/sh7032/include/sh7_pfc.h
new file mode 100644
index 0000000000..ba6580c5fd
--- /dev/null
+++ b/c/src/lib/libcpu/sh/sh7032/include/sh7_pfc.h
@@ -0,0 +1,118 @@
+/*
+ * Bit values for the pin function controller of the Hitachi SH703X
+ *
+ * From Hitachi tutorials
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef _sh7_pfc_h
+#define _sh7_pfc_h
+
+#include <rtems/score/iosh7030.h>
+
+/*
+ * Port B IO Register (PBIOR)
+ */
+#define PBIOR           PFC_PBIOR
+#define PB15IOR         0x8000
+#define PB14IOR         0x4000
+#define PB13IOR         0x2000
+#define PB12IOR         0x1000
+#define PB11IOR         0x0800
+#define PB10IOR         0x0400
+#define PB9IOR          0x0200
+#define PB8IOR          0x0100
+#define PB7IOR          0x0080
+#define PB6IOR          0x0040
+#define PB5IOR          0x0020
+#define PB4IOR          0x0010
+#define PB3IOR          0x0008
+#define PB2IOR          0x0004
+#define PB1IOR          0x0002
+#define PB0IOR          0x0001
+
+/*
+ * Port B Control Register (PBCR1)
+ */
+#define PBCR1           PFC_PBCR1
+#define PB15MD1         0x8000
+#define PB15MD0         0x4000
+#define PB14MD1         0x2000
+#define PB14MD0         0x1000
+#define PB13MD1         0x0800
+#define PB13MD0         0x0400
+#define PB12MD1         0x0200
+#define PB12MD0         0x0100
+#define PB11MD1         0x0080
+#define PB11MD0         0x0040
+#define PB10MD1         0x0020
+#define PB10MD0         0x0010
+#define PB9MD1          0x0008
+#define PB9MD0          0x0004
+#define PB8MD1          0x0002
+#define PB8MD0          0x0001
+
+#define PB15MD          PB15MD1|PB14MD0
+#define PB14MD          PB14MD1|PB14MD0
+#define PB13MD          PB13MD1|PB13MD0
+#define PB12MD          PB12MD1|PB12MD0
+#define PB11MD          PB11MD1|PB11MD0
+#define PB10MD          PB10MD1|PB10MD0
+#define PB9MD           PB9MD1|PB9MD0
+#define PB8MD           PB8MD1|PB8MD0
+
+#define PB_TXD1         PB11MD1
+#define PB_RXD1         PB10MD1
+#define PB_TXD0         PB9MD1
+#define PB_RXD0         PB8MD1
+
+/*
+ * Port B Control Register (PBCR2)
+ */
+#define PBCR2   PFC_PBCR2
+#define PB7MD1  0x8000
+#define PB7MD0  0x4000
+#define PB6MD1  0x2000
+#define PB6MD0  0x1000
+#define PB5MD1  0x0800
+#define PB5MD0  0x0400
+#define PB4MD1  0x0200
+#define PB4MD0  0x0100
+#define PB3MD1  0x0080
+#define PB3MD0  0x0040
+#define PB2MD1  0x0020
+#define PB2MD0  0x0010
+#define PB1MD1  0x0008
+#define PB1MD0  0x0004
+#define PB0MD1  0x0002
+#define PB0MD0  0x0001
+	
+#define PB7MD   PB7MD1|PB7MD0
+#define PB6MD   PB6MD1|PB6MD0
+#define PB5MD   PB5MD1|PB5MD0
+#define PB4MD   PB4MD1|PB4MD0
+#define PB3MD   PB3MD1|PB3MD0
+#define PB2MD   PB2MD1|PB2MD0
+#define PB1MD   PB1MD1|PB1MD0
+#define PB0MD   PB0MD1|PB0MD0
+
+#endif /* _sh7_pfc_h */
diff --git a/c/src/lib/libcpu/sh/sh7032/include/sh7_sci.h b/c/src/lib/libcpu/sh/sh7032/include/sh7_sci.h
new file mode 100644
index 0000000000..cb2cc03893
--- /dev/null
+++ b/c/src/lib/libcpu/sh/sh7032/include/sh7_sci.h
@@ -0,0 +1,82 @@
+/*
+ * Bit values for the serial control registers of the Hitachi SH703X
+ *
+ * From Hitachi tutorials
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef _sh7_sci_h
+#define _sh7_sci_h
+
+#include <rtems/score/iosh7030.h>
+
+/*
+ * Serial mode register bits
+ */
+
+#define SCI_SYNC_MODE               0x80
+#define SCI_SEVEN_BIT_DATA          0x40
+#define SCI_PARITY_ON               0x20
+#define SCI_ODD_PARITY              0x10
+#define SCI_STOP_BITS_2             0x08
+#define SCI_ENABLE_MULTIP           0x04
+#define SCI_PHI_64                  0x03
+#define SCI_PHI_16                  0x02
+#define SCI_PHI_4                   0x01
+#define SCI_PHI_0                   0x00
+
+/*
+ * Serial register offsets, relative to SCI0_SMR or SCI1_SMR
+ */
+
+#define SCI_SMR			0x00
+#define SCI_BRR			0x01
+#define SCI_SCR			0x02
+#define SCI_TDR			0x03
+#define SCI_SSR			0x04
+#define SCI_RDR			0x05
+
+/*
+ * Serial control register bits
+ */
+#define SCI_TIE                 0x80    /* Transmit interrupt enable */
+#define SCI_RIE                 0x40    /* Receive interrupt enable */
+#define SCI_TE                  0x20    /* Transmit enable */
+#define SCI_RE                  0x10    /* Receive enable */
+#define SCI_MPIE                0x08    /* Multiprocessor interrupt enable */
+#define SCI_TEIE                0x04    /* Transmit end interrupt enable */
+#define SCI_CKE1                0x02    /* Clock enable 1 */
+#define SCI_CKE0                0x01    /* Clock enable 0 */
+
+/*
+ * Serial status register bits
+ */
+#define SCI_TDRE                0x80    /* Transmit data register empty */
+#define SCI_RDRF                0x40    /* Receive data register full */
+#define SCI_ORER                0x20    /* Overrun error */
+#define SCI_FER                 0x10    /* Framing error */
+#define SCI_PER                 0x08    /* Parity error */
+#define SCI_TEND                0x04    /* Transmit end */
+#define SCI_MPB                 0x02    /* Multiprocessor bit */
+#define SCI_MPBT                0x01    /* Multiprocessor bit transfer */
+
+#endif /* _sh7_sci_h */