Add Virtex4 and Virtex5 BSPs

This commit covers at least PR2020, 2022, and 2023. This
patch adds all of the code for both BSPs, modifications
to libcpu/powerpc for the ppc440, and some updates to the
BSPs from follow up review and testing.

These BSPs should be good baselines for future development.
The configurations used by Ric are custom and have a non-standard
NIC. They also do not have a UART.  Thus the current console
driver just prints to a RAM buffer.

The NIC and UART support are left for future work. When the UART
support is added, moving the existing "to RAM" console driver to
a shared location is likely desirable because boards with no debug
UART port are commonly deployed. This would let printk() go to RAM.

10 files changed, 255 insertions, 190 deletions

diff --git a/c/src/lib/libcpu/powerpc/Makefile.am b/c/src/lib/libcpu/powerpc/Makefile.am
index 67eb8790d2..d01b91776f 100644
--- a/c/src/lib/libcpu/powerpc/Makefile.am
+++ b/c/src/lib/libcpu/powerpc/Makefile.am
@@ -94,7 +94,7 @@ include_libcpu_HEADERS += shared/src/stackTrace.h
 endif
 
 EXTRA_DIST += ppc403/README ppc403/vectors/README
-if ppc403
+if ppc4xx
 # ppc403/clock
 noinst_PROGRAMS += ppc403/clock.rel
 ppc403_clock_rel_SOURCES = ppc403/clock/clock.c
@@ -132,7 +132,7 @@ ppc403_tty_drv_rel_CPPFLAGS = $(AM_CPPFLAGS)
 ppc403_tty_drv_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
 endif
 
-endif # ppc403
+endif # ppc4xx
 
 if ppc405
 
diff --git a/c/src/lib/libcpu/powerpc/README b/c/src/lib/libcpu/powerpc/README
index 57ac52a9fa..820deb1b2f 100644
--- a/c/src/lib/libcpu/powerpc/README
+++ b/c/src/lib/libcpu/powerpc/README
@@ -22,6 +22,7 @@ family members using the new exception processing model:
   + mpc860
   + mpc8260
   + ppc405
+  + ppc440
 
 Note that because of similarities in various family members,
 the mpc823 should be able to use the mpc821 code and the
diff --git a/c/src/lib/libcpu/powerpc/configure.ac b/c/src/lib/libcpu/powerpc/configure.ac
index a77b907206..4fe697645d 100644
--- a/c/src/lib/libcpu/powerpc/configure.ac
+++ b/c/src/lib/libcpu/powerpc/configure.ac
@@ -41,6 +41,7 @@ AM_CONDITIONAL(shared, \
 || test "$RTEMS_CPU_MODEL" = "ppc603e" \
 || test "$RTEMS_CPU_MODEL" = "ppc403" \
 || test "$RTEMS_CPU_MODEL" = "ppc405" \
+|| test "$RTEMS_CPU_MODEL" = "ppc440" \
 || test "$RTEMS_CPU_MODEL" = "mpc604" \
 || test "$RTEMS_CPU_MODEL" = "mpc6xx" \
 || test "$RTEMS_CPU_MODEL" = "mpc8xx" \
@@ -74,10 +75,13 @@ AM_CONDITIONAL(mpc8260, test "$RTEMS_CPU_MODEL" = "mpc8260")
 AM_CONDITIONAL(mpc83xx, test "$RTEMS_CPU_MODEL" = "mpc83xx")
 AM_CONDITIONAL(qoriq, test "$RTEMS_CPU_MODEL" = "qoriq")
 
-# the ppc405 shares files with the ppc403
-AM_CONDITIONAL(ppc403,[test "$RTEMS_CPU_MODEL" = "ppc403" \
-|| test "$RTEMS_CPU_MODEL" = "ppc405"])
+# the ppc405 and ppc440 share files with the ppc403
+AM_CONDITIONAL(ppc403, test "$RTEMS_CPU_MODEL" = "ppc403")
 AM_CONDITIONAL(ppc405, test "$RTEMS_CPU_MODEL" = "ppc405")
+AM_CONDITIONAL(ppc440, test "$RTEMS_CPU_MODEL" = "ppc440")
+AM_CONDITIONAL(ppc4xx, test "$RTEMS_CPU_MODEL" = "ppc403" \
+|| test "$RTEMS_CPU_MODEL" = "ppc405" \
+|| test "$RTEMS_CPU_MODEL" = "ppc440")
 
 AM_CONDITIONAL(e500, test "$RTEMS_CPU_MODEL" = "e500" \
 || test "$RTEMS_CPU_MODEL" = "qoriq" )
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_categories.c b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_categories.c
index f13d720dce..260270dfba 100644
--- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_categories.c
+++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_categories.c
@@ -56,10 +56,10 @@ static const ppc_exc_categories ppc_405_category_table = {
   [ASM_PROG_VECTOR] = PPC_EXC_CLASSIC,
   [ASM_FLOAT_VECTOR] = PPC_EXC_CLASSIC,
 
-  [ASM_PPC405_APU_UNAVAIL_VECTOR] = PPC_EXC_CLASSIC,
-
   [ASM_SYS_VECTOR] = PPC_EXC_CLASSIC,
 
+  [ASM_PPC405_APU_UNAVAIL_VECTOR] = PPC_EXC_CLASSIC,
+
   [ASM_BOOKE_DEC_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
   [ASM_BOOKE_FIT_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
   [ASM_BOOKE_WDOG_VECTOR] = PPC_EXC_405_CRITICAL | PPC_EXC_ASYNC,
@@ -68,6 +68,25 @@ static const ppc_exc_categories ppc_405_category_table = {
   [ASM_TRACE_VECTOR] = PPC_EXC_405_CRITICAL,
 };
 
+static const ppc_exc_categories ppc_booke_category_table = {
+  [ASM_BOOKE_CRIT_VECTOR] = PPC_EXC_BOOKE_CRITICAL | PPC_EXC_ASYNC,
+  [ASM_MACH_VECTOR] = PPC_EXC_E500_MACHCHK,
+  [ASM_PROT_VECTOR] = PPC_EXC_CLASSIC,
+  [ASM_ISI_VECTOR] = PPC_EXC_CLASSIC,
+  [ASM_EXT_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
+  [ASM_ALIGN_VECTOR] = PPC_EXC_CLASSIC,
+  [ASM_PROG_VECTOR] = PPC_EXC_CLASSIC,
+  [ASM_FLOAT_VECTOR] = PPC_EXC_CLASSIC,
+  [ASM_SYS_VECTOR] = PPC_EXC_CLASSIC,
+  [ASM_BOOKE_APU_VECTOR] = PPC_EXC_CLASSIC,
+  [ASM_BOOKE_DEC_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
+  [ASM_BOOKE_FIT_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
+  [ASM_BOOKE_WDOG_VECTOR] = PPC_EXC_BOOKE_CRITICAL | PPC_EXC_ASYNC,
+  [ASM_BOOKE_DTLBMISS_VECTOR] = PPC_EXC_CLASSIC,
+  [ASM_BOOKE_ITLBMISS_VECTOR] = PPC_EXC_CLASSIC,
+  [ASM_BOOKE_DEBUG_VECTOR] = PPC_EXC_BOOKE_CRITICAL,
+};
+
 static const ppc_exc_categories mpc_5xx_category_table = {
   [ASM_RESET_VECTOR] = PPC_EXC_CLASSIC,
   [ASM_MACH_VECTOR] = PPC_EXC_CLASSIC,
@@ -286,6 +305,8 @@ const ppc_exc_categories *ppc_exc_categories_for_cpu(ppc_cpu_id_t cpu)
     case PPC_405GP:
     case PPC_405EX:
       return &ppc_405_category_table;
+    case PPC_440:
+      return &ppc_booke_category_table;
     default:
       break;
   }
diff --git a/c/src/lib/libcpu/powerpc/ppc403/clock/clock.c b/c/src/lib/libcpu/powerpc/ppc403/clock/clock.c
index 5d40090fc5..c807bbadcd 100644
--- a/c/src/lib/libcpu/powerpc/ppc403/clock/clock.c
+++ b/c/src/lib/libcpu/powerpc/ppc403/clock/clock.c
@@ -1,12 +1,17 @@
-/*  clock.c
+/**
+ *  @file
  *
  *  This routine initializes the interval timer on the
- *  PowerPC 403 CPU.  The tick frequency is specified by the bsp.
- *
+ *  PowerPC 403 CPU.  The tick frequency is specified by the BSP.
+ */
+
+/*
+ *  Original PPC403 Code from:
  *  Author: Andrew Bray <andy@i-cubed.co.uk>
- *
  *  COPYRIGHT (c) 1995 by i-cubed ltd.
  *
+ *  Modifications for PPC405GP by Dennis Ehlin
+ *
  *  To anyone who acknowledges that this file is provided "AS IS"
  *  without any express or implied warranty:
  *      permission to use, copy, modify, and distribute this file
@@ -18,22 +23,18 @@
  *      i-cubed limited makes no representations about the suitability
  *      of this software for any purpose.
  *
- *  Derived from c/src/lib/libcpu/hppa1.1/clock/clock.c:
- *
  *  Modifications for deriving timer clock from cpu system clock by
  *              Thomas Doerfler <td@imd.m.isar.de>
  *  for these modifications:
  *  COPYRIGHT (c) 1997 by IMD, Puchheim, Germany.
  *
- *  COPYRIGHT (c) 1989-2007.
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
  *  found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  *
- *  Modifications for PPC405GP by Dennis Ehlin
- *
  *  $Id$
  */
 
@@ -62,231 +63,244 @@ static bool auto_restart;
 
 void Clock_exit( void );
 
-rtems_isr_entry set_vector(                    /* returns old vector */
-  rtems_isr_entry     handler,                  /* isr routine        */
-  rtems_vector_number vector,                   /* vector number      */
-  int                 type                      /* RTEMS or RAW intr  */
-);
-
 static inline uint32_t   get_itimer(void)
 {
-    register uint32_t   rc;
+  register uint32_t   rc;
 
 #ifndef ppc405 /* this is a ppc403 */
-    __asm__ volatile ("mfspr %0, 0x3dd" : "=r" ((rc))); /* TBLO */
+  __asm__ volatile ("mfspr %0, 0x3dd" : "=r" ((rc))); /* TBLO */
 #else /* ppc405 */
-    __asm__ volatile ("mfspr %0, 0x10c" : "=r" ((rc))); /* 405GP TBL */
+  __asm__ volatile ("mfspr %0, 0x10c" : "=r" ((rc))); /* 405GP TBL */
 #endif /* ppc405 */
 
-    return rc;
+  return rc;
 }
 
 /*
  *  ISR Handler
  */
-
 void Clock_isr(void* handle)
 {
-    uint32_t   clicks_til_next_interrupt;
+  uint32_t   clicks_til_next_interrupt;
 #if defined(BSP_PPC403_CLOCK_ISR_IRQ_LEVEL)
-	uint32_t   l_orig = _ISR_Get_level();
+  uint32_t   l_orig = _ISR_Get_level();
+#endif
+
+  if (!auto_restart) {
+    uint32_t   itimer_value;
+    /*
+     * setup for next interrupt; making sure the new value is reasonably
+     * in the future.... in case we lost out on an interrupt somehow
+     */
+    itimer_value = get_itimer();
+    tick_time += pit_value;
+
+    /*
+     * how far away is next interrupt *really*
+     * It may be a long time; this subtraction works even if
+     * Clock_clicks_interrupt < Clock_clicks_low_order via
+     * the miracle of unsigned math.
+     */
+    clicks_til_next_interrupt = tick_time - itimer_value;
+
+    /*
+     * If it is too soon then bump it up.
+     * This should only happen if CPU_HPPA_CLICKS_PER_TICK is too small.
+     * But setting it low is useful for debug, so...
+     */
+
+    if (clicks_til_next_interrupt < 400) {
+      tick_time = itimer_value + 1000;
+      clicks_til_next_interrupt = 1000;
+      /* XXX: count these! this should be rare */
+    }
+
+    /*
+     * If it is too late, that means we missed the interrupt somehow.
+     * Rather than wait 35-50s for a wrap, we just fudge it here.
+     */
+
+    if (clicks_til_next_interrupt > pit_value) {
+      tick_time = itimer_value + 1000;
+      clicks_til_next_interrupt = 1000;
+      /* XXX: count these! this should never happen :-) */
+    }
+
+#ifndef ppc440
+    __asm__ volatile ("mtspr 0x3db, %0" :: "r"
+                      (clicks_til_next_interrupt)); /* PIT */
+#else
+    __asm__ volatile ("mtspr 0x016, %0" :: "r"
+                      (clicks_til_next_interrupt)); /* Decrementer */
 #endif
-    if (!auto_restart)
-    {
-      uint32_t   itimer_value;
-      /*
-       * setup for next interrupt; making sure the new value is reasonably
-       * in the future.... in case we lost out on an interrupt somehow
-       */
-
-      itimer_value = get_itimer();
-      tick_time += pit_value;
-
-      /*
-       * how far away is next interrupt *really*
-       * It may be a long time; this subtraction works even if
-       * Clock_clicks_interrupt < Clock_clicks_low_order via
-       * the miracle of unsigned math.
-       */
-      clicks_til_next_interrupt = tick_time - itimer_value;
-
-      /*
-       * If it is too soon then bump it up.
-       * This should only happen if CPU_HPPA_CLICKS_PER_TICK is too small.
-       * But setting it low is useful for debug, so...
-       */
-
-      if (clicks_til_next_interrupt < 400)
-      {
-        tick_time = itimer_value + 1000;
-        clicks_til_next_interrupt = 1000;
-        /* XXX: count these! this should be rare */
-      }
-
-      /*
-       * If it is too late, that means we missed the interrupt somehow.
-       * Rather than wait 35-50s for a wrap, we just fudge it here.
-       */
-
-      if (clicks_til_next_interrupt > pit_value)
-      {
-        tick_time = itimer_value + 1000;
-        clicks_til_next_interrupt = 1000;
-        /* XXX: count these! this should never happen :-) */
-      }
-
-      __asm__ volatile ("mtspr 0x3db, %0" :: "r"
-                         (clicks_til_next_interrupt)); /* PIT */
   }
 
+#ifndef ppc440
     __asm__ volatile ( "mtspr 0x3d8, %0" :: "r" (0x08000000)); /* TSR */
+#else /* Book E */
+    __asm__ volatile ( "mtspr 0x150, %0" :: "r" (0x08000000)); /* TSR */
+#endif
 
-    Clock_driver_ticks++;
-
-	/* Give BSP a chance to say if they want to re-enable interrupts */
+  Clock_driver_ticks++;
 
+  /* Give BSP a chance to say if they want to re-enable interrupts */
 #if defined(BSP_PPC403_CLOCK_ISR_IRQ_LEVEL)
-	_ISR_Set_level(BSP_PPC403_CLOCK_ISR_IRQ_LEVEL);
+  _ISR_Set_level(BSP_PPC403_CLOCK_ISR_IRQ_LEVEL);
 #endif
-
-    rtems_clock_tick();
+  rtems_clock_tick();
 
 #if defined(BSP_PPC403_CLOCK_ISR_IRQ_LEVEL)
-	_ISR_Set_level(l_orig)
+  _ISR_Set_level(l_orig)
 #endif
 }
 
 int ClockIsOn(const rtems_irq_connect_data* unused)
 {
-    register uint32_t   tcr;
+  register uint32_t   tcr;
 
-    __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
+#ifndef ppc440
+  __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
+#else /* Book E */
+  __asm__ volatile ("mfspr %0, 0x154" : "=r" ((tcr))); /* TCR */
+#endif
 
-    return (tcr & 0x04000000) != 0;
+  return (tcr & 0x04000000) != 0;
 }
 
-void ClockOff(
-	      const rtems_irq_connect_data* unused
-)
+void ClockOff(const rtems_irq_connect_data* unused)
 {
-    register uint32_t   tcr;
-
-    __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
-
-    tcr &= ~ 0x04400000;
-
-    __asm__ volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
+  register uint32_t   tcr;
+
+#ifndef ppc440
+  __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
+  tcr &= ~ 0x04400000;
+  __asm__ volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
+#else /* Book E */
+  __asm__ volatile ("mfspr %0, 0x154" : "=r" ((tcr))); /* TCR */
+  tcr &= ~ 0x04400000;
+  __asm__ volatile ("mtspr 0x154, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
+#endif
 }
 
-void ClockOn(
-	      const rtems_irq_connect_data* unused
-)
+void ClockOn(const rtems_irq_connect_data* unused)
 {
-    uint32_t   iocr;
-    register uint32_t   tcr;
-#ifndef ppc405
-    uint32_t   pvr;
+  uint32_t   iocr;
+  register uint32_t   tcr;
+#ifdef ppc403
+  uint32_t   pvr;
 #endif /* ppc403 */
 
-    Clock_driver_ticks = 0;
+  Clock_driver_ticks = 0;
 
-#ifndef ppc405 /* this is a ppc403 */
-    __asm__ volatile ("mfdcr %0, 0xa0" : "=r" (iocr)); /* IOCR */
-    if (bsp_timer_internal_clock) {
-	iocr &= ~4; /* timer clocked from system clock */
-    }
-    else {
-	iocr |= 4; /* select external timer clock */
-    }
-    __asm__ volatile ("mtdcr 0xa0, %0" : "=r" (iocr) : "0" (iocr)); /* IOCR */
+#ifdef ppc403 /* this is a ppc403 */
+  __asm__ volatile ("mfdcr %0, 0xa0" : "=r" (iocr)); /* IOCR */
+  if (bsp_timer_internal_clock) {
+    iocr &= ~4; /* timer clocked from system clock */
+  } else {
+    iocr |= 4; /* select external timer clock */
+  }
+  __asm__ volatile ("mtdcr 0xa0, %0" : "=r" (iocr) : "0" (iocr)); /* IOCR */
 
-    __asm__ volatile ("mfspr %0, 0x11f" : "=r" ((pvr))); /* PVR */
-    if (((pvr & 0xffff0000) >> 16) != 0x0020)
-      return; /* Not a ppc403 */
+  __asm__ volatile ("mfspr %0, 0x11f" : "=r" ((pvr))); /* PVR */
+  if (((pvr & 0xffff0000) >> 16) != 0x0020)
+    return; /* Not a ppc403 */
 
-    if ((pvr & 0xff00) == 0x0000) /* 403GA */
+  if ((pvr & 0xff00) == 0x0000) /* 403GA */
 #if 0 /* FIXME: in which processor versions will "autoload" work properly? */
-      auto_restart = (pvr & 0x00f0) > 0x0000 ? true : false;
+   auto_restart = (pvr & 0x00f0) > 0x0000 ? true : false;
 #else
-    /* no known chip version supports auto restart of timer... */
-    auto_restart = false;
+   /* no known chip version supports auto restart of timer... */
+   auto_restart = false;
 #endif
-    else if ((pvr & 0xff00) == 0x0100) /* 403GB */
-      auto_restart = true;
-
-#else /* ppc405 */
-    __asm__ volatile ("mfdcr %0, 0x0b2" : "=r" (iocr));  /*405GP CPC0_CR1 */
-    if (bsp_timer_internal_clock) {
-	iocr &=~0x800000	;/* timer clocked from system clock CETE*/
-    }
-    else {
-	iocr |= 0x800000; /* select external timer clock CETE*/
-    }
-    __asm__ volatile ("mtdcr 0x0b2, %0" : "=r" (iocr) : "0" (iocr)); /* 405GP CPC0_CR1 */
-
-     /*
-      * Enable auto restart
-      */
-
-    auto_restart=true;
-
-#endif /* ppc405 */
-    pit_value = rtems_configuration_get_microseconds_per_tick() *
-      bsp_clicks_per_usec;
-
-     /*
-      * Set PIT value
-      */
-
-    __asm__ volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */
-
-     /*
-      * Set timer to autoreload, bit TCR->ARE = 1  0x0400000
-      * Enable PIT interrupt, bit TCR->PIE = 1     0x4000000
-      */
-    tick_time = get_itimer() + pit_value;
+   else if ((pvr & 0xff00) == 0x0100) /* 403GB */
+     auto_restart = true;
+
+#elif defined(ppc405) /* ppc405 */
+  __asm__ volatile ("mfdcr %0, 0x0b2" : "=r" (iocr));  /*405GP CPC0_CR1 */
+  if (bsp_timer_internal_clock) {
+    iocr &=~0x800000; /* timer clocked from system clock CETE */
+  } else {
+    iocr |= 0x800000; /* select external timer clock CETE */
+  }
+  /* 405GP CPC0_CR1 */
+  __asm__ volatile ("mtdcr 0x0b2, %0" : "=r" (iocr) : "0" (iocr));
 
-    __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
-    tcr = (tcr & ~0x04400000) | (auto_restart ? 0x04400000 : 0x04000000);
-#if 1
-    __asm__ volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
+  /*
+   * Enable auto restart
+   */
+  auto_restart = true;
+#else
+  /* PPC440 */
+  __asm__ volatile ("mfspr %0, 0x378" : "=r" (iocr));  /* 440 CCR1 */
+  if (bsp_timer_internal_clock) {
+    iocr &= ~0x00000100;           /* timer clocked from system clock CETE */
+  } else {
+    iocr |= 0x00000100;           /* select external timer clock CETE */
+  }
+  __asm__ volatile ("mtspr 0x378, %0" : "=r" (iocr) : "0" (iocr)); /*440 CCR1*/
+#endif
+  pit_value = rtems_configuration_get_microseconds_per_tick() *
+                bsp_clicks_per_usec;
+
+  /*
+   * Set PIT value
+   */
+#ifndef ppc440
+  __asm__ volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */
+#else /* Book E */
+  __asm__ volatile ("mtspr 0x016, %0" : : "r" (pit_value)); /* Decrementer */
 #endif
 
+   /*
+    * Set timer to autoreload, bit TCR->ARE = 1  0x0400000
+    * Enable PIT interrupt, bit TCR->PIE = 1     0x4000000
+    */
+  tick_time = get_itimer() + pit_value;
+
+#ifndef ppc440
+  __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
+  tcr = (tcr & ~0x04400000) | (auto_restart ? 0x04400000 : 0x04000000);
+  __asm__ volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
+#else /* Book E */
+  __asm__ volatile ("mfspr %0, 0x154" : "=r" ((tcr)));               /* TCR */
+  tcr = (tcr & ~0x04400000) | (auto_restart ? 0x04400000 : 0x04000000);
+  __asm__ volatile ("mtspr 0x154, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
+#endif
 }
 
-
-
 void Install_clock(
   void (*clock_isr)(void *)
 )
 {
-   rtems_irq_connect_data clockIrqConnData;
+  rtems_irq_connect_data clockIrqConnData;
 
-    Clock_driver_ticks = 0;
+  Clock_driver_ticks = 0;
 
-    /*
-     * initialize the interval here
-     * First tick is set to right amount of time in the future
-     * Future ticks will be incremented over last value set
-     * in order to provide consistent clicks in the face of
-     * interrupt overhead
-     */
+  /*
+   * initialize the interval here
+   * First tick is set to right amount of time in the future
+   * Future ticks will be incremented over last value set
+   * in order to provide consistent clicks in the face of
+   * interrupt overhead
+   */
+  clockIrqConnData.on   = ClockOn;
+  clockIrqConnData.off  = ClockOff;
+  clockIrqConnData.isOn = ClockIsOn;
+#if defined(ppc440) || defined(ppc405)
+  clockIrqConnData.name = BSP_PIT;
+#else
+  clockIrqConnData.name = BSP_DECREMENTER;
+#endif
+  clockIrqConnData.hdl  = clock_isr;
+  if (!BSP_install_rtems_irq_handler (&clockIrqConnData)) {
+    printk("Unable to connect Clock Irq handler\n");
+    rtems_fatal_error_occurred(1);
+  }
 
-   clockIrqConnData.on   = ClockOn;
-   clockIrqConnData.off  = ClockOff;
-   clockIrqConnData.isOn = ClockIsOn;
-   clockIrqConnData.name = BSP_PIT;
-   clockIrqConnData.hdl  = clock_isr;
-   if (!BSP_install_rtems_irq_handler (&clockIrqConnData)) {
-     printk("Unable to connect Clock Irq handler\n");
-     rtems_fatal_error_occurred(1);
-   }
-
-   atexit(Clock_exit);
+  atexit(Clock_exit);
 }
 
-void
-ReInstall_clock(
+void ReInstall_clock(
   void (*new_clock_isr)(void *)
 )
 {
@@ -295,8 +309,11 @@ ReInstall_clock(
 
   rtems_interrupt_disable(isrlevel);
 
-
+#if defined(ppc440) || defined(ppc405)
   clockIrqConnData.name = BSP_PIT;
+#else
+  clockIrqConnData.name = BSP_DECREMENTER;
+#endif
   if (!BSP_get_current_rtems_irq_handler(&clockIrqConnData)) {
     printk("Unable to stop system clock\n");
     rtems_fatal_error_occurred(1);
@@ -307,7 +324,11 @@ ReInstall_clock(
   clockIrqConnData.on   = ClockOn;
   clockIrqConnData.off  = ClockOff;
   clockIrqConnData.isOn = ClockIsOn;
+#if defined(ppc440) || defined(ppc405)
   clockIrqConnData.name = BSP_PIT;
+#else
+  clockIrqConnData.name = BSP_DECREMENTER;
+#endif
   clockIrqConnData.hdl  = new_clock_isr;
 
   if (!BSP_install_rtems_irq_handler (&clockIrqConnData)) {
@@ -318,7 +339,6 @@ ReInstall_clock(
   rtems_interrupt_enable(isrlevel);
 }
 
-
 /*
  * Called via atexit()
  * Remove the clock interrupt handler by setting handler to NULL
@@ -326,12 +346,15 @@ ReInstall_clock(
  * This will not work on the 405GP because
  * when bit's are set in TCR they can only be unset by a reset
  */
-
 void Clock_exit(void)
 {
   rtems_irq_connect_data clockIrqConnData;
 
+#if defined(ppc440) || defined(ppc405)
   clockIrqConnData.name = BSP_PIT;
+#else
+  clockIrqConnData.name = BSP_DECREMENTER;
+#endif
   if (!BSP_get_current_rtems_irq_handler(&clockIrqConnData)) {
     printk("Unable to stop system clock\n");
     rtems_fatal_error_occurred(1);
diff --git a/c/src/lib/libcpu/powerpc/preinstall.am b/c/src/lib/libcpu/powerpc/preinstall.am
index c6fbf8e2e0..79b7d88878 100644
--- a/c/src/lib/libcpu/powerpc/preinstall.am
+++ b/c/src/lib/libcpu/powerpc/preinstall.am
@@ -96,13 +96,13 @@ $(PROJECT_INCLUDE)/libcpu/stackTrace.h: shared/src/stackTrace.h $(PROJECT_INCLUD
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/stackTrace.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/stackTrace.h
 endif
-if ppc403
+if ppc4xx
 if ppc405
 $(PROJECT_INCLUDE)/tty_drv.h: ppc403/tty_drv/tty_drv.h $(PROJECT_INCLUDE)/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tty_drv.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/tty_drv.h
 endif
-endif # ppc403
+endif # ppc4xx
 if ppc405
 $(PROJECT_INCLUDE)/ppc4xx/$(dirstamp):
 	@$(MKDIR_P) $(PROJECT_INCLUDE)/ppc4xx
diff --git a/c/src/lib/libcpu/powerpc/rtems/powerpc/debugmod.h b/c/src/lib/libcpu/powerpc/rtems/powerpc/debugmod.h
index 692a5643cc..565534fcd8 100644
--- a/c/src/lib/libcpu/powerpc/rtems/powerpc/debugmod.h
+++ b/c/src/lib/libcpu/powerpc/rtems/powerpc/debugmod.h
@@ -78,7 +78,7 @@ extern "C" {
 #define PPC_DEBUG_MODEL_SINGLE_STEP_ONLY 2
 #define PPC_DEBUG_MODEL_IBM4xx           3
 
-#elif defined(ppc403) || defined(ppc405)
+#elif defined(ppc403) || defined(ppc405) || defined(ppc440)
 
 #define PPC_DEBUG_MODEL          PPC_DEBUG_MODEL_IBM4xx
 
diff --git a/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h b/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h
index 9609fd10d2..092fbf93ec 100644
--- a/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h
+++ b/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h
@@ -137,6 +137,17 @@ extern "C" {
 #define PPC_HAS_EXCEPTION_PREFIX 0
 #define PPC_HAS_EVPR             1
 
+#elif defined (ppc440)
+
+#define PPC_CACHE_ALIGNMENT         32
+#define PPC_HAS_RI                   0
+#define PPC_HAS_RFCI                 1
+#define PPC_USE_MULTIPLE             1
+#define PPC_I_CACHE              32768
+#define PPC_D_CACHE              32768
+#define PPC_HAS_EXCEPTION_PREFIX     0
+#define PPC_HAS_EVPR                 1
+
 #elif defined(mpc555)
 
 /* Copied from mpc505 */
@@ -380,7 +391,7 @@ extern "C" {
 
 #define PPC_IRQ_FIRST           PPC_IRQ_SYSTEM_RESET
 
-#if defined(ppc403) || defined(ppc405)
+#if defined(ppc403) || defined(ppc405) || defined(ppc440)
 
 #define PPC_IRQ_CRIT     PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
 #define PPC_IRQ_PIT      (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/
diff --git a/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c b/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c
index 9acdafb696..2c671c6c74 100644
--- a/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c
+++ b/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c
@@ -33,6 +33,7 @@ const char *get_ppc_cpu_type_name(ppc_cpu_id_t cpu)
     case PPC_405:		return "PPC405";
 	case PPC_405GP:		return "PPC405GP";
 	case PPC_405EX:		return "PPC405EX";
+    case PPC_440:               return "PPC440";
     case PPC_601:		return "MPC601";
     case PPC_5XX:		return "MPC5XX";
     case PPC_603:		return "MPC603";
@@ -104,6 +105,7 @@ ppc_cpu_id_t get_ppc_cpu_type(void)
     case PPC_405:
     case PPC_405GP:
     case PPC_405EX:
+    case PPC_440:
     case PPC_601:
     case PPC_5XX:
     case PPC_603:
@@ -150,7 +152,7 @@ ppc_cpu_id_t get_ppc_cpu_type(void)
     case PPC_7400:
 	/* NOTE: PSIM PVR doesn't tell us anything (its
      *       contents are not set based on what model
-	 *       the uses chooses but has to be programmed via
+       *       the user chooses but has to be programmed via
 	 *       the device file with the special value 0xfffe
 	 *       telling us that we have a 'psim cpu').
 	 *
@@ -182,6 +184,8 @@ ppc_cpu_id_t get_ppc_cpu_type(void)
  	case PPC_405EX:
 		current_ppc_features.is_bookE			= PPC_BOOKE_405;
 	break;
+    case PPC_440:
+      current_ppc_features.is_bookE          = PPC_BOOKE_STD;
   	case PPC_8540:
   	case PPC_e200z0:
   	case PPC_e200z1:
diff --git a/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h b/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h
index cae5d84ead..d37a6ee50d 100644
--- a/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h
+++ b/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h
@@ -35,12 +35,13 @@ typedef enum
   PPC_604e = 0x9,
   PPC_604r = 0xA,
   PPC_7400 = 0xC,
-  PPC_405  = 0x2001,
+  PPC_405  = 0x2001,  /* Xilinx Virtex-II Pro or -4 */
   PPC_405EX = 0x1291,	/* + 405EXr */
   PPC_405GP = 0x4011,	/* + 405CR */
   PPC_405GPr = 0x5091,
   PPC_405EZ = 0x4151,
   PPC_405EP = 0x5121,
+  PPC_440 = 0x7ff2,  /* Xilinx Virtex-5*/
   PPC_7455 = 0x8001, /* Kate Feng */
   PPC_7457 = 0x8002,
   PPC_620 = 0x16,