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author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2002-05-14 16:56:44 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2002-05-14 16:56:44 +0000 |
commit | 0d776cd24743625f2888d04d72188b2e3f416a3e (patch) | |
tree | 3f146379e2bd7bdd9f4ee85485fb5039fc036b71 /c/src/lib/libcpu/powerpc/shared | |
parent | 2001-05-14 Till Straumann <strauman@slac.stanford.edu> (diff) | |
download | rtems-0d776cd24743625f2888d04d72188b2e3f416a3e.tar.bz2 |
2001-05-14 Till Straumann <strauman@slac.stanford.edu>
* rtems/powerpc/registers.h, rtems/score/ppc.h: Per PR213, add
the following:
- support for the MPC74000 (AKA G4); there is no
AltiVec support yet, however.
- the cache flushing assembly code uses hardware-flush on the G4.
Also, a couple of hardcoded numerical values were replaced
by more readable symbolic constants.
- extended interrupt-disabled code section so enclose the entire
cache flush/invalidate procedure (as recommended by the book).
This is not (latency) critical as it is only used by
init code but prevents possible corruption.
- Trivial page table support as been added.
(1:1 effective-virtual-physical address mapping which is only
useful only on CPUs which feature hardware TLB replacement,
e.g. >604. This allows for write-protecting memory regions,
e.g. text/ro-data which makes catching corruptors a lot easier.
It also frees one DBAT/IBAT and gives more flexibility
for setting up address maps :-)
- setdbat() allows changing BAT0 also (since the BSP may use
a page table, BAT0 could be available...).
- asm_setdbatX() violated the SVR ABI by using
r20 as a scratch register; changed for r0
- according to the book, a context synchronizing instruction is
necessary prior to and after changing a DBAT -> isync added
Diffstat (limited to 'c/src/lib/libcpu/powerpc/shared')
-rw-r--r-- | c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c | 25 | ||||
-rw-r--r-- | c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h | 2 |
2 files changed, 24 insertions, 3 deletions
diff --git a/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c b/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c index ddb7775d89..5e4a78848a 100644 --- a/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c +++ b/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c @@ -26,10 +26,29 @@ SPR_RO(PVR) ppc_cpu_id_t current_ppc_cpu = PPC_UNKNOWN; ppc_cpu_revision_t current_ppc_revision = 0xff; +char *get_ppc_cpu_type_name(ppc_cpu_id_t cpu) +{ + switch (cpu) { + case PPC_601: return "MPC601"; + case PPC_603: return "MPC603"; + case PPC_603ev: return "MPC603ev"; + case PPC_604: return "MPC604"; + case PPC_750: return "MPC750"; + case PPC_7400: return "MPC7400"; + case PPC_604e: return "MPC604e"; + case PPC_604r: return "MPC604r"; + case PPC_620: return "MPC620"; + case PPC_860: return "MPC860"; + case PPC_8260: return "MPC8260"; + default: + printk("Unknown CPU value of 0x%x. Please add it to <libcpu/powerpc/shared/cpu.h>\n", cpu ); + } + return "UNKNOWN"; +} + ppc_cpu_id_t get_ppc_cpu_type() { unsigned int pvr = (_read_PVR() >> 16); - current_ppc_cpu = (ppc_cpu_id_t) pvr; switch (pvr) { case PPC_601: @@ -37,19 +56,19 @@ ppc_cpu_id_t get_ppc_cpu_type() case PPC_603ev: case PPC_604: case PPC_750: + case PPC_7400: case PPC_604e: case PPC_604r: case PPC_620: case PPC_860: case PPC_8260: - current_ppc_cpu = (ppc_cpu_id_t) pvr; return current_ppc_cpu; default: printk("Unknown PVR value of 0x%x. Please add it to <libcpu/powerpc/shared/cpu.h>\n", pvr ); return PPC_UNKNOWN; } - } + ppc_cpu_revision_t get_ppc_cpu_revision() { ppc_cpu_revision_t rev = (ppc_cpu_revision_t) (_read_PVR() & 0xffff); diff --git a/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h b/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h index 7d608bfe33..e61749067e 100644 --- a/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h +++ b/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h @@ -27,6 +27,7 @@ typedef enum PPC_750 = 0x8, PPC_604e = 0x9, PPC_604r = 0xA, + PPC_7400 = 0xA, PPC_620 = 0x16, PPC_860 = 0x50, PPC_821 = PPC_860, @@ -38,6 +39,7 @@ typedef unsigned short ppc_cpu_revision_t; extern ppc_cpu_id_t get_ppc_cpu_type (); extern ppc_cpu_id_t current_ppc_cpu; +extern char *get_ppc_cpu_type_name(ppc_cpu_id_t cpu); extern ppc_cpu_revision_t get_ppc_cpu_revision (); extern ppc_cpu_revision_t current_ppc_revision; #endif /* ASM */ |