2001-11-08 Dennis Ehlin (ECS) <Dennis.Ehlin@ecs.ericsson.se>

	This modification is part of the submitted modifications necessary to
	support the IBM PPC405 family.  This submission was reviewed by
	Thomas Doerfler <Thomas.Doerfler@imd-systems.de> who ensured it did
	not negatively impact the ppc403 BSPs.  The submission and tracking
	process was captured as PR50.
	* ppc403/console/console405.c ppc403/tty_drv/.cvsignore,
	ppc403/tty_drv/Makefile.am, ppc403/tty_drv/tty_drv.c,
	ppc403/tty_drv/tty_drv.h: New files.
	* Makefile.am, README, configure.ac, old_exception_processing/cpu.c,
	old_exception_processing/cpu.h, ppc403/Makefile.am,
	ppc403/clock/clock.c, ppc403/console/Makefile.am,
	ppc403/console/console.c, ppc403/ictrl/ictrl.c, ppc403/ictrl/ictrl.h,
	ppc403/timer/timer.c: Modified.

1 files changed, 42 insertions, 15 deletions

diff --git a/c/src/lib/libcpu/powerpc/ppc403/clock/clock.c b/c/src/lib/libcpu/powerpc/ppc403/clock/clock.c
index d7e9514b5f..5ba10ace42 100644
--- a/c/src/lib/libcpu/powerpc/ppc403/clock/clock.c
+++ b/c/src/lib/libcpu/powerpc/ppc403/clock/clock.c
@@ -25,7 +25,6 @@
  *  for these modifications:
  *  COPYRIGHT (c) 1997 by IMD, Puchheim, Germany.
  *
- *
  *  COPYRIGHT (c) 1989-1999.
  *  On-Line Applications Research Corporation (OAR).
  *
@@ -33,6 +32,8 @@
  *  found in the file LICENSE in this distribution or at
  *  http://www.OARcorp.com/rtems/license.html.
  *
+ *  Modifications for PPC405GP by Dennis Ehlin
+ *
  *  $Id$
  */
 
@@ -59,7 +60,11 @@ static inline rtems_unsigned32 get_itimer(void)
 {
     register rtems_unsigned32 rc;
 
+#ifndef ppc405 /* this is a ppc403 */
     asm volatile ("mfspr %0, 0x3dd" : "=r" ((rc))); /* TBLO */
+#else /* ppc405 */
+    asm volatile ("mfspr %0, 0x10c" : "=r" ((rc))); /* 405GP TBL */
+#endif /* ppc405 */
 
     return rc;
 }
@@ -71,11 +76,10 @@ static inline rtems_unsigned32 get_itimer(void)
 rtems_isr
 Clock_isr(rtems_vector_number vector)
 {
+      rtems_unsigned32 clicks_til_next_interrupt;
     if (!auto_restart)
     {
-      rtems_unsigned32 clicks_til_next_interrupt;
       rtems_unsigned32 itimer_value;
- 
       /*
        * setup for next interrupt; making sure the new value is reasonably
        * in the future.... in case we lost out on an interrupt somehow
@@ -131,24 +135,25 @@ Clock_isr(rtems_vector_number vector)
 void Install_clock(rtems_isr_entry clock_isr)
 {
     rtems_isr_entry previous_isr;
-    rtems_unsigned32 pvr, iocr;
+    rtems_unsigned32 iocr;
     register rtems_unsigned32 tcr;
+#ifdef ppc403
+    rtems_unsigned32 pvr;
+#endif /* ppc403 */
  
     Clock_driver_ticks = 0;
  
+#ifndef ppc405 /* this is a ppc403 */
     asm volatile ("mfdcr %0, 0xa0" : "=r" (iocr)); /* IOCR */
-
     if (rtems_cpu_configuration_get_timer_internal_clock()) {
 	iocr &= ~4; /* timer clocked from system clock */
     }
     else {
 	iocr |= 4; /* select external timer clock */
     }
-
     asm volatile ("mtdcr 0xa0, %0" : "=r" (iocr) : "0" (iocr)); /* IOCR */
  
     asm volatile ("mfspr %0, 0x11f" : "=r" ((pvr))); /* PVR */
- 
     if (((pvr & 0xffff0000) >> 16) != 0x0020)
       return; /* Not a ppc403 */
  
@@ -162,10 +167,26 @@ void Install_clock(rtems_isr_entry clock_isr)
     else if ((pvr & 0xff00) == 0x0100) /* 403GB */
       auto_restart = 1;
  
+#else /* ppc405 */
+    asm volatile ("mfdcr %0, 0x0b2" : "=r" (iocr));  /*405GP CPC0_CR1 */
+    if (rtems_cpu_configuration_get_timer_internal_clock()) {
+	iocr &=~0x800000	;/* timer clocked from system clock CETE*/
+    }
+    else {
+	iocr |= 0x800000; /* select external timer clock CETE*/
+    }
+    asm volatile ("mtdcr 0x0b2, %0" : "=r" (iocr) : "0" (iocr)); /* 405GP CPC0_CR1 */
+
+     /*
+      * Enable auto restart
+      */
+
+    auto_restart=1;
+
+#endif /* ppc405 */
     pit_value = rtems_configuration_get_microseconds_per_tick() *
       rtems_cpu_configuration_get_clicks_per_usec();
  
-
     /*
      * initialize the interval here
      * First tick is set to right amount of time in the future
@@ -176,16 +197,19 @@ void Install_clock(rtems_isr_entry clock_isr)
 
     rtems_interrupt_catch(clock_isr, PPC_IRQ_PIT, &previous_isr);
 
+     /*
+      * Set PIT value
+      */
+
     asm volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */
  
-    asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
- 
-    tcr &= ~ 0x04400000;
- 
-    tcr |= (auto_restart ? 0x04400000 : 0x04000000);
- 
+     /*     
+      * Set timer to autoreload, bit TCR->ARE = 1  0x0400000
+      * Enable PIT interrupt, bit TCR->PIE = 1     0x4000000
+      */
     tick_time = get_itimer() + pit_value;
- 
+    asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */ 
+    tcr = (tcr & ~0x04400000) | (auto_restart ? 0x04400000 : 0x04000000);
     asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
 
     atexit(Clock_exit);
@@ -208,6 +232,9 @@ ReInstall_clock(rtems_isr_entry new_clock_isr)
 /*
  * Called via atexit()
  * Remove the clock interrupt handler by setting handler to NULL
+ *
+ * This will not work on the 405GP because 
+ * when bit's are set in TCR they can only be unset by a reset 
  */
 
 void