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author | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-12-02 14:31:19 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-12-02 14:31:19 +0000 |
commit | acc25eec35e186abc118b9ca4f097e22fc6b4846 (patch) | |
tree | 7fa75871c51372e70cbd9cb50b0a2fab55cfa750 /c/src/lib/libcpu/powerpc/old-exceptions/ppccache.c | |
parent | Merged of mcp750 and mvme2307 BSP by Eric Valette <valette@crf.canon.fr>. (diff) | |
download | rtems-acc25eec35e186abc118b9ca4f097e22fc6b4846.tar.bz2 |
Merged of mcp750 and mvme2307 BSP by Eric Valette <valette@crf.canon.fr>.
As part of this effort, the mpc750 libcpu code is now shared with the
ppc6xx.
Diffstat (limited to 'c/src/lib/libcpu/powerpc/old-exceptions/ppccache.c')
-rw-r--r-- | c/src/lib/libcpu/powerpc/old-exceptions/ppccache.c | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/powerpc/old-exceptions/ppccache.c b/c/src/lib/libcpu/powerpc/old-exceptions/ppccache.c new file mode 100644 index 0000000000..ecfb4b96ca --- /dev/null +++ b/c/src/lib/libcpu/powerpc/old-exceptions/ppccache.c @@ -0,0 +1,61 @@ +/* + * PowerPC Cache enable routines + * + * $Id$ + */ + +#include <rtems/system.h> + +#define PPC_Get_HID0( _value ) \ + do { \ + _value = 0; /* to avoid warnings */ \ + asm volatile( \ + "mfspr %0, 0x3f0;" /* get HID0 */ \ + "isync" \ + : "=r" (_value) \ + : "0" (_value) \ + ); \ + } while (0) + +#define PPC_Set_HID0( _value ) \ + do { \ + asm volatile( \ + "isync;" \ + "mtspr 0x3f0, %0;" /* load HID0 */ \ + "isync" \ + : "=r" (_value) \ + : "0" (_value) \ + ); \ + } while (0) + + +void powerpc_instruction_cache_enable () +{ + unsigned32 value; + + /* + * Enable the instruction cache + */ + + PPC_Get_HID0( value ); + + value |= 0x00008000; /* Set ICE bit */ + + PPC_Set_HID0( value ); +} + +void powerpc_data_cache_enable () +{ + unsigned32 value; + + /* + * enable data cache + */ + + PPC_Get_HID0( value ); + + value |= 0x00004000; /* set DCE bit */ + + PPC_Set_HID0( value ); +} + |