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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-08-01 16:36:55 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-08-09 23:02:43 +0200 |
| commit | c6c998b000afa2a221de6dc02a82a36f5652ef06 (patch) | |
| tree | bc1fe5e4c178af4d0a1693e50109a6557c96a822 /c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S | |
| parent | score: Per-CPU thread dispatch disable level (diff) | |
| download | rtems-c6c998b000afa2a221de6dc02a82a36f5652ef06.tar.bz2 | |
bsps/powerpc: Per-CPU thread dispatch disable
Interrupt support for per-CPU thread dispatch disable level.
Diffstat (limited to 'c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S | 51 |
1 files changed, 14 insertions, 37 deletions
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S index 399c227ad3..7014530251 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S @@ -17,7 +17,7 @@ #include <bsp/vectors.h> #define VECTOR_REGISTER r4 -#define ISR_NEST_HADDR_REGISTER r5 +#define SELF_CPU_REGISTER r5 #define ISR_NEST_REGISTER r6 #define DISPATCH_LEVEL_REGISTER r7 #define HANDLER_REGISTER r8 @@ -30,7 +30,7 @@ #define FRAME_REGISTER r14 #define VECTOR_OFFSET(reg) GPR4_OFFSET(reg) -#define ISR_NEST_HADDR_OFFSET(reg) GPR5_OFFSET(reg) +#define SELF_CPU_OFFSET(reg) GPR5_OFFSET(reg) #define ISR_NEST_OFFSET(reg) GPR6_OFFSET(reg) #define DISPATCH_LEVEL_OFFSET(reg) GPR7_OFFSET(reg) #define HANDLER_OFFSET(reg) GPR8_OFFSET(reg) @@ -85,12 +85,12 @@ ppc_exc_wrap_async_normal: mr FRAME_REGISTER, r1 /* Load ISR nest level and thread dispatch disable level */ - PPC_GPR_STORE ISR_NEST_HADDR_REGISTER, ISR_NEST_HADDR_OFFSET(r1) - lis ISR_NEST_HADDR_REGISTER, ISR_NEST_LEVEL@ha + PPC_GPR_STORE SELF_CPU_REGISTER, SELF_CPU_OFFSET(r1) + GET_SELF_CPU_CONTROL SELF_CPU_REGISTER PPC_GPR_STORE ISR_NEST_REGISTER, ISR_NEST_OFFSET(r1) - lwz ISR_NEST_REGISTER, ISR_NEST_LEVEL@l(ISR_NEST_HADDR_REGISTER) + lwz ISR_NEST_REGISTER, PER_CPU_ISR_NEST_LEVEL(SELF_CPU_REGISTER) PPC_GPR_STORE DISPATCH_LEVEL_REGISTER, DISPATCH_LEVEL_OFFSET(r1) - lwz DISPATCH_LEVEL_REGISTER, _Thread_Dispatch_disable_level@sdarel(r13) + lwz DISPATCH_LEVEL_REGISTER, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(SELF_CPU_REGISTER) PPC_GPR_STORE SCRATCH_0_REGISTER, SCRATCH_0_OFFSET(r1) @@ -152,13 +152,12 @@ ppc_exc_wrap_async_normal: evstdd SCRATCH_1_REGISTER, PPC_EXC_ACC_OFFSET(r1) #endif -#ifndef RTEMS_SMP /* Increment ISR nest level and thread dispatch disable level */ cmpwi ISR_NEST_REGISTER, 0 addi ISR_NEST_REGISTER, ISR_NEST_REGISTER, 1 addi DISPATCH_LEVEL_REGISTER, DISPATCH_LEVEL_REGISTER, 1 - stw ISR_NEST_REGISTER, ISR_NEST_LEVEL@l(ISR_NEST_HADDR_REGISTER) - stw DISPATCH_LEVEL_REGISTER, _Thread_Dispatch_disable_level@sdarel(r13) + stw ISR_NEST_REGISTER, PER_CPU_ISR_NEST_LEVEL(SELF_CPU_REGISTER) + stw DISPATCH_LEVEL_REGISTER, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(SELF_CPU_REGISTER) /* Switch stack if necessary */ mfspr SCRATCH_0_REGISTER, SPRG1 @@ -181,9 +180,9 @@ ppc_exc_wrap_async_normal: #endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */ /* Load ISR nest level and thread dispatch disable level */ - lis ISR_NEST_HADDR_REGISTER, ISR_NEST_LEVEL@ha - lwz ISR_NEST_REGISTER, ISR_NEST_LEVEL@l(ISR_NEST_HADDR_REGISTER) - lwz DISPATCH_LEVEL_REGISTER, _Thread_Dispatch_disable_level@sdarel(r13) + GET_SELF_CPU_CONTROL SELF_CPU_REGISTER + lwz ISR_NEST_REGISTER, PER_CPU_ISR_NEST_LEVEL(SELF_CPU_REGISTER) + lwz DISPATCH_LEVEL_REGISTER, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(SELF_CPU_REGISTER) /* * Switch back to original stack (FRAME_REGISTER == r1 if we are still @@ -195,30 +194,8 @@ ppc_exc_wrap_async_normal: /* Decrement ISR nest level and thread dispatch disable level */ subi ISR_NEST_REGISTER, ISR_NEST_REGISTER, 1 subic. DISPATCH_LEVEL_REGISTER, DISPATCH_LEVEL_REGISTER, 1 - stw ISR_NEST_REGISTER, ISR_NEST_LEVEL@l(ISR_NEST_HADDR_REGISTER) - stw DISPATCH_LEVEL_REGISTER, _Thread_Dispatch_disable_level@sdarel(r13) -#else /* RTEMS_SMP */ - /* ISR Enter */ - bl _ISR_SMP_Enter - cmpwi r3, 0 - - /* Switch stack if necessary */ - mfspr SCRATCH_0_REGISTER, SPRG1 - iselgt r1, r1, SCRATCH_0_REGISTER - - bl bsp_interrupt_dispatch - - /* - * Switch back to original stack (FRAME_REGISTER == r1 if we are still - * on the IRQ stack) and restore FRAME_REGISTER. - */ - mr r1, FRAME_REGISTER - lwz FRAME_REGISTER, FRAME_OFFSET(r1) - - /* ISR Leave */ - bl _ISR_SMP_Exit - cmpwi r3, 1 -#endif /* RTEMS_SMP */ + stw ISR_NEST_REGISTER, PER_CPU_ISR_NEST_LEVEL(SELF_CPU_REGISTER) + stw DISPATCH_LEVEL_REGISTER, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(SELF_CPU_REGISTER) /* Call thread dispatcher if necessary */ bne thread_dispatching_done @@ -240,7 +217,7 @@ thread_dispatching_done: lwz SCRATCH_5_REGISTER, EXC_LR_OFFSET(r1) PPC_GPR_LOAD VECTOR_REGISTER, VECTOR_OFFSET(r1) - PPC_GPR_LOAD ISR_NEST_HADDR_REGISTER, ISR_NEST_HADDR_OFFSET(r1) + PPC_GPR_LOAD SELF_CPU_REGISTER, SELF_CPU_OFFSET(r1) PPC_GPR_LOAD ISR_NEST_REGISTER, ISR_NEST_OFFSET(r1) #ifdef __SPE__ |