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| author | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2009-11-03 18:45:04 +0000 |
|---|---|---|
| committer | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2009-11-03 18:45:04 +0000 |
| commit | e08dbc5ea9ec881b6fc93cf926c18fb094d3bd55 (patch) | |
| tree | 465630c9bb6a962362ed043b9bb0bc4c5505a3a5 /c/src/lib/libcpu/powerpc/mpc8xx | |
| parent | 2009-11-03 Ralf Corsépius <ralf.corsepius@rtems.org> (diff) | |
| download | rtems-e08dbc5ea9ec881b6fc93cf926c18fb094d3bd55.tar.bz2 | |
various PowerPC code maintenance
Diffstat (limited to 'c/src/lib/libcpu/powerpc/mpc8xx')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c b/c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c index b2d1a5bf58..4fa55701cd 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c +++ b/c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c @@ -50,8 +50,11 @@ void mmu_init( void ) * Initialize IMMU & DMMU Control Registers (MI_CTR & MD_CTR) * GPM [0] 0b0 = PowerPC mode * PPM [1] 0b0 = Page resolution of protection - * CIDEF [2] 0b0/0b1 = Default cache-inhibit attribute = - * NO for IMMU, YES for DMMU! + * CIDEF [2] 0b0/0b0 = Default cache-inhibit attribute = + * NO for IMMU, NO for DMMU + * NOTE: it is vital that data caching is ON, when + * DMMU is off, otherwise valid/dirty values in + * cache would be ignored during exception entry * reserved/WTDEF [3] 0b0 = Default write-through attribute = not * RSV4x [4] 0b0 = 4 entries not reserved * reserved/TWAM [5] 0b0/0b1 = 4-Kbyte page hardware assist @@ -67,7 +70,7 @@ void mmu_init( void ) */ reg1 = M8xx_MI_CTR_ITLB_INDX(31); _mtspr( M8xx_MI_CTR, reg1 ); - reg1 = M8xx_MD_CTR_CIDEF | M8xx_MD_CTR_TWAM | M8xx_MD_CTR_DTLB_INDX(31); + reg1 = M8xx_MD_CTR_TWAM | M8xx_MD_CTR_DTLB_INDX(31); _mtspr( M8xx_MD_CTR, reg1 ); _isync; |