diff options
| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-12-02 14:00:01 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-12-02 14:00:01 +0000 |
| commit | e4ab88fde5ad3dc273fcee66b03c2892a2d80dac (patch) | |
| tree | c8c25da3957d445fb7ef0b0e8ce03e629d30feb8 /c/src/lib/libcpu/powerpc/mpc750/exceptions/asm_utils.S | |
| parent | Merged of mcp750 and mvme2307 BSP by Eric Valette <valette@crf.canon.fr>. (diff) | |
| download | rtems-e4ab88fde5ad3dc273fcee66b03c2892a2d80dac.tar.bz2 | |
Merged of mcp750 and mvme2307 BSP by Eric Valette <valette@crf.canon.fr>.
As part of this effort, the mpc750 libcpu code is now shared with the
ppc6xx.
Diffstat (limited to 'c/src/lib/libcpu/powerpc/mpc750/exceptions/asm_utils.S')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/mpc750/exceptions/asm_utils.S | 65 |
1 files changed, 0 insertions, 65 deletions
diff --git a/c/src/lib/libcpu/powerpc/mpc750/exceptions/asm_utils.S b/c/src/lib/libcpu/powerpc/mpc750/exceptions/asm_utils.S deleted file mode 100644 index f046915404..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc750/exceptions/asm_utils.S +++ /dev/null @@ -1,65 +0,0 @@ -/* - * asm_utils.s - * - * $Id$ - * - * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) - * - * This file contains the low-level support for moving exception - * exception code to appropriate location. - * - */ - -#include <libcpu/cpu.h> -#include <libcpu/io.h> -#include <rtems/score/targopts.h> -#include "asm.h" - - .globl codemove -codemove: - .type codemove,@function -/* r3 dest, r4 src, r5 length in bytes, r6 cachelinesize */ - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 7f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b - -/* Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. - */ -4: cmpwi r6,0 - add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ - subi r0,r6,1 - andc r3,r3,r0 - mr r4,r3 -5: cmplw r4,r5 - dcbst 0,r4 - add r4,r4,r6 - blt 5b - sync /* Wait for all dcbst to complete on bus */ - mr r4,r3 -6: cmplw r4,r5 - icbi 0,r4 - add r4,r4,r6 - blt 6b -7: sync /* Wait for all icbi to complete on bus */ - isync - blr |