Whitespace removal.

8 files changed, 118 insertions, 118 deletions

diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c b/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c
index ebf306a3e9..0f7fe86ef0 100644
--- a/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c
+++ b/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c
@@ -54,7 +54,7 @@ uint32_t   Clock_Decrementer_value;
 /*
  * These are set by clock driver during its init
  */
- 
+
 rtems_device_major_number rtems_clock_major = ~0;
 rtems_device_minor_number rtems_clock_minor;
 
@@ -214,12 +214,12 @@ void Clock_exit( void )
 {
   (void) BSP_disconnect_clock_handler ();
 }
- 
+
 uint32_t Clock_driver_nanoseconds_since_last_tick(void)
 {
   uint32_t clicks, tmp;
 
-  PPC_Get_decrementer( clicks ); 
+  PPC_Get_decrementer( clicks );
 
   /*
    * Multiply by 1000 here separately from below so we do not overflow
@@ -257,7 +257,7 @@ rtems_interrupt_level l,tcr;
   Clock_Decrementer_value = (BSP_bus_frequency/BSP_time_base_divisor)*
             (rtems_configuration_get_microseconds_per_tick()/1000);
 
-  /* set the decrementer now, prior to installing the handler 
+  /* set the decrementer now, prior to installing the handler
    * so no interrupts will happen in a while.
    */
   PPC_Set_decrementer( (unsigned)-1 );
@@ -298,7 +298,7 @@ rtems_interrupt_level l,tcr;
     rtems_fatal_error_occurred(1);
   }
   /* make major/minor avail to others such as shared memory driver */
- 
+
   rtems_clock_major = major;
   rtems_clock_minor = minor;
 
diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/exceptions/asm_utils.S b/c/src/lib/libcpu/powerpc/mpc6xx/exceptions/asm_utils.S
index 30bda4face..34fc13092e 100644
--- a/c/src/lib/libcpu/powerpc/mpc6xx/exceptions/asm_utils.S
+++ b/c/src/lib/libcpu/powerpc/mpc6xx/exceptions/asm_utils.S
@@ -25,11 +25,11 @@ codemove:
 	beq	7f	/* Protect against 0 count */
 	mtctr	r0
 	bge	cr1,2f
-	
+
 	la	r8,-4(r4)
 	la	r7,-4(r3)
 1:	lwzu	r0,4(r8)
-	stwu	r0,4(r7)	
+	stwu	r0,4(r7)
 	bdnz	1b
 	b	4f
 
@@ -39,23 +39,23 @@ codemove:
 3:	lwzu	r0,-4(r8)
 	stwu	r0,-4(r7)
 	bdnz	3b
-	
+
 /* Now flush the cache:	note that we must start from a cache aligned
- * address. Otherwise we might miss one cache line. 
+ * address. Otherwise we might miss one cache line.
  */
 4:	cmpwi	r6,0
 	add	r5,r3,r5
-	beq	7f	/* Always flush prefetch queue in any case */ 
+	beq	7f	/* Always flush prefetch queue in any case */
 	subi	r0,r6,1
 	andc	r3,r3,r0
 	mr	r4,r3
-5:	cmplw	r4,r5	
+5:	cmplw	r4,r5
 	dcbst	0,r4
 	add	r4,r4,r6
 	blt	5b
 	sync		/* Wait for all dcbst to complete on bus */
 	mr	r4,r3
-6:	cmplw	r4,r5	
+6:	cmplw	r4,r5
 	icbi	0,r4
 	add	r4,r4,r6
 	blt	6b
diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c
index 0c85143c5d..f5119800fb 100644
--- a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c
+++ b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c
@@ -6,7 +6,7 @@
  *	    More detailed information can be found on motorola
  *	    site and more precisely in the following book :
  *
- *		MPC750 
+ *		MPC750
  *		Risc Microporcessor User's Manual
  *		Mtorola REF : MPC750UM/AD 8/97
  *
@@ -380,7 +380,7 @@ setbat (int typ, int bat_index, unsigned long virt, unsigned long phys,
       init_done = 1;
     }
   }
-  
+
   err = check_overlap (typ, virt, size);
   if ((size >= (1 << 17)) && (err >= 0) && (err != bat_index)) {
     rtems_interrupt_enable (level);
diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h
index 1f86dab66e..b5141686dd 100644
--- a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h
+++ b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h
@@ -6,7 +6,7 @@
  *	    More detailed information can be found on motorola
  *	    site and more precisely in the following book :
  *
- *		MPC750 
+ *		MPC750
  *		Risc Microporcessor User's Manual
  *		Motorola REF : MPC750UM/AD 8/97
  *
@@ -57,7 +57,7 @@ extern int setibat(int bat_index, unsigned long virt, unsigned long phys,
 
 /* read DBAT # 'idx' into *pu / *pl. NULL pointers may be passed.
  * If pu and pl are NULL, the bat contents are dumped to the console (printk).
- * 
+ *
  * RETURNS: upper BAT contents or (-1) if index is invalid
  */
 extern int getdbat(int bat_index, unsigned long *pu, unsigned long *pl);
diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S
index 2df1c85c9a..1035ed6922 100644
--- a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S
+++ b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S
@@ -11,7 +11,7 @@
  *  The license and distribution terms for this file may be
  *  found in found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
- *	
+ *
  *  T. Straumann - 11/2001: added support for 7400 (no AltiVec yet)
  *  S.K. Feng    - 10/2003: added support for 7455 (no AltiVec yet)
  *
@@ -40,7 +40,7 @@
 #define PPC_860   0x50
 #define PPC_821   PPC_860
 #define PPC_8260  0x81
-#define PPC_8240  PPC_8260 
+#define PPC_8240  PPC_8260
 
 /* ALTIVEC instructions (not recognized by off-the shelf gcc yet) */
 #define DSSALL	.long	0x7e00066c		/* DSSALL altivec instruction opcode */
@@ -54,13 +54,13 @@
 
 #define DL1HWF	(1<<(31-8))
 #define L2HWF	(1<<(31-20))
-	
+
 #FIXME Should really move this to C code
 
 	.globl L1_caches_enables
 	.type  L1_caches_enables, @function
-	
-L1_caches_enables:	
+
+L1_caches_enables:
 	/*
 	 * Enable caches and 604-specific features if necessary.
 	 */
@@ -87,15 +87,15 @@ L1_caches_enables:
 	cror	6,6,10
 	cror	6,6,14
 	cmpi	2,r9,PPC_750	/* or 750 */
-	cror	6,6,10	
+	cror	6,6,10
 	cmpi	2,r9,PPC_7400	/* or 7400 */
-	cror	6,6,10		
+	cror	6,6,10
 	cmpli   0,r9,PPC_7455   /* or 7455 */
 	beq     1f
 	cmpli   0,r9,PPC_7457   /* or 7457 */
 	bne		2f
 1:
-	/* 7455:link register stack,branch folding & 
+	/* 7455:link register stack,branch folding &
 	 * TBEN : enable the time base and decrementer.
 	 * EMCP bit is defined in HID1. However, it's not used
 	 * in mvme5500 board because of GT64260 (e.g. it's connected
@@ -103,7 +103,7 @@ L1_caches_enables:
 	 */
 	oris    r11,r11,(HID0_LRSTK|HID0_FOLD|HID0_TBEN)@h
 	ori     r11,r11,(HID0_LRSTK|HID0_FOLD|HID0_TBEN)@l
-2:	cror    2,2,10	
+2:	cror    2,2,10
 	bne	3f
 	ori	r11,r11,HID0_BTIC	/* enable branch tgt cache on 7400 , 7455 , 7457 */
 3:	cror	2,2,6
@@ -119,14 +119,14 @@ L1_caches_enables:
 	blr
 
 	.globl get_L1CR
-.type  get_L1CR, @function	
+.type  get_L1CR, @function
 get_L1CR:
 	mfspr   r3,HID0
 	blr
-			
+
 	.globl get_L2CR
-	.type  get_L2CR, @function	
-get_L2CR:	
+	.type  get_L2CR, @function
+get_L2CR:
 	/* Make sure this is a > 750 chip */
 	mfspr	r3,PVR
 	rlwinm	r3,r3,16,16,31
@@ -135,12 +135,12 @@ get_L2CR:
 	cmplwi  r3,PPC_7400	/* it's a 7400 */
 	beq	1f
 	cmplwi  r3,PPC_7455	/* it's a 7455 */
-	beq	1f	
+	beq	1f
 	cmplwi  r3,PPC_7457	/* it's a 7457 */
-	beq	1f	
+	beq	1f
 	li	r3,-1
 	blr
-	
+
 1:
 	/* Return the L2CR contents */
 	mfspr	r3,L2CR
@@ -148,18 +148,18 @@ get_L2CR:
 
 	.globl set_L2CR
 	.type  set_L2CR, @function
-set_L2CR:	
+set_L2CR:
 	/* Usage:
-	 * When setting the L2CR register, you must do a few special things.  
-	 * If you are enabling the cache, you must perform a global invalidate. 
+	 * When setting the L2CR register, you must do a few special things.
+	 * If you are enabling the cache, you must perform a global invalidate.
 	 * If you are disabling the cache, you must flush the cache contents first.
 	 * This routine takes care of doing these things.  When first
-	 * enabling the cache, make sure you pass in the L2CR you want, as well as 
-	 * passing in the global invalidate bit set.  A global invalidate will 
-	 * only be performed if the L2I bit is set in applyThis.  When enabling 
+	 * enabling the cache, make sure you pass in the L2CR you want, as well as
+	 * passing in the global invalidate bit set.  A global invalidate will
+	 * only be performed if the L2I bit is set in applyThis.  When enabling
 	 * the cache, you should also set the L2E bit in applyThis.  If you
-	 * want to modify the L2CR contents after the cache has been enabled, 
-	 * the recommended procedure is to first call __setL2CR(0) to disable 
+	 * want to modify the L2CR contents after the cache has been enabled,
+	 * the recommended procedure is to first call __setL2CR(0) to disable
 	 * the cache and then call it again with the new values for L2CR.  Examples:
 	 *
 	 *	_setL2CR(0)		-	disables the cache
@@ -171,13 +171,13 @@ set_L2CR:
 	 *				-	L2I set to perform a global invalidation
 	 *				-	L2OH set to 1 nS
 	 *
-	 * A similar call should work for your card.  You need to know the correct 
-	 * setting for your card and then place them in the fields I have outlined 
-	 * above.  Other fields support optional features, such as L2DO which caches 
-	 * only data, or L2TS which causes cache pushes from the L1 cache to go to 
+	 * A similar call should work for your card.  You need to know the correct
+	 * setting for your card and then place them in the fields I have outlined
+	 * above.  Other fields support optional features, such as L2DO which caches
+	 * only data, or L2TS which causes cache pushes from the L1 cache to go to
 	 *the L2 cache instead of to main memory.
 	 */
-	
+
 	/* Make sure this is a > 750 chip */
 	mfspr	r0,PVR
 	rlwinm	r0,r0,16,16,31
@@ -186,17 +186,17 @@ set_L2CR:
 	cmplwi	r0,PPC_7400
 	beq	thisIs750
 	cmplwi	r0,PPC_7455
-	beq	thisIs750	
+	beq	thisIs750
 	cmplwi	r0,PPC_7457
-	beq	thisIs750	
+	beq	thisIs750
 	li	r3,-1
 	blr
-	
+
 thisIs750:
 	/* Get the current enable bit of the L2CR into r4 */
 	mfspr	r4,L2CR
 	rlwinm	r4,r4,0,0,0
-	
+
 	/* See if we want to perform a global inval this time. */
 	rlwinm	r6,r3,0,10,10		/* r6 contains the new invalidate bit */
 	rlwinm.	r5,r3,0,0,0		/* r5 contains the new enable bit */
@@ -209,7 +209,7 @@ thisIs750:
 	mtmsr	r4
 	bne	dontDisableCache	/* Only disable the cache if L2CRApply has the enable bit off */
 
-	cmplwi  r0,PPC_7400		/* 7400 ? */ 
+	cmplwi  r0,PPC_7400		/* 7400 ? */
 	bne	disableCache		/* use traditional method */
 
 	/* On the 7400, they recommend using the hardware flush feature */
@@ -241,18 +241,18 @@ disableCache:
 	mtmsr	r4
 	sync
 	isync
-	mfspr	r4, MSSCR0	
+	mfspr	r4, MSSCR0
 	rlwinm	r4,r4,0,29,0		/* Turn off the L2PFE bits */
 	mtspr	MSSCR0, r4
-	sync	
+	sync
 	/* flush L1 first */
 	lis	r4,0x0001
 	mtctr	r4
 	li	r4,0
-	li      r0,0 
+	li      r0,0
 loadFlush:
 	lwzx	r0,r0,r4
-	dcbf	r0,r4	
+	dcbf	r0,r4
 	addi	r4,r4,CACHE_LINE_SIZE	/* Go to start of next cache line */
 	bdnz	loadFlush
 	sync
@@ -269,8 +269,8 @@ loadFlush:
 	sync
 	/* L2 flushed,L2IO & L2DO got cleared in the dontDisableCache:  */
 	b	reenableDR
-	
-not745x:			
+
+not745x:
 	sync
 	mtmsr	r4
 	isync
@@ -286,7 +286,7 @@ loadLoop:
 	lwzx	r0,r0,r4
 	addi	r4,r4,CACHE_LINE_SIZE	/* Go to start of next cache line */
 	bdnz	loadLoop
-	
+
 	/* Now, flush the first 2MB of memory */
 	lis		r4,0x0001
 	mtctr	r4
@@ -296,17 +296,17 @@ flushLoop:
 	dcbf	r0,r4
 	addi	r4,r4,CACHE_LINE_SIZE	/* Go to start of next cache line */
 	bdnz	flushLoop
-reenableDR:	
+reenableDR:
 	rlwinm	r4,r7,0,17,15		/* still mask EE but reenable data relocation */
 	sync
 	mtmsr	r4
 	isync
 
 flushDone:
-	
+
 	/* Turn off the L2CR enable bit. */
 	rlwinm	r3,r3,0,1,31
-	
+
 dontDisableCache:
 	/* Set up the L2CR configuration bits */
 	sync
@@ -314,7 +314,7 @@ dontDisableCache:
 	sync
 	cmplwi	r6,0
 	beq	noInval
-	
+
 	/* Perform a global invalidation */
 	oris	r3,r3,0x0020
 	sync
@@ -324,11 +324,11 @@ invalCompleteLoop:				/* Wait for the invalidation to complete */
 	mfspr	r3,L2CR
 	rlwinm.	r4,r3,0,31,31
 	bne	invalCompleteLoop
-	
+
 	rlwinm	r3,r3,0,11,9;		/* Turn off the L2I bit */
 	sync
 	mtspr	L2CR,r3
-	
+
 noInval:
 	sync
 	/* re-enable interrupts, i.e. restore original MSR */
@@ -336,7 +336,7 @@ noInval:
 	/* See if we need to enable the cache */
 	cmplwi	r5,0
 	beqlr
-	
+
 enableCache:
 	/* Enable the cache */
 	oris	r3,r3,0x8000
@@ -344,20 +344,20 @@ enableCache:
 	sync
 	blr
 
-	
+
 	.globl get_L3CR
-	.type  get_L3CR, @function	
-get_L3CR:	
+	.type  get_L3CR, @function
+get_L3CR:
 	/* Make sure this is a 7455 chip */
 	mfspr	r3,PVR
 	rlwinm	r3,r3,16,16,31
 	cmplwi  r3,PPC_7455	/* it's a 7455 */
-	beq	1f	
+	beq	1f
 	cmplwi  r3,PPC_7457	/* it's a 7457 */
-	beq	1f	
+	beq	1f
 	li	r3,-1
 	blr
-	
+
 1:
 	/* Return the L3CR contents */
 	mfspr	r3,L3CR
@@ -365,34 +365,34 @@ get_L3CR:
 
 	.globl set_L3CR
 	.type  set_L3CR, @function
-set_L3CR:	
+set_L3CR:
 	/* Usage:
-	 * When setting the L3CR register, you must do a few special things.  
+	 * When setting the L3CR register, you must do a few special things.
 	 * If you are enabling the cache, you must perform a global invalidate.
 	 * Then call cpu_enable_l3cr(l3cr).
 	 * If you are disabling the cache, you must flush the cache contents first.
 	 * This routine takes care of doing these things.  If you
-	 * want to modify the L3CR contents after the cache has been enabled, 
-	 * the recommended procedure is to first call __setL3CR(0) to disable 
-	 * the cache and then call cpu_enable_l3cr with the new values for 
+	 * want to modify the L3CR contents after the cache has been enabled,
+	 * the recommended procedure is to first call __setL3CR(0) to disable
+	 * the cache and then call cpu_enable_l3cr with the new values for
 	 * L3CR.
 	 */
-	
+
 	/* Make sure this is a 7455 chip */
 	mfspr	r0,PVR
 	rlwinm	r0,r0,16,16,31
 	cmplwi	r0,PPC_7455
-	beq	thisIs7455	
+	beq	thisIs7455
 	cmplwi	r0,PPC_7457
-	beq	thisIs7455	
+	beq	thisIs7455
 	li	r3,-1
 	blr
-	
+
 thisIs7455:
 	/* Get the current enable bit of the L3CR into r4 */
 	mfspr	r4,L3CR
 	rlwinm	r4,r4,0,0,0
-	
+
 	/* See if we want to perform a global inval this time. */
 	rlwinm	r6,r3,0,10,10		/* r6 contains the new invalidate bit */
 	rlwinm.	r5,r3,0,0,0		/* r5 contains the new enable bit */
@@ -411,7 +411,7 @@ thisIs7455:
 	sync
 	mtmsr	r4
 	isync				/* make sure memory accesses have completed */
-	/* 7455: L3 :	 hardware flush 	
+	/* 7455: L3 :	 hardware flush
 	 * Set the L3CR[L3IO & L3DO] bits to completely lock the L3 cache */
 	mfspr   r0, L3CR
 	lis     r4, L3CR_LOCK_745x@h
@@ -428,19 +428,19 @@ thisIs7455:
 	sync
 	mtmsr	r4
 	isync
-	
+
 	/* Turn off the L3CR enable bit. */
 	rlwinm	r3,r3,0,1,31
-	
-dontDisableL3Cache:		
+
+dontDisableL3Cache:
 	/* Set up the L3CR configuration bits */
 	sync
 	mtspr	L3CR,r3
 	sync
-ifL3Inval:	
+ifL3Inval:
 	cmplwi	r6,0
 	beq	noL3Inval
-	
+
 	/* Perform a global invalidation */
 	oris	r3,r3,0x0020
 	sync
@@ -450,19 +450,19 @@ invalCompleteL3:				/* Wait for the invalidation to complete */
 	mfspr	r3,L3CR
 	rlwinm.	r4,r3,0,31,31
 	bne	invalCompleteL3
-	
+
 	rlwinm	r3,r3,0,11,9;		/* Turn off the L3I bit */
 	sync
 	mtspr	L3CR,r3
 	sync
-	
+
 noL3Inval:
 	/* re-enable interrupts, i.e. restore original MSR */
 	mtmsr	r7					/* (no sync needed) */
 	/* See if we need to enable the cache */
 	cmplwi	r5,0
 	beqlr
-	
+
 enableL3Cache:
 	/* Enable the cache */
 	oris	r3,r3,0x8000
diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c
index a81ed2d119..d4a891c7dd 100644
--- a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c
+++ b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c
@@ -4,19 +4,19 @@
  * Purpose: allow write protection of text/ro-data
  */
 
-/* 
+/*
  * Authorship
  * ----------
  * This software was created by
  *     Till Straumann <strauman@slac.stanford.edu>, 4/2002, 2003, 2004,
  * 	   Stanford Linear Accelerator Center, Stanford University.
- * 
+ *
  * Acknowledgement of sponsorship
  * ------------------------------
  * This software was produced by
  *     the Stanford Linear Accelerator Center, Stanford University,
  * 	   under Contract DE-AC03-76SFO0515 with the Department of Energy.
- * 
+ *
  * Government disclaimer of liability
  * ----------------------------------
  * Neither the United States nor the United States Department of Energy,
@@ -25,18 +25,18 @@
  * completeness, or usefulness of any data, apparatus, product, or process
  * disclosed, or represents that its use would not infringe privately owned
  * rights.
- * 
+ *
  * Stanford disclaimer of liability
  * --------------------------------
  * Stanford University makes no representations or warranties, express or
  * implied, nor assumes any liability for the use of this software.
- * 
+ *
  * Stanford disclaimer of copyright
  * --------------------------------
  * Stanford University, owner of the copyright, hereby disclaims its
  * copyright and all other rights in this software.  Hence, anyone may
- * freely use it for any purpose without restriction.  
- * 
+ * freely use it for any purpose without restriction.
+ *
  * Maintenance of notices
  * ----------------------
  * In the interest of clarity regarding the origin and status of this
@@ -45,9 +45,9 @@
  * or distributed by the recipient and are to be affixed to any copy of
  * software made or distributed by the recipient that contains a copy or
  * derivative of this software.
- * 
+ *
  * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
- */ 
+ */
 
 /* Chose debugging options */
 #undef  DEBUG_MAIN              /* create a standalone (host) program for basic testing */
@@ -419,7 +419,7 @@ triv121PgTblInit (unsigned long base, unsigned ldSize)
    * for a new CPU variant and that it has hardware PTE lookup/
    * TLB replacement before adding it to this list.
    *
-   * NOTE: The 603 features no hardware PTE lookup - and 
+   * NOTE: The 603 features no hardware PTE lookup - and
    *       hence the page tables should NOT be used.
    *               Although lookup could be implemented in
    *               software this is probably not desirable
@@ -1024,7 +1024,7 @@ dumpPteg (unsigned long vsid, unsigned long pi, unsigned long hash)
  *
  * RETURNS: address of the first page for which no
  *          PTE was found (i.e. page index * page size)
- *          
+ *
  *          ON SUCCESS, the special value 0x0C0C ("OKOK")
  *          [which is not page aligned and hence is not
  *          a valid page address].
diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.h b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.h
index 6b9497106d..fef2f0b269 100644
--- a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.h
+++ b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.h
@@ -2,19 +2,19 @@
 #define _LIBCPU_PTE121_H
 /* $Id$ */
 
-/* 
+/*
  * Authorship
  * ----------
  * This software was created by
  *     Till Straumann <strauman@slac.stanford.edu>, 4/2002, 2003, 2004,
  * 	   Stanford Linear Accelerator Center, Stanford University.
- * 
+ *
  * Acknowledgement of sponsorship
  * ------------------------------
  * This software was produced by
  *     the Stanford Linear Accelerator Center, Stanford University,
  * 	   under Contract DE-AC03-76SFO0515 with the Department of Energy.
- * 
+ *
  * Government disclaimer of liability
  * ----------------------------------
  * Neither the United States nor the United States Department of Energy,
@@ -23,18 +23,18 @@
  * completeness, or usefulness of any data, apparatus, product, or process
  * disclosed, or represents that its use would not infringe privately owned
  * rights.
- * 
+ *
  * Stanford disclaimer of liability
  * --------------------------------
  * Stanford University makes no representations or warranties, express or
  * implied, nor assumes any liability for the use of this software.
- * 
+ *
  * Stanford disclaimer of copyright
  * --------------------------------
  * Stanford University, owner of the copyright, hereby disclaims its
  * copyright and all other rights in this software.  Hence, anyone may
- * freely use it for any purpose without restriction.  
- * 
+ * freely use it for any purpose without restriction.
+ *
  * Maintenance of notices
  * ----------------------
  * In the interest of clarity regarding the origin and status of this
@@ -43,9 +43,9 @@
  * or distributed by the recipient and are to be affixed to any copy of
  * software made or distributed by the recipient that contains a copy or
  * derivative of this software.
- * 
+ *
  * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
- */ 
+ */
 
 /* Rudimentary page/hash table support for Powerpc
  *
@@ -56,7 +56,7 @@
  *
  * PURPOSE:
  *    1) allow write-protection of text/read-only data areas
- *    2) provide more effective-address space in case 
+ *    2) provide more effective-address space in case
  *       the BATs are not enough
  *    3) allow 'alias' mappings. Such aliases can only use
  *       the upper bits of the VSID since VSID & 0xf and the
@@ -67,7 +67,7 @@
  *       be big enough!.
  *    -  only one page table supported.
  *    -  no locking implemented. If multiple threads modify
- *       the page table, it is the user's responsibility to 
+ *       the page table, it is the user's responsibility to
  *       implement exclusive access.
  */
 
@@ -92,7 +92,7 @@ typedef struct PTERec_ {
  * RETURNS: a handle to the internal data structure
  *          used to manage the page table. NULL on
  *          error.
- *          
+ *
  * NOTES:   - 'base' must be aligned to the size
  *          - minimal ldSize is 16 (== 64k)
  *          - this routine maps the page table itself
@@ -100,7 +100,7 @@ typedef struct PTERec_ {
  *            the CPU from overwriting the page table,
  *            it can still be corrupted by PCI bus masters
  *            (like DMA engines, [VME] bridges etc.) and
- *            even by this CPU if either the MMU is off 
+ *            even by this CPU if either the MMU is off
  *            or if there is a DBAT mapping granting write
  *            access...
  */
@@ -118,7 +118,7 @@ triv121PgTblInit(unsigned long base, unsigned ldSize);
  *  ldSize = triv121PgTblLdMinSize(memsize);
  *  memsize -= (1<<ldSize);  / * reduce memory available to RTEMS * /
  *  pgTbl  = triv121PgTblInit(memsize,ldSize);
- * 
+ *
  */
 unsigned long
 triv121PgTblLdMinSize(unsigned long size);
@@ -167,7 +167,7 @@ triv121PgTblMap(
   unsigned protection      /* 'pp' access protection: Super      User
                             *
                             *   0                      r/w       none
-                            *   1                      r/w       ro   
+                            *   1                      r/w       ro
                             *   2                      r/w       r/w
                             *   3                      ro        ro
                             */
@@ -231,7 +231,7 @@ APte triv121DumpEa(unsigned long ea);
  */
 APte triv121FindPte(unsigned long vsid, unsigned long pi);
 
-/* 
+/*
  * Unmap an effective address
  *
  * RETURNS: pte that mapped the ea or NULL if no
@@ -239,7 +239,7 @@ APte triv121FindPte(unsigned long vsid, unsigned long pi);
  */
 APte triv121UnmapEa(unsigned long ea);
 
-/* 
+/*
  * Change the WIMG and PP attributes of the page containing 'ea'
  *
  * NOTES:   The 'wimg' and 'pp' may be <0 to indicate that no
diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/timer/timer.c b/c/src/lib/libcpu/powerpc/mpc6xx/timer/timer.c
index bc9ed1e7b2..f32f6b572e 100644
--- a/c/src/lib/libcpu/powerpc/mpc6xx/timer/timer.c
+++ b/c/src/lib/libcpu/powerpc/mpc6xx/timer/timer.c
@@ -42,7 +42,7 @@ int Timer_get_clicks_overhead(void)
 }
 
 /*
- * benchmark_timer_initialize 
+ * benchmark_timer_initialize
  */
 void benchmark_timer_initialize(void)
 {