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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2011-08-24 09:45:20 +0000 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2011-08-24 09:45:20 +0000 |
| commit | 1d367a49dfd1d8f1b81a3139974148a0b6bf82dc (patch) | |
| tree | bee2e164034bce352db325ad3cd09de5b5645c9e /c/src/lib/libcpu/powerpc/mpc6xx | |
| parent | 2011-08-24 Sebastian Huber <sebastian.huber@embedded-brains.de> (diff) | |
| download | rtems-1d367a49dfd1d8f1b81a3139974148a0b6bf82dc.tar.bz2 | |
2011-08-24 Sebastian Huber <sebastian.huber@embedded-brains.de>
* mpc6xx/clock/c_clock.c, mpc6xx/mmu/mmuAsm.S,
new-exceptions/bspsupport/ppc_exc_global_handler.c,
shared/include/cpuIdent.c, shared/src/stack.c: Update due to API
changes.
Diffstat (limited to 'c/src/lib/libcpu/powerpc/mpc6xx')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c | 1 | ||||
| -rw-r--r-- | c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S | 12 |
2 files changed, 6 insertions, 7 deletions
diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c b/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c index 9983a78fdb..afb75c79e4 100644 --- a/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c +++ b/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c @@ -35,7 +35,6 @@ SPR_RW(BOOKE_TCR) SPR_RW(BOOKE_TSR) SPR_RW(BOOKE_DECAR) -SPR_RW(DEC) extern int BSP_connect_clock_handler (void); diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S index 354dd352fb..645e9d7509 100644 --- a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S +++ b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S @@ -64,7 +64,7 @@ L1_caches_enables: /* * Enable caches and 604-specific features if necessary. */ - mfspr r9,PVR + mfspr r9,PPC_PVR rlwinm r9,r9,16,16,31 cmpi 0,r9,PPC_601 beq 4f /* not needed for 601 */ @@ -128,7 +128,7 @@ get_L1CR: .type get_L2CR, @function get_L2CR: /* Make sure this is a > 750 chip */ - mfspr r3,PVR + mfspr r3,PPC_PVR rlwinm r3,r3,16,16,31 cmplwi r3,PPC_750 /* it's a 750 */ beq 1f @@ -179,7 +179,7 @@ set_L2CR: */ /* Make sure this is a > 750 chip */ - mfspr r0,PVR + mfspr r0,PPC_PVR rlwinm r0,r0,16,16,31 cmplwi r0,PPC_750 beq thisIs750 @@ -349,7 +349,7 @@ enableCache: .type get_L3CR, @function get_L3CR: /* Make sure this is a 7455 chip */ - mfspr r3,PVR + mfspr r3,PPC_PVR rlwinm r3,r3,16,16,31 cmplwi r3,PPC_7455 /* it's a 7455 */ beq 1f @@ -379,7 +379,7 @@ set_L3CR: */ /* Make sure this is a 7455 chip */ - mfspr r0,PVR + mfspr r0,PPC_PVR rlwinm r0,r0,16,16,31 cmplwi r0,PPC_7455 beq thisIs7455 @@ -482,7 +482,7 @@ enableL3Cache: .type CPU_clear_bats_early,@function CPU_clear_bats_early: li r3,0 - mfspr r4,PVR + mfspr r4,PPC_PVR rlwinm r4,r4,16,16,31 /* r4 = 1 for 601, 4 for 604 */ cmpwi r4, 1 sync |