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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2012-05-18 15:47:23 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2012-06-04 09:54:31 +0200 |
| commit | 1869bb7101de25205f325287419aaa25a13143c7 (patch) | |
| tree | 99dd5d871ed47673a9e95a9ba5f8d5ff791e31a3 /c/src/lib/libcpu/powerpc/mpc6xx | |
| parent | Fix C files which had two semi-colons at EOL (diff) | |
| download | rtems-1869bb7101de25205f325287419aaa25a13143c7.tar.bz2 | |
powerpc: Simplify context switch
PowerPC cores with the SPE (Signal Processing Extension) have 64-bit
general-purpose registers. The SPE context switch code has been merged
with the standard context switch code. The context switch may use cache
operations to increase the performance. It will be ensured that the
context is 32-byte aligned (PPC_DEFAULT_CACHE_LINE_SIZE). This
increases the overall memory size of the context area in the thread
control block slightly. The general-purpose registers GPR2 and GPR13
are no longer part of the context. The BSP must initialize these
registers during startup (usually initialized by the __eabi() function).
The new BSP option BSP_USE_DATA_CACHE_BLOCK_TOUCH can be used to enable
the dcbt instruction in the context switch.
The new BSP option BSP_USE_SYNC_IN_CONTEXT_SWITCH can be used to enable
sync and isync instructions in the context switch. This should be not
necessary in most cases.
Diffstat (limited to 'c/src/lib/libcpu/powerpc/mpc6xx')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c | 2 | ||||
| -rw-r--r-- | c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup_asm.S | 11 |
2 files changed, 1 insertions, 12 deletions
diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c b/c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c index 0eba0b7c9e..07b9fd2d50 100644 --- a/c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c +++ b/c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c @@ -233,7 +233,7 @@ unsigned pvr; * for use by assembly code. * Therefore, we compute it here and store it in memory... */ - _CPU_altivec_ctxt_off = (uint32_t) &((Context_Control*)0)->altivec; + _CPU_altivec_ctxt_off = offsetof(ppc_context, altivec); /* * Add space possibly needed for alignment */ diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup_asm.S b/c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup_asm.S index 6b78c0b5eb..1a5c906de3 100644 --- a/c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup_asm.S +++ b/c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup_asm.S @@ -623,17 +623,6 @@ _CPU_load_altivec_volatile: #endif blr - .global _CPU_Context_restore_altivec -_CPU_Context_restore_altivec: - /* Restore is like 'switch' but we don't have - * to save an old context. - * Move argument to second arg and load NULL pointer - * to first one, then jump to 'switch' routine. - */ - mr r4, r3 - li r3, 0 - b _CPU_Context_switch_altivec - .global _CPU_Context_switch_altivec _CPU_Context_switch_altivec: |