Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step.  It
copied header files from arbitrary locations into the build tree.  The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

* The make preinstall step itself needs time and disk space.

* Errors in header files show up in the build tree copy.  This makes it
  hard for editors to open the right file to fix the error.

* There is no clear relationship between source and build tree header
  files.  This makes an audit of the build process difficult.

* The visibility of all header files in the build tree makes it
  difficult to enforce API barriers.  For example it is discouraged to
  use BSP-specifics in the cpukit.

* An introduction of a new build system is difficult.

* Include paths specified by the -B option are system headers.  This
  may suppress warnings.

* The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step.   All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc.  Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

* cpukit/include

* cpukit/score/cpu/@RTEMS_CPU@/include

* cpukit/libnetworking

The new BSP include directories are:

* bsps/include

* bsps/@RTEMS_CPU@/include

* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed.  The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

5 files changed, 0 insertions, 1135 deletions

diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.h b/c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.h
deleted file mode 100644
index dd0c483b0d..0000000000
--- a/c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * raw_execption.h
- *
- *	    This file contains implementation of C function to
- *          Instantiate mpc5xx primary exception entries.
- *	    More detailled information can be found on the Motorola
- *	    site and more precisely in the following book:
- *
- *		MPC555/MPC556 User's Manual
- *		Motorola REF : MPC555UM/D Rev. 3, 2000 October 15
- *
- *
- *  MPC5xx port sponsored by Defence Research and Development Canada - Suffield
- *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
- *
- *  Derived from libcpu/powerpc/mpc8xx/exceptions/raw_exception.h:
- *
- *  Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
- *                     Canon Centre Recherche France.
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _LIBCPU_RAW_EXCEPTION_H
-#define _LIBCPU_RAW_EXCEPTION_H
-
-#include <libcpu/vectors.h>
-
-/*
- * Exception Vectors as defined in the MPC555 User's Manual
- */
-
-#define	ASM_RESET_VECTOR 	0x01
-#define	ASM_MACH_VECTOR		0x02
-
-#define	ASM_EXT_VECTOR 		0x05
-#define	ASM_ALIGN_VECTOR 	0x06
-#define	ASM_PROG_VECTOR		0x07
-#define	ASM_FLOAT_VECTOR	0x08
-#define	ASM_DEC_VECTOR		0x09
-
-#define	ASM_SYS_VECTOR		0x0C
-#define	ASM_TRACE_VECTOR	0x0D
-#define	ASM_FLOATASSIST_VECTOR	0x0E
-
-#define	ASM_SOFTEMUL_VECTOR	0x10
-
-#define	ASM_IPROT_VECTOR	0x13
-#define	ASM_DPROT_VECTOR	0x14
-
-#define ASM_DBREAK_VECTOR	0x1C
-#define ASM_IBREAK_VECTOR	0x1D
-#define ASM_MEBREAK_VECTOR	0x1E
-#define ASM_NMEBREAK_VECTOR	0x1F
-
-#define LAST_VALID_EXC		ASM_NMEBREAK_VECTOR
-
-#ifndef ASM
-
-/*
- * Type definition for raw exceptions.
- */
-
-typedef unsigned char  rtems_vector;
-struct 	__rtems_raw_except_connect_data__;
-typedef unsigned char 	rtems_raw_except_hdl_size;
-
-typedef struct {
-  rtems_vector			vector;
-  rtems_exception_handler_t*	raw_hdl;
-}rtems_raw_except_hdl;
-
-typedef void (*rtems_raw_except_enable)		(const struct __rtems_raw_except_connect_data__*);
-typedef void (*rtems_raw_except_disable)	(const struct __rtems_raw_except_connect_data__*);
-typedef int  (*rtems_raw_except_is_enabled)	(const struct __rtems_raw_except_connect_data__*);
-
-typedef struct __rtems_raw_except_connect_data__{
- /*
-  * Exception vector (As defined in the manual)
-  */
-  rtems_vector			exceptIndex;
-  /*
-   * Exception raw handler. See comment on handler properties below in function prototype.
-   */
-  rtems_raw_except_hdl	   	hdl;
-  /*
-   * function for enabling raw exceptions. In order to be consistent
-   * with the fact that the raw connexion can defined in the
-   * libcpu library, this library should have no knowledge of
-   * board specific hardware to manage exceptions and thus the
-   * "on" routine must enable the except at processor level only.
-   *
-   */
-    rtems_raw_except_enable	on;
-  /*
-   * function for disabling raw exceptions. In order to be consistent
-   * with the fact that the raw connexion can defined in the
-   * libcpu library, this library should have no knowledge of
-   * board specific hardware to manage exceptions and thus the
-   * "on" routine must disable the except both at device and PIC level.
-   *
-   */
-  rtems_raw_except_disable	off;
-  /*
-   * function enabling to know what exception may currently occur
-   */
-  rtems_raw_except_is_enabled	isOn;
-}rtems_raw_except_connect_data;
-
-typedef struct {
-  /*
-   * size of all the table fields (*Tbl) described below.
-   */
-  unsigned int	 			exceptSize;
-  /*
-   * Default handler used when disconnecting exceptions.
-   */
-  rtems_raw_except_connect_data		defaultRawEntry;
-  /*
-   * Table containing initials/current value.
-   */
-  rtems_raw_except_connect_data*	rawExceptHdlTbl;
-}rtems_raw_except_global_settings;
-
-/*
- * C callable function enabling to set up one raw idt entry
- */
-extern int mpc5xx_set_exception (const rtems_raw_except_connect_data*);
-
-/*
- * C callable function enabling to get one current raw idt entry
- */
-extern int mpc5xx_get_current_exception (rtems_raw_except_connect_data*);
-
-/*
- * C callable function enabling to remove one current raw idt entry
- */
-extern int mpc5xx_delete_exception (const rtems_raw_except_connect_data*);
-
-/*
- * C callable function enabling to check if vector is valid
- */
-extern int mpc5xx_vector_is_valid(rtems_vector vector);
-
-inline static  void* mpc5xx_get_vector_addr(rtems_vector vector)
-{
-  return ((void*)  (((unsigned) vector) << 8));
-}
-/*
- * Exception global init.
- */
-extern int mpc5xx_init_exceptions (rtems_raw_except_global_settings* config);
-extern int mpc5xx_get_exception_config (rtems_raw_except_global_settings** config);
-
-# endif /* ASM */
-
-#define SIZEOF_
-
-#endif
diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/include/console.h b/c/src/lib/libcpu/powerpc/mpc5xx/include/console.h
deleted file mode 100644
index c0633af938..0000000000
--- a/c/src/lib/libcpu/powerpc/mpc5xx/include/console.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- *  Console declarations
- *
- *
- *  MPC5xx port sponsored by Defence Research and Development Canada - Suffield
- *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _MPC5XX_CONSOLE_H
-#define _MPC5XX_CONSOLE_H
-
-#include <rtems/libio.h>
-#include <rtems/termiostypes.h>
-
-void m5xx_uart_initialize(int minor);
-
-/* Termios callbacks */
-int m5xx_uart_firstOpen(int maj, int min, void *arg);
-int m5xx_uart_lastClose(int maj, int min, void *arg);
-int m5xx_uart_pollRead(int minor);
-ssize_t m5xx_uart_pollWrite(int minor, const char* buf, size_t len);
-ssize_t m5xx_uart_write    (int minor, const char *buf, size_t len);
-int m5xx_uart_setAttributes(int, const struct termios* t);
-
-#define NUM_PORTS	2	/* number of serial ports */
-
-#define SCI1_MINOR	0
-#define SCI2_MINOR	1
-
-#endif /* _MPC5XX_CONSOLE_H */
diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/include/mpc5xx.h b/c/src/lib/libcpu/powerpc/mpc5xx/include/mpc5xx.h
deleted file mode 100644
index fc9b756cbf..0000000000
--- a/c/src/lib/libcpu/powerpc/mpc5xx/include/mpc5xx.h
+++ /dev/null
@@ -1,626 +0,0 @@
-/*
- *
- * MPC5xx Internal I/O Definitions
- */
-
-/*
- *  MPC5xx port sponsored by Defence Research and Development Canada - Suffield
- *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
- *
- *  Derived from c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h:
- *
- *  Submitted By:                                                        *
- *                                                                       *
- *      W. Eric Norum                                                    *
- *      Saskatchewan Accelerator Laboratory                              *
- *      University of Saskatchewan                                       *
- *      107 North Road                                                   *
- *      Saskatoon, Saskatchewan, CANADA                                  *
- *      S7N 5C6                                                          *
- *                                                                       *
- *      eric@skatter.usask.ca                                            *
- *                                                                       *
- *  Modified for use with the MPC860 (original code was for MC68360)     *
- *  by                                                                   *
- *      Jay Monkman                                                      *
- *      Frasca International, Inc.                                       *
- *      906 E. Airport Rd.                                               *
- *      Urbana, IL, 61801                                                *
- *                                                                       *
- *      jmonkman@frasca.com                                              *
- *                                                                       *
- *  Modified further for use with the MPC821 by:                         *
- *      Andrew Bray <andy@chaos.org.uk>                                  *
- *                                                                       *
- *  With some corrections/additions by:                                  *
- *      Darlene A. Stewart and                                           *
- *      Charles-Antoine Gauthier                                         *
- *      Institute for Information Technology                             *
- *      National Research Council of Canada                              *
- *      Ottawa, ON  K1A 0R6                                              *
- *                                                                       *
- *      Darlene.Stewart@iit.nrc.ca                                       *
- *      charles.gauthier@iit.nrc.ca                                      *
- *                                                                       *
- *      Corrections/additions:                                           *
- *        Copyright (c) 1999, National Research Council of Canada        *
- *
- *  MPC5xx port sponsored by Defence Research and Development Canada - Suffield
- *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _MPC5XX_H
-#define _MPC5XX_H
-
-#include <libcpu/spr.h>
-
-
-#ifndef ASM
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * Macros for accessing Special Purpose Registers (SPRs)
- */
-
-#define _eieio   __asm__ volatile ("eieio\n"::)
-#define _sync    __asm__ volatile ("sync\n"::)
-#define _isync   __asm__ volatile ("isync\n"::)
-
-/*
- * Core Registers (SPRs)
- */
-#define DER             149     /* Debug Enable Register */
-#define IMMR            638     /* Internal Memory Map Register */
-#define IMMR_FLEN	(1<<11)	   /* Internal flash ROM enabled */
-
-/*
- * Interrupt Control Registers (SPRs)
- */
-#define EIE              80     /* External Interrupt Enable Register */
-#define EID              81     /* External Interrupt Disable Register */
-#define NRI              82     /* Non-Recoverable Interrupt Register */
-
-#define ECR             148     /* Exception Cause Register */
-
-/*
- * Bus Control Registers (SPRs)
- */
-#define LCTRL1          156     /* L-Bus Support Control Register 1 */
-#define LCTRL2          157     /* L-Bus Support Control Register 2 */
-#define ICTRL           158     /* I-Bus Support Control Register */
-
-/*
- * Burst Buffer Control Registers (SPRs)
- */
-#define BBCMCR          560     /* Burst Buffer Configuration Register */
-#define BBCMCR_BE       (1<<13) /* Burst enable */
-#define BBCMCR_ETRE     (1<<12) /* Exception table relocation enable */
-
-#define MI_RBA0         784     /* Region 0 Address Register */
-#define MI_RBA1         785     /* Region 1 Address Register */
-#define MI_RBA2         786     /* Region 2 Address Register */
-#define MI_RBA3         787     /* Region 3 Address Register */
-
-#define MI_RA0          816     /* Region 0 Attribute Register */
-#define MI_RA1          817     /* Region 1 Attribute Register */
-#define MI_RA2          818     /* Region 2 Attribute Register */
-#define MI_RA3          819     /* Region 3 Attribute Register */
-#define MI_GRA          528     /* Region Global Attribute Register */
-#define MI_RA_PP	(3 << 10)	/* Protection bits: */
-#define MI_RA_PP_SUPV	(1 << 10)	/*   Supervisor */
-#define MI_RA_PP_USER	(2 << 10)	/*   User */
-#define MI_RA_G		(1 << 6)	/* Guarded region */
-
-
-/*
- * L-Bus to U-Bus Interface (L2U) Registers (SPRs)
- */
-#define L2U_MCR         568     /* L2U Module Configuration Register */
-
-#define L2U_RBA0        792     /* L2U Region 0 Address Register */
-#define L2U_RBA1        793     /* L2U Region 1 Address Register */
-#define L2U_RBA2        794     /* L2U Region 2 Address Register */
-#define L2U_RBA3        795     /* L2U Region 3 Address Register */
-
-#define L2U_RA0         824     /* L2U Region 0 Attribute Register */
-#define L2U_RA1         825     /* L2U Region 1 Attribute Register */
-#define L2U_RA2         826     /* L2U Region 2 Attribute Register */
-#define L2U_RA3         827     /* L2U Region 3 Attribute Register */
-#define L2U_GRA         536     /* L2U Global Region Attribute Register */
-#define L2U_RA_PP	(3 << 10)	/* Protection bits: */
-#define L2U_RA_PP_SUPV	(1 << 10)	/*   Supervisor */
-#define L2U_RA_PP_USER	(2 << 10)	/*   User */
-#define L2U_RA_G	(1 << 6)	/* Guarded region */
-
-
-/*
- *************************************************************************
- *                         REGISTER SUBBLOCKS                            *
- *************************************************************************
- */
-
-/*
- *************************************************************************
- *                 System Protection Control Register (SYPCR)            *
- *************************************************************************
- */
-#define USIU_SYPCR_SWTC(x)      ((x)<<16)   /* Software watchdog timer count */
-#define USIU_SYPCR_BMT(x)       ((x)<<8)    /* Bus monitor timing */
-#define USIU_SYPCR_BME          (1<<7)      /* Bus monitor enable */
-#define USIU_SYPCR_SWF          (1<<3)      /* Software watchdog freeze */
-#define USIU_SYPCR_SWE          (1<<2)      /* Software watchdog enable */
-#define USIU_SYPCR_SWRI         (1<<1)      /* Watchdog reset/interrupt sel. */
-#define USIU_SYPCR_SWP          (1<<0)      /* Software watchdog prescale */
-
-#define USIU_SYPCR_BMT(x)       ((x)<<8)    /* Bus monitor timing */
-#define USIU_SYPCR_BME          (1<<7)      /* Bus monitor enable */
-#define USIU_SYPCR_SWF          (1<<3)      /* Software watchdog freeze */
-#define USIU_SYPCR_SWE          (1<<2)      /* Software watchdog enable */
-#define USIU_SYPCR_SWRI         (1<<1)      /* Watchdog reset/interrupt sel. */
-#define USIU_SYPCR_SWP          (1<<0)      /* Software watchdog prescale */
-
-/*
- *************************************************************************
- *                 Software Service Register (SWSR)                      *
- *************************************************************************
- */
-#define TICKLE_WATCHDOG()		\
-do {					\
-  usiu.swsr = 0x556C;			\
-  usiu.swsr = 0xAA39;			\
-} while (0)				\
-
-/*
- *************************************************************************
- *                        Memory Control Registers                       *
- *************************************************************************
- */
-#define USIU_MEMC_BR_BA(x)      (((uint32_t)x)&0xffff8000)
-					 /* Base address */
-#define USIU_MEMC_BR_AT(x)      ((x)<<12) /* Address type */
-#define USIU_MEMC_BR_PS8        (1<<10)  /* 8 bit port */
-#define USIU_MEMC_BR_PS16       (2<<10)  /* 16 bit port */
-#define USIU_MEMC_BR_PS32       (0<<10)  /* 32 bit port */
-#define USIU_MEMC_BR_WP         (1<<8)   /* Write protect */
-#define USIU_MEMC_BR_WEBS       (1<<5)   /* Write enable/byte select */
-#define USIU_MEMC_BR_TBDIP      (1<<4)   /* Toggle-Burst data in progress*/
-#define USIU_MEMC_BR_LBDIP      (1<<3)   /* Late-burst data in progress */
-#define USIU_MEMC_BR_SETA       (1<<2)   /* External transfer acknowledge */
-#define USIU_MEMC_BR_BI         (1<<1)   /* Burst inhibit */
-#define USIU_MEMC_BR_V          (1<<0)   /* Base/Option register are valid */
-
-#define USIU_MEMC_OR_32K        0xffff8000      /* Address range */
-#define USIU_MEMC_OR_64K        0xffff0000
-#define USIU_MEMC_OR_128K       0xfffe0000
-#define USIU_MEMC_OR_256K       0xfffc0000
-#define USIU_MEMC_OR_512K       0xfff80000
-#define USIU_MEMC_OR_1M         0xfff00000
-#define USIU_MEMC_OR_2M         0xffe00000
-#define USIU_MEMC_OR_4M         0xffc00000
-#define USIU_MEMC_OR_8M         0xff800000
-#define USIU_MEMC_OR_16M        0xff000000
-#define USIU_MEMC_OR_32M        0xfe000000
-#define USIU_MEMC_OR_64M        0xfc000000
-#define USIU_MEMC_OR_128        0xf8000000
-#define USIU_MEMC_OR_256M       0xf0000000
-#define USIU_MEMC_OR_512M       0xe0000000
-#define USIU_MEMC_OR_1G         0xc0000000
-#define USIU_MEMC_OR_2G         0x80000000
-#define USIU_MEMC_OR_4G         0x00000000
-#define USIU_MEMC_OR_ATM(x)     ((x)<<12)   /* Address type mask */
-#define USIU_MEMC_OR_CSNT       (1<<11)     /* Chip select is negated early */
-#define USIU_MEMC_OR_ACS_NORM   (0<<9)      /* *CS asserted with addr lines */
-#define USIU_MEMC_OR_ACS_QRTR   (2<<9)      /* *CS asserted 1/4 after addr */
-#define USIU_MEMC_OR_ACS_HALF   (3<<9)      /* *CS asserted 1/2 after addr */
-#define USIU_MEMC_OR_ETHR       (1<<8)      /* Extended hold time on reads */
-#define USIU_MEMC_OR_SCY(x)     ((x)<<4)    /* Cycle length in clocks */
-#define USIU_MEMC_OR_BSCY(x)    ((x)<<1)    /* Burst beat length in clocks */
-#define USIU_MEMC_OR_TRLX       (1<<0)      /* Relaxed timing in GPCM */
-
-/*
- *************************************************************************
- *                      Clocks and Reset Controlmer                      *
- *************************************************************************
- */
-
-#define USIU_SCCR_DBCT          (1<<31)    /* Disable backup clock for timers */
-#define USIU_SCCR_COM(x)	((x)<<29)  /* Clock output mode */
-#define USIU_SCCR_RTDIV         (1<<24)    /* RTC, PIT divide by 256, not 4 */
-#define USIU_PRQEN              (1<<21)    /* MSR[POW] controls frequency */
-#define USIU_SCCR_EBDF(x)       ((x)<<17)  /* External bus division factor */
-#define USIU_LME                (1<<16)    /* Enable limp mode */
-#define USIU_ENGDIV(x)          ((x)<<9)   /* Set engineering clock divisor */
-
-#define USIU_PLPRCR_MF(x)	(((x)-1)<<20)	/* PLL mult. factor (true) */
-#define USIU_PLPRCR_SPLS        (1<<16)    /* System PLL locked */
-#define	USIU_PLPRCR_TEXPS	(1<<14)    /* Assert TEXP always */
-
-/*
- *************************************************************************
- *                      Programmable Interval Timer                      *
- *************************************************************************
- */
-#define USIU_PISCR_PIRQ(x)      (1<<(15-x))  /* PIT interrupt level */
-#define USIU_PISCR_PS           (1<<7)    /* PIT Interrupt state */
-#define USIU_PISCR_PIE          (1<<2)    /* PIT interrupt enable */
-#define USIU_PISCR_PITF         (1<<1)    /* Stop timer when freeze asserted */
-#define USIU_PISCR_PTE          (1<<0)    /* PIT enable */
-
-/*
- *************************************************************************
- *                             Time Base                                 *
- *************************************************************************
- */
-#define USIU_TBSCR_TBIRQ(x)     (1<<(15-x))  /* TB interrupt level */
-#define USIU_TBSCR_REFA         (1<<7)    /* TB matches TBREFF0 */
-#define USIU_TBSCR_REFB         (1<<6)    /* TB matches TBREFF1 */
-#define USIU_TBSCR_REFAE        (1<<3)    /* Enable ints for REFA */
-#define USIU_TBSCR_REFBE        (1<<2)    /* Enable ints for REFB */
-#define USIU_TBSCR_TBF          (1<<1)    /* TB stops on FREEZE */
-#define USIU_TBSCR_TBE          (1<<0)    /* enable TB and decrementer */
-
-/*
- *************************************************************************
- *                       SIU Interrupt Mask                              *
- *************************************************************************
- */
-#define USIU_SIMASK_IRM0        (1<<31)
-#define USIU_SIMASK_LVM0        (1<<30)
-#define USIU_SIMASK_IRM1        (1<<29)
-#define USIU_SIMASK_LVM1        (1<<28)
-#define USIU_SIMASK_IRM2        (1<<27)
-#define USIU_SIMASK_LVM2        (1<<26)
-#define USIU_SIMASK_IRM3        (1<<25)
-#define USIU_SIMASK_LVM3        (1<<24)
-#define USIU_SIMASK_IRM4        (1<<23)
-#define USIU_SIMASK_LVM4        (1<<22)
-#define USIU_SIMASK_IRM5        (1<<21)
-#define USIU_SIMASK_LVM5        (1<<20)
-#define USIU_SIMASK_IRM6        (1<<19)
-#define USIU_SIMASK_LVM6        (1<<18)
-#define USIU_SIMASK_IRM7        (1<<17)
-#define USIU_SIMASK_LVM7        (1<<16)
-
-/*
- *************************************************************************
- *                       SIU Module Control                              *
- *************************************************************************
- */
-#define USIU_SIUMCR_EARB        (1<<31)
-#define USIU_SIUMCR_EARP0       (0<<28)
-#define USIU_SIUMCR_EARP1       (1<<28)
-#define USIU_SIUMCR_EARP2       (2<<28)
-#define USIU_SIUMCR_EARP3       (3<<28)
-#define USIU_SIUMCR_EARP4       (4<<28)
-#define USIU_SIUMCR_EARP5       (5<<28)
-#define USIU_SIUMCR_EARP6       (6<<28)
-#define USIU_SIUMCR_EARP7       (7<<28)
-#define USIU_SIUMCR_DSHW        (1<<23)
-#define USIU_SIUMCR_DBGC0       (0<<21)
-#define USIU_SIUMCR_DBGC1       (1<<21)
-#define USIU_SIUMCR_DBGC2       (2<<21)
-#define USIU_SIUMCR_DBGC3       (3<<21)
-#define USIU_SIUMCR_DBPC        (1<<20)
-#define USIU_SIUMCR_ATWC        (1<<19)
-#define USIU_SIUMCR_GPC0        (0<<17)
-#define USIU_SIUMCR_GPC1        (1<<17)
-#define USIU_SIUMCR_GPC2        (2<<17)
-#define USIU_SIUMCR_GPC3        (3<<17)
-#define USIU_SIUMCR_DLK         (1<<16)
-#define USIU_SIUMCR_SC0         (0<<13)
-#define USIU_SIUMCR_SC1         (1<<13)
-#define USIU_SIUMCR_SC2         (2<<13)
-#define USIU_SIUMCR_SC3         (3<<13)
-#define USIU_SIUMCR_RCTX        (1<<12)
-#define USIU_SIUMCR_MLRC0       (0<<10)
-#define USIU_SIUMCR_MLRC1       (1<<10)
-#define USIU_SIUMCR_MLRC2       (2<<10)
-#define USIU_SIUMCR_MLRC3       (3<<10)
-#define USIU_SIUMCR_MTSC        (1<<7)
-
-/*
- *  Value to write to a key register to unlock the corresponding SIU register
- */
-#define USIU_UNLOCK_KEY         0x55CCAA33
-
-/*
- *************************************************************************
- *                       UIMB Module Control                             *
- *************************************************************************
- */
-#define UIMB_UMCR_STOP          (1<<31)
-#define UIMB_UMCR_IRQMUX(x)     ((x)<<29)
-#define UIMB_UMCR_HSPEED        (1<<28)
-
-/*
- *************************************************************************
- *              QSMCM Serial Communications Interface (SCI)              *
- *************************************************************************
- */
-
-
-#define QSMCM_ILDSCI(x)        ((x)<<8)    /* SCI interrupt level */
-
-#define QSMCM_SCI_BAUD(x)      ((x)&0x1FFF) /* Baud rate field */
-
-#define QSMCM_SCI_LOOPS        (1<<14)     /* Loopback test mode */
-#define QSMCM_SCI_WOMS         (1<<13)     /* Wire-or mode select */
-#define QSMCM_SCI_ILT          (1<<12)     /* Idle-line detect type */
-#define QSMCM_SCI_PT           (1<<11)     /* Parity type */
-#define QSMCM_SCI_PE           (1<<10)     /* Parity enable */
-#define QSMCM_SCI_M            (1<<9)      /* 11-bit mode */
-#define QSMCM_SCI_WAKE         (1<<8)      /* Wakeup mode */
-
-#define QSMCM_SCI_TIE          (1<<7)      /* Transmitter interrupt enable */
-#define QSMCM_SCI_TCIE         (1<<6)      /* Transmit complete intr. enable */
-#define QSMCM_SCI_RIE          (1<<5)      /* Receiver interrupt enable */
-#define QSMCM_SCI_ILIE         (1<<4)      /* Idle line interrupt enable */
-#define QSMCM_SCI_TE           (1<<3)      /* Transmitter enable */
-#define QSMCM_SCI_RE           (1<<2)      /* Receiver enable */
-#define QSMCM_SCI_RWU          (1<<1)      /* Receiver wake-up enable */
-#define QSMCM_SCI_SBK          (1<<0)      /* Send break */
-
-#define QSMCM_SCI_TDRE         (1<<8)      /* Transmit data register empty */
-#define QSMCM_SCI_TC           (1<<7)      /* Transmit complete */
-#define QSMCM_SCI_RDRF         (1<<6)      /* Receive data register full */
-#define QSMCM_SCI_RAF          (1<<5)      /* Receiver active flag */
-#define QSMCM_SCI_IDLE         (1<<4)      /* Idle line detected */
-#define QSMCM_SCI_OR           (1<<3)      /* Receiver overrun error */
-#define QSMCM_SCI_NF           (1<<2)      /* Receiver noise error flag */
-#define QSMCM_SCI_FE           (1<<1)      /* Receiver framing error */
-#define QSMCM_SCI_PF           (1<<0)      /* Receiver parity error */
-
-/*
- *************************************************************************
- *   Unified System Interface Unit                                       *
- *************************************************************************
- */
-
-/*
- * Memory controller registers
- */
-typedef struct m5xxMEMCRegisters_ {
-  uint32_t        _br;
-  uint32_t        _or;    /* Used to be called 'or'; reserved ANSI C++ keyword */
-} m5xxMEMCRegisters_t;
-
-/*
- * USIU itself
- */
-typedef struct usiu_ {
-  /*
-   * SIU Block
-   */
-  uint32_t      siumcr;
-  uint32_t      sypcr;
-  uint32_t      _pad70;
-  uint16_t      _pad0;
-  uint16_t      swsr;
-  uint32_t      sipend;
-  uint32_t      simask;
-  uint32_t      siel;
-  uint32_t      sivec;
-  uint32_t      tesr;
-  uint32_t      sgpiodt1;
-  uint32_t      sgpiodt2;
-  uint32_t      sgpiocr;
-  uint32_t      emcr;
-  uint8_t	_pad71[0x03C-0x034];
-  uint32_t      pdmcr;
-  uint8_t       _pad2[0x100-0x40];
-
-  /*
-   * MEMC Block
-   */
-  m5xxMEMCRegisters_t   memc[4];
-  uint8_t       _pad7[0x140-0x120];
-  uint32_t      dmbr;
-  uint32_t      dmor;
-  uint8_t       _pad8[0x178-0x148];
-  uint16_t      mstat;
-  uint8_t       _pad9[0x200-0x17A];
-
-  /*
-   * System integration timers
-   */
-  uint16_t      tbscr;
-  uint16_t      _pad10;
-  uint32_t      tbreff0;
-  uint32_t      tbreff1;
-  uint8_t       _pad11[0x220-0x20c];
-  uint16_t      rtcsc;
-  uint16_t      _pad12;
-  uint32_t      rtc;
-  uint32_t      rtsec;
-  uint32_t      rtcal;
-  uint32_t      _pad13[4];
-  uint16_t      piscr;
-  uint16_t      _pad14;
-  uint16_t      pitc;
-  uint16_t      _pad_14_1;
-  uint16_t      pitr;
-  uint16_t      _pad_14_2;
-  uint8_t       _pad15[0x280-0x24c];
-
-  /*
-   * Clocks and Reset
-   */
-  uint32_t      sccr;
-  uint32_t      plprcr;
-  uint16_t      rsr;
-  uint16_t	_pad72;
-  uint16_t	colir;
-  uint16_t	_pad73;
-  uint16_t	vsrmcr;
-  uint8_t       _pad16[0x300-0x292];
-
-  /*
-   * System integration timers keys
-   */
-  uint32_t      tbscrk;
-  uint32_t      tbreff0k;
-  uint32_t      tbreff1k;
-  uint32_t      tbk;
-  uint32_t      _pad17[4];
-  uint32_t      rtcsk;
-  uint32_t      rtck;
-  uint32_t      rtseck;
-  uint32_t      rtcalk;
-  uint32_t      _pad18[4];
-  uint32_t      piscrk;
-  uint32_t      pitck;
-  uint8_t       _pad19[0x380-0x348];
-
-  /*
-   * Clocks and Reset Keys
-   */
-  uint32_t      sccrk;
-  uint32_t      plprck;
-  uint32_t      rsrk;
-  uint8_t       _pad20[0x400-0x38c];
-} usiu_t;
-
-extern volatile usiu_t usiu;	/* defined in linkcmds */
-
-/*
- *************************************************************************
- *   Inter-Module Bus and Devices                                        *
- *************************************************************************
- */
-
-/*
- * Dual-Port TPU RAM (DPTRAM)
- */
-typedef struct m5xxDPTRAMRegisters_ {
-  uint8_t	pad[0x4000];		/* define later */
-} m5xxDPTRAMRegisters_t;
-
-/*
- * Time Processor Unit (TPU)
- */
-typedef struct m5xxTPU3Registers_ {
-  uint8_t	pad[0x400];		/* define later */
-} m5xxTPU3Registers_t;
-
-/*
- * Queued A/D Converter (QADC)
- */
-typedef struct m5xxQADC64Registers_ {
-  uint8_t	pad[0x400];		/* define later */
-} m5xxQADC64Registers_t;
-
-/*
- * Serial Communications Interface (SCI)
- */
-typedef struct m5xxSCIRegisters_ {
-  uint16_t        sccr0;
-  uint16_t        sccr1;
-  uint16_t        scsr;
-  uint16_t        scdr;
-} m5xxSCIRegisters_t;
-
-/*
- * Serial Peripheral Interface (SPI)
- */
-typedef struct m5xxSPIRegisters_ {
-  uint16_t        spcr0;
-  uint16_t        spcr1;
-  uint16_t        spcr2;
-  uint8_t         spcr3;
-  uint8_t         spsr;
-} m5xxSPIRegisters_t;
-
-/*
- * Queued Serial Multi-Channel Module (QSMCM)
- */
-typedef struct m5xxQSMCMRegisters_ {
-  uint16_t      qsmcmmcr;
-  uint16_t      qtest;
-  uint16_t      qdsci_il;
-  uint16_t      qspi_il;
-
-  m5xxSCIRegisters_t    sci1;
-
-  uint8_t       _pad10[0x14-0x10];
-
-  uint16_t      portqs;
-  uint16_t      pqspar;
-  m5xxSPIRegisters_t    spi;
-
-  m5xxSCIRegisters_t    sci2;
-
-  uint16_t      qsci1cr;
-  uint16_t      qsci1sr;
-  uint16_t      sctq[0x10];
-  uint16_t      scrq[0x10];
-
-  uint8_t       _pad6C[0x140-0x06C];
-
-  uint16_t      recram[0x20];
-  uint16_t      tranram[0x20];
-  uint16_t      comdram[0x20];
-} m5xxQSMCMRegisters_t;
-
-/*
- * Modular Input/Output System (MIOS)
- */
-typedef struct m5xxMIOS1Registers_ {
-  uint8_t	pad[0x1000];		/* define later */
-} m5xxMIOS1Registers_t;
-
-/*
- * Can 2.0B Controller (TouCAN)
- */
-typedef struct m5xxTouCANRegisters_ {
-  uint8_t	pad[0x400];		/* define later */
-} m5xxTouCANRegisters_t;
-
-/*
- * U-Bus to IMB3 Bus Interface Module (UIMB)
- */
-typedef struct m5xxUIMBRegisters_ {
-  uint32_t      umcr;
-  uint32_t      utstcreg;
-  uint32_t      uipend;
-} m5xxUIMBRegisters_t;
-
-/*
- * IMB itself
- */
-typedef struct imb_ {
-  m5xxDPTRAMRegisters_t	dptram;
-  m5xxTPU3Registers_t	tpu[2];
-  m5xxQADC64Registers_t	qadc[2];
-  m5xxQSMCMRegisters_t	qsmcm;
-  uint8_t       _pad5200[0x6000-0x5200];
-  m5xxMIOS1Registers_t	mios;
-  m5xxTouCANRegisters_t	toucan[2];
-  uint8_t       _pad7800[0x7F80-0x7800];
-  m5xxUIMBRegisters_t	uimb;
-} imb_t;
-
-extern volatile imb_t imb;		/* defined in linkcmds */
-
-
-/*
- * Methods shared across libcpu and the BSP.
- */
-void clockOn(void* unused);
-void clockOff(void* unused);
-int clockIsOn(void* unused);
-rtems_isr Clock_isr(rtems_vector_number vector);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ASM */
-
-#endif /* _MPC5XX_H */
diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h
deleted file mode 100644
index ab06041d24..0000000000
--- a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * irq.h
- *
- *  This include file describe the data structure and the functions implemented
- *  by rtems to write interrupt handlers.
- *
- *
- *  MPC5xx port sponsored by Defence Research and Development Canada - Suffield
- *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
- *
- *  Derived from libbsp/powerpc/mbx8xx/irq/irq.h:
- *
- *  CopyRight (C) 1999 valette@crf.canon.fr
- *
- *  This code is heavilly inspired by the public specification of STREAM V2
- *  that can be found at :
- *
- *      <http://www.chorus.com/Documentation/index.html> by following
- *  the STREAM API Specification Document link.
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _LIBCPU_IRQ_H
-#define _LIBCPU_IRQ_H
-
-#include <rtems/irq.h>
-
-#define CPU_ASM_IRQ_VECTOR_BASE 0x0
-
-#ifndef ASM
-
-extern volatile unsigned int ppc_cached_irq_mask;
-
-/*
- * Symblolic IRQ names and related definitions.
- */
-
-  /*
-   * Base vector for our USIU IRQ handlers.
-   */
-#define CPU_USIU_VECTOR_BASE	(CPU_ASM_IRQ_VECTOR_BASE)
-  /*
-   * USIU IRQ handler related definitions
-   */
-#define CPU_USIU_IRQ_COUNT    	(16) /* 16 reserved but in the future... */
-#define CPU_USIU_IRQ_MIN_OFFSET	(0)
-#define CPU_USIU_IRQ_MAX_OFFSET	(CPU_USIU_IRQ_MIN_OFFSET + CPU_USIU_IRQ_COUNT - 1)
-  /*
-   * UIMB IRQ handlers related definitions
-   */
-#define CPU_UIMB_IRQ_COUNT	(32 - 8) /* first 8 overlap USIU */
-#define CPU_UIMB_IRQ_MIN_OFFSET	(CPU_USIU_IRQ_COUNT + CPU_USIU_VECTOR_BASE)
-#define CPU_UIMB_IRQ_MAX_OFFSET	(CPU_UIMB_IRQ_MIN_OFFSET + CPU_UIMB_IRQ_COUNT - 1)
-  /*
-   * PowerPc exceptions handled as interrupt where a rtems managed interrupt
-   * handler might be connected
-   */
-#define CPU_PROC_IRQ_COUNT	(1)
-#define CPU_PROC_IRQ_MIN_OFFSET	(CPU_UIMB_IRQ_MAX_OFFSET + 1)
-#define CPU_PROC_IRQ_MAX_OFFSET	(CPU_PROC_IRQ_MIN_OFFSET + CPU_PROC_IRQ_COUNT - 1)
-  /*
-   * Summary
-   */
-#define CPU_IRQ_COUNT		(CPU_PROC_IRQ_MAX_OFFSET + 1)
-#define CPU_MIN_OFFSET		(CPU_USIU_IRQ_MIN_OFFSET)
-#define CPU_MAX_OFFSET		(CPU_PROC_IRQ_MAX_OFFSET)
-  /*
-   * USIU IRQ symbolic name definitions.
-   */
-#define CPU_USIU_EXT_IRQ_0      (CPU_USIU_IRQ_MIN_OFFSET + 0)
-#define CPU_USIU_INT_IRQ_0      (CPU_USIU_IRQ_MIN_OFFSET + 1)
-
-#define CPU_USIU_EXT_IRQ_1      (CPU_USIU_IRQ_MIN_OFFSET + 2)
-#define CPU_USIU_INT_IRQ_1      (CPU_USIU_IRQ_MIN_OFFSET + 3)
-
-#define CPU_USIU_EXT_IRQ_2      (CPU_USIU_IRQ_MIN_OFFSET + 4)
-#define CPU_USIU_INT_IRQ_2      (CPU_USIU_IRQ_MIN_OFFSET + 5)
-
-#define CPU_USIU_EXT_IRQ_3      (CPU_USIU_IRQ_MIN_OFFSET + 6)
-#define CPU_USIU_INT_IRQ_3      (CPU_USIU_IRQ_MIN_OFFSET + 7)
-
-#define CPU_USIU_EXT_IRQ_4      (CPU_USIU_IRQ_MIN_OFFSET + 8)
-#define CPU_USIU_INT_IRQ_4      (CPU_USIU_IRQ_MIN_OFFSET + 9)
-
-#define CPU_USIU_EXT_IRQ_5      (CPU_USIU_IRQ_MIN_OFFSET + 10)
-#define CPU_USIU_INT_IRQ_5      (CPU_USIU_IRQ_MIN_OFFSET + 11)
-
-#define CPU_USIU_EXT_IRQ_6      (CPU_USIU_IRQ_MIN_OFFSET + 12)
-#define CPU_USIU_INT_IRQ_6      (CPU_USIU_IRQ_MIN_OFFSET + 13)
-
-#define CPU_USIU_EXT_IRQ_7      (CPU_USIU_IRQ_MIN_OFFSET + 14)
-#define CPU_USIU_INT_IRQ_7      (CPU_USIU_IRQ_MIN_OFFSET + 15)
-
-  /*
-   * Symbolic names for UISU interrupt sources.
-   */
-#define CPU_PERIODIC_TIMER	(CPU_USIU_INT_IRQ_6)
-#define CPU_UIMB_INTERRUPT	(CPU_USIU_INT_IRQ_7)
-
-  /*
-   * UIMB IRQ symbolic name definitions.  The first 8 sources are aliases to
-   * the USIU interrupts of the same number, because they are detected in
-   * the USIU pending register rather than the UIMB pending register.
-   */
-#define CPU_UIMB_IRQ_0 		(CPU_USIU_INT_IRQ_0)
-#define CPU_UIMB_IRQ_1 		(CPU_USIU_INT_IRQ_1)
-#define CPU_UIMB_IRQ_2 		(CPU_USIU_INT_IRQ_2)
-#define CPU_UIMB_IRQ_3 		(CPU_USIU_INT_IRQ_3)
-#define CPU_UIMB_IRQ_4 		(CPU_USIU_INT_IRQ_4)
-#define CPU_UIMB_IRQ_5 		(CPU_USIU_INT_IRQ_5)
-#define CPU_UIMB_IRQ_6 		(CPU_USIU_INT_IRQ_6)
-#define CPU_UIMB_IRQ_7 		(CPU_USIU_INT_IRQ_7)
-
-#define CPU_UIMB_IRQ_8         	(CPU_UIMB_IRQ_MIN_OFFSET+ 0)
-#define CPU_UIMB_IRQ_9          (CPU_UIMB_IRQ_MIN_OFFSET+ 1)
-#define CPU_UIMB_IRQ_10         (CPU_UIMB_IRQ_MIN_OFFSET+ 2)
-#define CPU_UIMB_IRQ_11         (CPU_UIMB_IRQ_MIN_OFFSET+ 3)
-#define CPU_UIMB_IRQ_12         (CPU_UIMB_IRQ_MIN_OFFSET+ 4)
-#define CPU_UIMB_IRQ_13         (CPU_UIMB_IRQ_MIN_OFFSET+ 5)
-#define CPU_UIMB_IRQ_14         (CPU_UIMB_IRQ_MIN_OFFSET+ 6)
-#define CPU_UIMB_IRQ_15         (CPU_UIMB_IRQ_MIN_OFFSET+ 7)
-#define CPU_UIMB_IRQ_16         (CPU_UIMB_IRQ_MIN_OFFSET+ 8)
-#define CPU_UIMB_IRQ_17         (CPU_UIMB_IRQ_MIN_OFFSET+ 9)
-#define CPU_UIMB_IRQ_18         (CPU_UIMB_IRQ_MIN_OFFSET+ 0)
-#define CPU_UIMB_IRQ_19         (CPU_UIMB_IRQ_MIN_OFFSET+11)
-#define CPU_UIMB_IRQ_20         (CPU_UIMB_IRQ_MIN_OFFSET+12)
-#define CPU_UIMB_IRQ_21         (CPU_UIMB_IRQ_MIN_OFFSET+13)
-#define CPU_UIMB_IRQ_22         (CPU_UIMB_IRQ_MIN_OFFSET+14)
-#define CPU_UIMB_IRQ_23         (CPU_UIMB_IRQ_MIN_OFFSET+15)
-#define CPU_UIMB_IRQ_24         (CPU_UIMB_IRQ_MIN_OFFSET+16)
-#define CPU_UIMB_IRQ_25         (CPU_UIMB_IRQ_MIN_OFFSET+17)
-#define CPU_UIMB_IRQ_26         (CPU_UIMB_IRQ_MIN_OFFSET+18)
-#define CPU_UIMB_IRQ_27         (CPU_UIMB_IRQ_MIN_OFFSET+19)
-#define CPU_UIMB_IRQ_28         (CPU_UIMB_IRQ_MIN_OFFSET+20)
-#define CPU_UIMB_IRQ_29         (CPU_UIMB_IRQ_MIN_OFFSET+21)
-#define CPU_UIMB_IRQ_30         (CPU_UIMB_IRQ_MIN_OFFSET+22)
-#define CPU_UIMB_IRQ_31         (CPU_UIMB_IRQ_MIN_OFFSET+23)
-
-  /*
-   * Symbolic names for UIMB interrupt sources.
-   */
-#define CPU_IRQ_SCI		(CPU_UIMB_IRQ_5)
-
-  /*
-   * Processor exceptions handled as rtems IRQ symbolic name definitions.
-   */
-#define CPU_DECREMENTER		(CPU_PROC_IRQ_MIN_OFFSET)
-
-/*
- * Convert an rtems_irq_number constant to an interrupt level
- * suitable for programming into an I/O device's interrupt level field.
- */
-int CPU_irq_level_from_symbolic_name(const rtems_irq_number name);
-
-/*-------------------------------------------------------------------------+
-| Function Prototypes.
-+--------------------------------------------------------------------------*/
-
-extern void CPU_rtems_irq_mng_init(unsigned cpuId);
-
-typedef struct MPC5XX_Interrupt_frame {
-    uint32_t   stacklink;	/* Ensure this is a real frame (also reg1 save) */
-    uint32_t   calleeLr;	/* link register used by callees: SVR4/EABI */
-
-    /* This is what is left out of the primary contexts */
-    uint32_t   gpr0;
-    uint32_t   gpr2;		/* play safe */
-    uint32_t   gpr3;
-    uint32_t   gpr4;
-    uint32_t   gpr5;
-    uint32_t   gpr6;
-    uint32_t   gpr7;
-    uint32_t   gpr8;
-    uint32_t   gpr9;
-    uint32_t   gpr10;
-    uint32_t   gpr11;
-    uint32_t   gpr12;
-    uint32_t   gpr13;   /* Play safe */
-    uint32_t   gpr28;   /* For internal use by the IRQ handler */
-    uint32_t   gpr29;   /* For internal use by the IRQ handler */
-    uint32_t   gpr30;   /* For internal use by the IRQ handler */
-    uint32_t   gpr31;   /* For internal use by the IRQ handler */
-    uint32_t   cr;	/* Bits of this are volatile, so no-one may save */
-    uint32_t   ctr;
-    uint32_t   xer;
-    uint32_t   lr;
-    uint32_t   pc;
-    uint32_t   msr;
-    uint32_t   pad[3];
-} MPC5XX_Interrupt_frame;
-
-void C_dispatch_irq_handler(MPC5XX_Interrupt_frame *frame, unsigned int excNum);
-
-#endif
-
-#endif
diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h b/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h
deleted file mode 100644
index 2c8914e2a4..0000000000
--- a/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * vectors.h Exception frame related contant and API.
- *
- *  This include file describe the data structure and the functions implemented
- *  by rtems to handle exceptions.
- *
- *
- *  MPC5xx port sponsored by Defence Research and Development Canada - Suffield
- *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
- *
- *  Derived from libbsp/powerpc/mbx8xx/vectors/vectors.h:
- *
- *  CopyRight (C) 1999 valette@crf.canon.fr
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-#ifndef _LIBCPU_VECTORS_H
-#define _LIBCPU_VECTORS_H
-
-
-/*
- * Size of hardware vector table.
- */
-#define NUM_EXCEPTIONS		0x20
-
-/*
- * The callee (high level exception code written in C)
- * will store the Link Registers (return address) at entry r1 + 4 !!!.
- * So let room for it!!!.
- */
-#define LINK_REGISTER_CALLEE_UPDATE_ROOM 4
-#define SRR0_FRAME_OFFSET 8
-#define SRR1_FRAME_OFFSET 12
-#define EXCEPTION_NUMBER_OFFSET 16
-#define EXC_CR_OFFSET 20
-#define EXC_CTR_OFFSET 24
-#define EXC_XER_OFFSET 28
-#define EXC_LR_OFFSET 32
-#define GPR0_OFFSET 36
-#define GPR1_OFFSET 40
-#define GPR2_OFFSET 44
-#define GPR3_OFFSET 48
-#define GPR4_OFFSET 52
-#define GPR5_OFFSET 56
-#define GPR6_OFFSET 60
-#define GPR7_OFFSET 64
-#define GPR8_OFFSET 68
-#define GPR9_OFFSET 72
-#define GPR10_OFFSET 76
-#define GPR11_OFFSET 80
-#define GPR12_OFFSET 84
-#define GPR13_OFFSET 88
-#define GPR14_OFFSET 92
-#define GPR15_OFFSET 96
-#define GPR16_OFFSET 100
-#define GPR17_OFFSET 104
-#define GPR18_OFFSET 108
-#define GPR19_OFFSET 112
-#define GPR20_OFFSET 116
-#define GPR21_OFFSET 120
-#define GPR22_OFFSET 124
-#define GPR23_OFFSET 128
-#define GPR24_OFFSET 132
-#define GPR25_OFFSET 136
-#define GPR26_OFFSET 140
-#define GPR27_OFFSET 144
-#define GPR28_OFFSET 148
-#define GPR29_OFFSET 152
-#define GPR30_OFFSET 156
-#define GPR31_OFFSET 160
-/*
- * maintain the EABI requested 8 bytes aligment
- * As SVR4 ABI requires 16, make it 16 (as some
- * exception may need more registers to be processed...)
- */
-#define    EXCEPTION_FRAME_END 176
-
-#ifndef ASM
-
-#include <rtems.h>
-
-/*
- * default raw exception handlers
- */
-
-extern	void default_exception_vector_code_prolog(void);
-extern	int  default_exception_vector_code_prolog_size;
-extern  void initialize_exceptions(void);
-
-typedef void rtems_exception_handler_t (CPU_Exception_frame* excPtr);
-/*DEBUG typedef rtems_exception_handler_t cpuExcHandlerType; */
-
-/*
- * Exception handler table.
- *
- * This table contains pointers to assembly-language exception handlers.
- * The common exception prologue in vectors.S looks up an entry in this
- * table and jumps to it.  No return address is saved, so the handlers in
- * this table must return directly to the interrupted code.
- *
- * On entry to an exception handler, R1 points to a new exception stack
- * frame in which R3, R4, and LR have been saved.  R4 holds the exception
- * number.
- */
-extern rtems_exception_handler_t* exception_handler_table[NUM_EXCEPTIONS];
-
-/* for compatability -- XXX remove */
-typedef rtems_exception_handler_t *cpuExcHandlerType;
-extern cpuExcHandlerType *globalExceptHdl;
-
-#endif /* ASM */
-
-#endif /* _LIBCPU_VECTORS_H */