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| author | Joel Sherrill <joel.sherrill@oarcorp.com> | 2014-10-14 14:10:22 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@oarcorp.com> | 2014-10-16 08:58:47 -0500 |
| commit | f62c7daa6482d74bb9b5275d8d4cc5c487ff9081 (patch) | |
| tree | c3c5cb24b170a5d8c05d668028aa48c275fe17f5 /c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c | |
| parent | mcf5282: Move cache to libcpu and update av5282 and uC5282 BSPs (diff) | |
| download | rtems-f62c7daa6482d74bb9b5275d8d4cc5c487ff9081.tar.bz2 | |
mpc5xx libcpu and ss555 BSP: Fix warnings
Diffstat (limited to '')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c index 7b9cfd079d..3ba7e8f505 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c +++ b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c @@ -3,8 +3,9 @@ * * This file contains the implementation of rtems initialization * related to interrupt handling. - * - * + */ + +/* * MPC5xx port sponsored by Defence Research and Development Canada - Suffield * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) * @@ -89,7 +90,7 @@ static rtems_irq_prio irqPrioTable[CPU_IRQ_COUNT]={ 0 }; -void CPU_USIU_irq_init(void) +static void CPU_USIU_irq_init(void) { /* * In theory we should initialize two registers at least : SIMASK and @@ -106,8 +107,7 @@ void CPU_USIU_irq_init(void) /* * Initialize UIMB interrupt management */ -void -CPU_UIMB_irq_init(void) +static void CPU_UIMB_irq_init(void) { } |