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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2002-05-14 16:56:44 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2002-05-14 16:56:44 +0000 |
| commit | 0d776cd24743625f2888d04d72188b2e3f416a3e (patch) | |
| tree | 3f146379e2bd7bdd9f4ee85485fb5039fc036b71 /c/src/lib/libcpu/powerpc/ChangeLog | |
| parent | 2001-05-14 Till Straumann <strauman@slac.stanford.edu> (diff) | |
| download | rtems-0d776cd24743625f2888d04d72188b2e3f416a3e.tar.bz2 | |
2001-05-14 Till Straumann <strauman@slac.stanford.edu>
* rtems/powerpc/registers.h, rtems/score/ppc.h: Per PR213, add
the following:
- support for the MPC74000 (AKA G4); there is no
AltiVec support yet, however.
- the cache flushing assembly code uses hardware-flush on the G4.
Also, a couple of hardcoded numerical values were replaced
by more readable symbolic constants.
- extended interrupt-disabled code section so enclose the entire
cache flush/invalidate procedure (as recommended by the book).
This is not (latency) critical as it is only used by
init code but prevents possible corruption.
- Trivial page table support as been added.
(1:1 effective-virtual-physical address mapping which is only
useful only on CPUs which feature hardware TLB replacement,
e.g. >604. This allows for write-protecting memory regions,
e.g. text/ro-data which makes catching corruptors a lot easier.
It also frees one DBAT/IBAT and gives more flexibility
for setting up address maps :-)
- setdbat() allows changing BAT0 also (since the BSP may use
a page table, BAT0 could be available...).
- asm_setdbatX() violated the SVR ABI by using
r20 as a scratch register; changed for r0
- according to the book, a context synchronizing instruction is
necessary prior to and after changing a DBAT -> isync added
Diffstat (limited to 'c/src/lib/libcpu/powerpc/ChangeLog')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/ChangeLog | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/powerpc/ChangeLog b/c/src/lib/libcpu/powerpc/ChangeLog index d67f245378..96eba47501 100644 --- a/c/src/lib/libcpu/powerpc/ChangeLog +++ b/c/src/lib/libcpu/powerpc/ChangeLog @@ -1,3 +1,30 @@ +2001-05-14 Till Straumann <strauman@slac.stanford.edu> + + * rtems/powerpc/registers.h, rtems/score/ppc.h: Per PR213, add + the following: + - support for the MPC74000 (AKA G4); there is no + AltiVec support yet, however. + - the cache flushing assembly code uses hardware-flush on the G4. + Also, a couple of hardcoded numerical values were replaced + by more readable symbolic constants. + - extended interrupt-disabled code section so enclose the entire + cache flush/invalidate procedure (as recommended by the book). + This is not (latency) critical as it is only used by + init code but prevents possible corruption. + - Trivial page table support as been added. + (1:1 effective-virtual-physical address mapping which is only + useful only on CPUs which feature hardware TLB replacement, + e.g. >604. This allows for write-protecting memory regions, + e.g. text/ro-data which makes catching corruptors a lot easier. + It also frees one DBAT/IBAT and gives more flexibility + for setting up address maps :-) + - setdbat() allows changing BAT0 also (since the BSP may use + a page table, BAT0 could be available...). + - asm_setdbatX() violated the SVR ABI by using + r20 as a scratch register; changed for r0 + - according to the book, a context synchronizing instruction is + necessary prior to and after changing a DBAT -> isync added + 2002-04-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de> * rtems/powerpc/cache.h: New file (extracted from |